DS1248YP-70 [ARTSCHIP]
NV SRAM with Phantom Clock;
| 型号： | DS1248YP-70 |
| 厂家： | 
Artschip |
| 描述： | NV SRAM with Phantom Clock PC 双倍数据速率 静态存储器 外围集成电路 |
| 文件： | 总15页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
FEATURES
PIN CONFIGURATIONS
z Real-Time Clock (RTC) Keeps Track of Hundredths of
Seconds, Minutes, Hours, Days, Date of the Month, Months,
and Years
TOP VIEW
z 128k x 8 NV SRAM Directly Replaces Volatile Static RAM or
EEPROM
z Embedded Lithium Energy Cell Maintains Calendar
Operation and Retains RAM Data
z Watch Function is Transparent to RAM Operation
z Month and Year Determine the Number of Days in Each
Month; Valid Up to 2100
z Full 10% Operating Range
z Operating Temperature Range:0℃ to +70℃
z Over 10 Years of Data Retention in the Absence of Power
z Lithium Energy Source is Electrically Disconnected to
Retain Freshness Until Power is Applied for the First Time
z DIP Module Only
z Standard 32-Pin JEDEC Pinout
z PowerCap ® Module Board Only
Surface Mountable Package for Direct
Connection to PowerCap Containing
Encapsulated DIP
(740-mil Flush)
Battery and Crystal
Replaceable Battery (PowerCap)
Pin-for-Pin Compatible with DS1244P and DS1251P
PowerCap Module Board
(Uses DS9034PCX PowerCap)
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1
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
ORDERING INFORMATION
PART
TEMP RANGE
Vcc RANGE
5V ±10%
5V ±10%
5V±10%
PIN-PACKAGE
32 EDIP
TOP MARK***
DS1248Y-70
DS1248Y-70
0℃ to +70℃
-40℃ to +85℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
-40℃ to +85℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
-40℃ to +85℃
DS1248Y-70IND
DS1248Y-100IND
DS1248YP-70
32 EDIP
DS1248Y-70 IND
DS1248Y-100 IND
DS1248YP-70
32 EDIP
5V±10%
34 PowerCap*
32 EDIP
DS1248W-120
3.3V±10%
3.3V ±10%
3.3V±10%
3.3V±10%
5V ±10%
5V ±10%
5V ±10%
5V ±10%
3.3V±10%
3.3V±10%
3.3V±10%
3.3V±10%
DS1248W-120
DS1248W-120 IND
DS1248WP-120
DS1248WP-120**
DS1248Y-70
DS1248W-120IND
DS1248WP-120
DS1248WP-120IND
DS1248Y-70+
32 EDIP
34 PowerCap*
34 PowerCap*
32 EDIP
DS1248Y-70IND+
DS1248Y-100IND+
DS1248YP-70+
DS1248W-120+
DS1248W-120IND+
DS1248W-120+
DS1248W-120IND+
32 EDIP
DS1248Y-70 IND
DS1248W-100 IND
DS1248Y-70
32 EDIP
34 PowerCap*
32 EDIP
DS1248W-120
DS1248W-120 IND
DS1248W-120
DS1248WP-120**
32 EDIP
34 PowerCap*
34 PowerCap*
*DS9034PCX (PowerCap) Required, order separately.
**An “IND” is located in the lower right-hand corner of the label.
***A ‘+’ indicates lead-free. The top mark will include a “+” symbol on lead-free devices.
DETAILED DESCRIPTION
The DS1248 1024k NV SRAM with phantom clock is a fully static, nonvolatile RAM (organized as 128k words by 8 bits) with a
built-in real-time clock. The DS1248 has a self-contained lithium energy source and control circuitry, which constantly monitors
Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and
writes protection is unconditionally enabled to prevent garbled data in both the memory and real-time clock.
PACKAGES
The DS1248 is available in two packages:32-pin DIP and 34-pin PowerCap module. The 32-pin DIP style module integrates the
crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module board is designed with contacts for
connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be
mounted on top of the DS1248P after completion of the surface mount process. Mounting the PowerCap after the surface mount
process prevents damage to the crystal and battery because of the high temperatures required for solder reflow. The PowerCap is
keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered separately and shipped in separate
containers.
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DS1248/DS1248P
1024K NV SRAM with Phantom Clock
PIN DESCRIPTION
PIN
NAME
FUNCTION
EDIP
PowerCap
1
1
Active-Low Reset Input. This pin has an internal pullup resistor connected to Vcc.
2
3
A16
3
32
30
25
24
23
22
21
20
19
18
28
29
27
26
31
2
A14
A12
A7
4
5
6
A6
7
A5
8
A4
9
A3
Address Inputs
10
11
12
23
25
26
27
28
31
13
14
15
17
18
19
20
21
22
24
29
30
32
16
A2
A1
A0
A10
A11
A9
A8
A13
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
16
15
14
13
12
11
10
9
Data In/Data Out
8
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
No Connect
7
6
4,33,34
5
N.C.
Vcc
Power-Supply Input
17
GND
Ground
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DS1248/DS1248P
1024K NV SRAM with Phantom Clock
RAM READ MODE
The DS1248 executes a read cycle whenever
(write enable) is inactive (high) and
(Chip enable) is active (low). The
unique address specified by the 17 address inputs (A0-A16) defines which of the 128k bytes of data is to be accessed. Valid data
will be available to the eight data-output drives within tACC (access time) after the last address input signal is stable, providing the
and
data access must be measured from the later occurring signal (
for , rather than address access.
(Output enable) access times and states are also satisfied. If
and
access times are not satisfied, then
or tOE
or ) and the limiting parameter is either tCO for
RAM WRITE MODE
The DS1248 is in the write mode whenever the
and
signals are in the active (low) state after address inputs are stable.
The latter occurring falling edge of
earlier rising edge of or . All address inputs must be kept valid throughout the write cycle.
state for a minimum recovery time (tWR) before another cycle can be initiated. The
or
will determine the start of the write cycle. The write cycle is terminated by the
must return to the high
control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output bus has been enabled (
disable the outputs in tODW from its falling edge.
and
active) then
will
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when Vcc is greater than VPF. However, when Vcc is below
the power-fail point, VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any
access. When Vcc falls below the battery switch point, Vso (battery supply level), device power is switched from the Vcc pin to the
backup battery. RTC operation and SRAM data are maintained from the battery until Vcc is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when Vcc is greater than VPF. When Vcc falls below VPF
,
access to the device is inhibited. If VPF is less than VBAT, the device power is switched from Vcc to the backup supply (VBAT) when
Vcc drops below VPF. If VPF is greater than VBAT, the device power is switched from Vcc to the backup supply (VBAT) when Vcc
drops below VBAT. RTC operation and SRAM data are maintained from the battery until Vcc is returned to nominal levels.
All control, data, and address signals must be powered down when Vcc is powered-down.
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits, which must be
matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses that occur prior to recognition
of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory
access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable, output
enable, and write enable. Initially, a read cycle to any memory location using the
the pattern recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write
cycles are executed using the and control of the Smart Watch. These 64 write cycles are used only to gain access to the
and
control of the phantom clock starts
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain
access to the phantom clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement
is to set aside just one address location in RAM as a phantom clock scratch pad. When be first write cycle is executed, it is
compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write
cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the
comparison register is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the
comparison register have been matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data
transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either receive or
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DS1248/DS1248P
1024K NV SRAM with Phantom Clock
transmit data on DQ0, depending on the level of the
pin or the
pin. Cycles to other locations outside the memory block
can be interleaved with
phantom clock.
cycles without interrupting the pattern recognition sequence or data transfer sequence to the
PHANTOM CLOCK PEGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after
the 64-bit pattern recognition sequence has been completed. When updating the phantom clock registers, each register must be
handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/Write
registers defined in Figure 2.
Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and writing the registers is always
accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7.
Figure 1. Phantom Clock Register Definition
NOTE: THE PATTERN RECOGNITION IN HEX IX C5,3A, 5C, C5, 3A, A3,5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY
DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN 1019. THIS PATTERN IS SENT TO THE
PHANTOM CLOCK LSB TO MSB.
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DS1248/DS1248P
1024K NV SRAM with Phantom Clock
Figure 2. Phantom Clock Register Definition
AM/PM/12/24-MODE
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the
12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
bit is set to logic 1, the
and oscillator functions. Bit 4 controls the
bit is set to logic 0, a low input on the
(pin 1). When the
pin will cause
input pin is ignored. When the
the phantom clock to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator. When set to
logic 1, the oscillator is off. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch
becomes operational. These bits are shipped from the factory set to logic 1.
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DS1248/DS1248P
1024K NV SRAM with Phantom Clock
ZERO BITS
Registers 1,2,3,4,5 and 6 contain one or more bits, which will always read logic 0 . when writing these locations, either a logic 1 or
0 is acceptable.
BATTERY LONGEVITY
The DS1248 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention
when the Vcc supply is not present. The capability of this internal power supply is sufficient to power the DS1248 continuously for
the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25℃ with the
internal clock oscillator running in the absence of Vcc power. Each DS1248 is shipped from ARTSCHIP Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When Vcc is first applied at a level greater than VPF, the
lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1248 will be much longer than 10
years since no lithium battery energy is consumed when Vcc is present.
CLOCK ACCURACY (DIP MODULE)
The DS1248 is guaranteed to keep time accuracy to within ±1 minute per month at +25℃. The clock is calibrated at the factory by
ARTSCHIP Semiconductor using special calibration nonvolatile tuning elements and does not require additional calibration. For
this reason, methods of field clock calibration are not available and not necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1248P and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep
time accuracy to within ±1.53 minutes per month (35ppm) at +25℃.
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………………………-0.3V to +6.0V
Storage Temperature Range………………………………………………………………………………………..-40℃ to +85℃
Soldering Temperature………………………………………………………………..+260℃ for 10 seconds (EDIP) (Note 13)
See IPC/JEDEC Standard J-STD-020 for
Surface-Mount Devices
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time can affect reliability.
OPERATING RANGE
RANGE
TEMP RANGE
0℃ to +70℃
-40℃ to +85℃
Vcc (V)
Commercial
Industrial
3.3 ±10% or 5 ±10%
3.3 ±10% or 5 ±10%
RECOMMENDED DC OPERATING CONDITIONS
Over the Operating Range
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
2.2
VCC
+
0.3V
Vcc+
0.3V
+0.8
+0.6
Vcc=5V± 10%
Logic 1
VIH
V
11
2.0
Vcc=3.3V± 10%
Vcc=5V± 10%
-0.3
-0.3
Logic
VIL
V
11
Vcc=3.3V± 10%
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DS1248/DS1248P
1024K NV SRAM with Phantom Clock
DC ELECTRICAL CHARACTERISTICS
Over the Operating Range (5V)
PARAMETER
SYMBOL
MIN
-1.0
-1.0
TYP
MAX
+1.0
+1.0
UNITS
µA
NOTES
Input Leakage Current
I/O Leakage Current
12
IIL
µA
IIO
≥ VIH ≤Vcc
Output Current at 2.4V
-1.0
2.0
mA
mA
mA
mA
IOH
Output Current at 0.4V
IOL
5
10
ICCS1
ICCS2
Standby Current
Standby Current
=2.2V
3.0
5.0
=Vcc-0.5V
85
mA
V
Operating Current tCYC=70ns
Write Protection Voltage
Battery Switchover Voltage
ICC01
VPF
4.25
4.37
4.50
11
11
V
VSO
VBAT
DC ELECTRICAL CHARACTERISTICS
Over the Operating Range (3.3V)
PARAMETER
SYMBOL
MIN
-1.0
-1.0
TYP
MAX
+1.0
+1.0
UNITS
µA
NOTES
Input Leakage Current
I/O Leakage Current
12
IIL
µA
IIO
≥ VIH ≤Vcc
Output Current at 2.4V
-1.0
2.0
mA
mA
mA
mA
IOH
Output Current at 0.4V
IOL
5
7
ICCS1
ICCS2
Standby Current
Standby Current
=2.2V
2.0
3.0
=Vcc-0.5V
Operating Current tCYC=70ns
50
mA
V
ICC01
VPF
Write Protection Voltage
2.80
2.86
VBAT or
VPF
2.97
11
11
Battery Switchover Voltage
Vso
V
CAPACITANCE
(TA=+25℃)
PARAMETER
SYMBOL
CIN
MIN
TYP
5
MAX
10
UNITS
pF
NOTES
Input Capacitance
Input/Output Capacitance
5
10
pF
CI/O
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8
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
MEMORY AC ELECTRICAL CHARACTERISTICS
Over the Operating Range (5V)
DS1248-70
PARAMETER
SYMBOL
UNITS
NOTES
MIN
MAX
Read Cycle Time
Access Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
70
35
70
tACC
tOE
to Output Valid
to Output Valid
tCO
5
5
5
tCOE
tOD
or
to Output Active
Output High-Z from Deselection
25
Output Hold from Address change
Write Cycle Time
5
tOH
70
50
0
tWC
tWP
tAW
tWR
tODW
tOEW
tDS
Write Pulse Width
3
Address Setup Time
Write Recovery time
Output High-Z from
Output Active from
0
25
5
5
4
4
5
Data Setup Time
30
5
tDH
Data Hold Time from
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
Over the Operating Range (5V)
PARAMETER
SYMBOL
tRC
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
tCO
Access Time
Access Time
tOE
5
5
tCOE
tOEE
tOD
to Output Low-Z
to Output Low-Z
25
25
5
5
to Output High-Z
to Output High-Z
Read Recovery
Write Cycle Time
Write Pulse Width
Write Recovery
tODO
tRR
10
65
55
10
30
0
tWC
3
tWP
10
4
tWR
Data Setup Time
Data Hold time
tDS
4
tDH
60
65
tCW
Pulse Width
Pulse Width
tRST
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9
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
POWER-DOWN/POWER-UP TIMING
Over the Operating Range (3.3V)
PARAMETER
at VIH before Power-Down
Vcc Slew from VPF(max) to
PF(min)( at VPF)
SYMBOL
tPD
tF
MIN
0
TYP
MAX UNITS
NOTES
µs
µs
300
V
10
0
µs
µs
Vcc Slow from VPF(min) to VSO
Vcc Slow from VPF(max) to
tFB
tR
VPF(min)
(
at VPF)
tREC
1.5
2.5
ms
at VIH after Power-Up
(TA=+25℃)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS
NOTES
Expected Data-Retention Time
10
years
9
tDR
Warning: Under no circumstances are negative undershoots of any amplitude allowed when device is in battery-backup mode.
MEMORY AC ELECTRICAL CHARACTERISTICS
Over the Operating Range (3.3V)
DS1248W-120
PARAMETER
SYMBOL
UNITS
NOTES
MIN
MAX
Read Cycle Time
Access Time
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
120
60
tACC
tOE
to Output Valid
to Output Valid
120
tCO
5
5
5
tCOE
tOD
or
to Output Active
Output High-Z from Deselection
40
Output Hold from Address Change
Write Cycle Time
5
tOH
120
90
0
tWC
tWP
tAW
tWR
tODW
tOEW
tDS
Write Pulse Width
3
Address Setup Time
Write Recovery Time
Output High-Z from
Output Active from
20
10
5
40
5
5
Data Setup Time
50
20
4
4
Data Hold Time from
tDH
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10
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
Over the Operating Range (3.3V)
PARAMETER
SYMBOL
tRC
MIN
TYP
MAX
UNITS
ns
NOTES
Read Cycle Time
120
100
100
ns
tCO
Access Time
Access Time
ns
tOE
5
5
ns
tCOE
tOEE
tOD
to Output Low-Z
to Output Low-Z
ns
40
40
ns
5
5
to Output High-Z
to Output High-Z
Read Recovery
Write Cycle Time
Write Pulse Width
Write Recovery
ns
tODO
tRR
20
ns
120
100
20
ns
tWC
ns
3
tWP
ns
10
4
tWR
Data Setup Time
Data Hold Time
45
ns
tDS
0
ns
4
tDH
105
120
ns
tCW
Pulse Width
Pulse Width
ns
tRST
POWER-DOWN/POWER-UP TIMING
Over the Operating Range (3.3V)
PARAMETER
SYMBOL
MIN
0
TYP
MAX
UNITS
µs
NOTES
tPD
tF
at VIH before Power-Down
Vcc Slew from VPF(MAX) to
300
µs
VPF(MIN)
Vcc Slew from VPF(MAX) to
VPF(MIN) at VIH)
at VIH after Power-Up
(
at VIH)
0
µs
tR
(
1.5
2.5
ms
tREC
(TA=+25℃)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data-Retention Time
10
years
9
tDR
Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
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DS1248/DS1248P
1024K NV SRAM with Phantom Clock
MEMORY READ CYCLE (Note 1)
MEMORY WRITE CYCLE 1 (Notes 2, 6, and 7)
MEMORY WRITE CYCLE 2 (Note 2 and 8)
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12
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
RESET FOR PHANTOM CLOCK
READ CYCLE TO PHANTOM CLOCK
WRITE CYCLE TO PHANTOM CLOCK
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13
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
POWER-DOWN/POWER-UP CONDITION (5V)
POWER-DOWN/POWER-UP CONDITION (3.3V)
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14
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
AC TEST CONDITIONS
Output Load: 50pF +1TTL Gate
Timing Measurement Reference Levels
Input:
1.5V
1.5V
Input Pulse Levels: 0 to 3V
Output:
Input Pulse Rise and Fall Times: 5ns
NOTES:
1)
2)
is high for a read cycle.
=VIH or VIL. If = VIH during write cycle, the output buffers remain in a high impedance state.
3) tWP is specified as the logical AND of
or going high.
4) tDH, tDS are measured from the earlier of
and
. tWP is measured from the latter of
or
going low to the earlier of
and
going high.
5) These parameters are sampled with a 50pF load and are not 100% tested.
6) If the low transition occurs simultaneously with or later than the
remain in a high-impedance state during this period.
low transition in Write Cycle 1, the output buffers
high transition, the output buffers remain in a
low transition occurs prior to or simultaneously with the low transition, the output buffers remain in
7) If the
high transition occurs prior to or simultaneously with the
high-impedance state during this period.
8) If
a high impedance state during this period.
9) The expected tDR is defined as cumulative time in the absence of Vcc with the clock oscillator running.
is low or the
10) tWR is a function of the latter occurring edge of
11) Voltages are referenced to ground.
or
.
12)
(Pin 1) has an internal pullup resistor.
13) RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85℃. Post-solder cleaning with water-washing
techniques is acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for details regarding
the PowerCap package.
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