DS1744P-100 [ARTSCHIP]
Y2K-Compliant, Nonvolatile Timekeeping RAMs;
| 型号： | DS1744P-100 |
| 厂家： | 
Artschip |
| 描述： | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| 文件： | 总19页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
FEATURES
z Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail
Control Circuit, and Lithium Energy Source
z Clock Registers are Accessed Identically to the Static RAM.
These Registers are Resident in the Eight Top RAM
Locations.
PIN CONFIGURATIONS
TOP VIEW
z Century Byte Register (i.e., Y2K Compliant)
z Totally Nonvolatile with Over 10 Years of Operation in the
Absence of Power
z BCD-Coded Century, Year, Month, Date, Day, Hours,
Minutes, and Seconds with Automatic Leap-Year
Compensation Valid Up to the Year 2100
z Battery Voltage-Level Indicator Flag
z Power-Fail Write Protection Allows for ±10% Vcc
Power-Supply Tolerance
z Lithium Energy Source is Electrically Disconnected to
Retain Freshness Until Power is Applied for the First Time
z DIP Module Only
EDIP
Standard JEDEC Byte-Wide 32k x 8 Static RAM Pinout
z PowerCap ® Module Board Only
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities of DS174xP
Timekeeping RAM
z Also Available in Industrial Temperature
Range: -40℃ to +85℃
PowerCap Module BOARD
z UL Recognized
(Uses DS9034PCX PowerCap)
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1
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
PIN
NAME
FUNCTION
PDIP
1
PowerCap
32
30
25
24
23
22
21
20
19
18
28
29
27
26
31
16
15
14
13
12
11
10
9
A14
A12
A7
2
3
4
A6
5
A5
6
A4
7
A3
Address Input
8
A2
9
A1
10
21
23
24
25
26
11
12
13
15
16
17
18
19
14
20
22
27
28
A0
A10
A11
A9
A8
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
Data Input/Output
17
8
Ground
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
Power-Supply Input
7
6
5
Vcc
Active-Low Reset Output, Open Drain. Requires a pullup resistor for
proper operation.
-
4
-
-
1,2,3,33,34
N.C.
No Connection
X1,X2,VBAT
Crystal Connections, VBAT Battery Connection
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
PART
VOLTAGE (V)
TEMP RANGE
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
PIN-PACKAGE
28 EDIP
TOP MARK**
DS1744-70
5.0
5.0
5.0
5.0
3.3
3.3
3.3
5.0
5.0
5.0
5.0
3.3
3.3
3.3
DS1744-70
DS1744-70+
28 EDIP
DS1744+70
DS1744-70IND
DS1744-100+
DS1744W-120
DS1744W-120+
DS1744W-120IND
DS1744P-70
28 EDIP
DS1744-70IND
DS1744 +100
DS1744W -120
DS1744W +120
DS1744W -120IND
DS1744P-70
28 EDIP
28 EDIP
28 EDIP
28 EDIP
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
DS1744P-70+
DS1744P-70IND
DS1744P-100+
DS1744WP-120
DS1744WP-120+
DS1744WP-120IND
DS1744P+70
DS1744P-70IND
DS1744P+100
DS1744WP-120
DS1744WP+120
DS1744WP-120IND
+Denotes a lead-free/RoHS-complient device.
* DS9034-PCX, DS90341-PCX, DS9034-PCX + required (must be ordered separatedly).
** A “+” anywhere in the top mark denotes a lead-free device. An “IND” denotes an industrial temperature grade device.
DESCRIPTION
The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8 NV SRAM. User access
to all registers within the DS1744 is accomplished with a byte-wide interface as shown in Figure 1. The RTC information and
control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made automatically.
The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The
double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data.
The DS1744 also contains its own power-fail circuitry that deselects the device when the VCC supply is in an out-of-tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and
update cycles are avoided.
Figure 1. Block Diagram
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
PACKAGES
The DS1744 is available in two packages (28-pin encapsulated DIP and 34-pin PowerCap module). The 28-pin EDIP module
integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap module board is designed with
contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the
PowerCap to be mounted on top of the DS1744P after the completion of the surface-mount process. Mounting the PowerCap
after the surface-mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered separately
and shipped in separate containers. The part number for the PowerCap is DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1744 clock
registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock
register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the
century register (Table 2). As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is, day, date, and time that was current at the moment the halt command was issued. However, the internal clock
registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All the
DS1744 registers are updated simultaneously after the internal clock-register updating process has been re-enabled. Updating is
within a second after the read bit is written to 0. The READ bit must be a 0 for a minimal of 500µs to ensure the external registers
are updated.
Table 1. Truth Table
VCC
MODE
Deselect
Write
DQ
POWER
VIH
VIL
VIL
VIL
X
X
X
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
Standby
X
VIL
VIH
VIH
X
Active
VCC > VPF
VIL
VIH
X
Read
Active
Read
Active
VSO < VCC < VPF
VCC < VSO < VPF
Deselect
Deselect
CMOS Standby
Data-Retention Mode
X
X
X
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the
DS1744 registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format. Resetting the
write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator can be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain
from the battery. The
bit is the MSB (bit 7) of the seconds registers (Table 2). Setting it to a 1 stops the oscillator.
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is
running, the LSB of the seconds register toggles at 512Hz. When the seconds register is being read, the DQ0 line toggles at the
512Hz frequency as long as conditions for access remain valid (i.e.,
register remain valid and stable).
low,
low,
high, and address for seconds
CLOCK ACCURACY (DIP MODULE)
The DS1744 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is calibrated at the factory by
ARTSCHIP Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason,
methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical
environment; caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional
information, refer to
Application Note 58: Crystal Considerations with ARTSCHIP Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1744 and DS9034PCX are individually tested for accuracy. Once mounted together, the module typically keeps time
accuracy to within ±1.53 minutes per month (35ppm) at +25°C. Clock accuracy is also affected by the electrical environment and
caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer
to Application Note 58: Crystal Considerations with ARTSCHIP Real-Time Clocks.
Table 2. Register Map
DATA
ADDRESS
FUNCTION RANGE
B7
B6
B5
X
B4
B3
B2
B1
B0
7FFF
7FFE
7FFD
7FFC
7FFB
7FFA
7FF9
7FF8
10 Year
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
X
X
X
X
10 Month
10 Date
BF
X
FT
X
X
X
X
Day
Day
10 Hour
Hour
Hour
X
10 Minutes
10 Seconds
Minutes
Minutes
Seconds
Century
OSC
W
Seconds
Century
R
10 Century
= Stop Bit
R=Read Bit
X=See Note
FT=Frequency Test
BF=Battery Flag
W=Write Bit
Note: All indicated “X” bits are not used but must be set to a “0” during write cycle to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever
The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data is available at
the DQ pins within tAA after the last address input is stable, providing that the and access times and states are satisfied.
If or access times and states are not met, valid data is available at the latter of chip-enable access (tCEA) or at
output-enable access time (tOEA). The state of the DQ pins is controlled by and . If the outputs are activated before tAA
the data lines are driven to an intermediate state until tAA. If the address inputs are changed while and remain valid,
(output enable) is low,
(write enable) is high, and
(chip enable) is low.
,
output data remains valid for output-data hold time (tOH) but then goes indeterminate until the next address access.
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever
occurring transition of or . The addresses must be held valid throughout the cycle.
minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain
and
are in their active state. The start of a write is referenced to the latter
or must return inactive for a
valid for tDH afterward. In a typical application, the
signal is high during a write cycle. However,
can be active provided
that care is taken with the data bus to avoid bus contention. If
is low prior to
transitioning low, the data bus can become
active with read data defined by the address inputs. A low transition on
then disables the output tWEZ after
goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below
the power-fail point, VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any
access. At this time the power-fail reset-output signal (
) is driven active and remains active until VCC returns to nominal
levels. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the
backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V
device is fully accessible, and data can be written or read only when VCC is greater than VPF. When VCC falls below VPF access to
the device is inhibited. At this time the power-fail reset-output signal (
nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below
VPF. If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VSO
RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The signal is an
, all control, data, and address signals must be powered down when
) is driven active and remains active until VCC returns to
.
open-drain output and requires a pull up. Except for the
VCC is powered down.
BATTERY LONGEVITY
The DS1744 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention
when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1744 continuously for
the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25°C with the
internal clock oscillator running in the absence of VCC power. Each DS1744 is shipped from ARTSCHIP Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the
lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1744 is much longer than 10 years
since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1744 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of the day register is used to
indicate the voltage-level range of the battery. This bit is not writable and should always be a 1 when read. If a 0 is ever present,
an exhausted lithium energy source is indicated, and both the contents of the RTC and RAM are questionable.
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground………………………………………………………………………..-0.3V to +6.0V
Operating Temperature Range……………………………………………………………………-40℃ to +85℃ (noncondensing)
Storage Temperature Range……………………………………………………………………….-40℃ to +85℃ (noncondensing)
Soldering Temperature………………………………………………….See IPC/JEDEC J-STD-020 Specification (EDIP, Note 7)
This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the
operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time
can affect reliability.
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
OPERATING RANGE
RANGE
TEMP RANGE
Vcc
Commercial
Industrial
0℃ to +70℃, Noncondensing
-40℃ to +85℃. Noncondesning
3.3V ± 10% or 5V ±10%
3.3V ± 10% or 5V ±10%
RECOMMENDED DC OPERATING CONDITIONS
(TA=Over the operating range)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Logic 1 Voltage (All Inputs)
VIH
2.2
VCC + 0.3V
V
1
VCC = 5V ±10%
VIH
2.0
VCC + 0.3V
V
VCC = 3.3V ±10%
Logic 0 Voltage (All Inputs)
CC = 5V ±10% VCC = 3.3V ±10%
VIL
VIL
-0.3
0.3
0.8
0.6
V
V
V
1
DC ELECTRICAL CHARACTERISTICS
(Vcc =5.0V ±10%, TA=Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
75
6
UNITS
mA
NOTES
2, 3
Active Supply Current
ICC
mA
2, 3
ICC1
Icc2
IIL
TTL Standby Current (
= VIH)
≥ VCC - 0.2V)
4
mA
2, 3
CMOS Standby Current (
Input Leakage Current (Any Input)
-1
+1
+1
µA
Output Leakage Current (Any Output)
Output Logic 1 Voltage (IOUT = -1.0mA)
Output Logic 0 Voltage (IOUT = +2.1mA)
Write Protection Voltage
-1
µA
IOL
2.4
1
VOH
VOL
VPF
VSO
0.4
1
4.25
4.50
V
1
Battery Switchover Voltage
VBAT
1, 4
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS
(Vcc = 3.3 V ±10%, TA=Over the operating range.)
PARAMETER
Active Supply Current
SYMBOL
MIN
TYP
MAX
UNITS
mA
NOTES
2, 3
30
2
ICC
mA
mA
µA
2, 3
2, 3
ICC1
ICC2
IIL
TTL Standby Current (
= VIH)
≥ VCC - 0.2V)
2
CMOS Standby Current (
Input Leakage Current (Any Input)
Output Leakage Current (Any Output)
Output Logic 1 Voltage (IOUT = -1.0mA)
Output Logic 0 Voltage (IOUT = +2.1mA)
Write Protection Voltage
-1
+1
+1
-1
µA
IOL
2.4
1
VOH
VOL
VPF
VSO
0.4
1
2.80
2.97
V
V
1
Battery Switchover Voltage
1, 4
VBAT or VPF
AC CHARACTERISTICS-READ CYCLE (5V)
(Vcc =5.0V ±10%, TA = Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
ns
NOTES
Read Cycle Time
Address Access Time
70
tRC
70
ns
tAA
5
ns
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
to DQ Low-Z
Access Time
70
25
ns
ns
Data Off Time
5
5
ns
to DQ Low-Z
35
25
ns
Access Time
ns
Data Off Time
Output Hold from Address
ns
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS-READ CYCLE (3.3V)
(Vcc = 3.3V ±10%, TA=Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Read Cycle Time
Address Access Time
to DQ Low-Z
tRC
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
120
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
5
5
5
Access Time
120
40
Data Off Time
to DQ Low-Z
Access Time
100
35
Data Off Time
Output Hold from Address
READ CYCLE TIMING DIAGRAM
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS-WRITE CYCLE (5V)
(Vcc=5.0V ±10%, TA=Over the operating range.)
PARAMETER
SYMBOL
tWC
MIN
70
0
TYP
MAX
UNITS
ns
NOTES
Write Cycle Time
Address Setup Time
Pulse Width
tAS
ns
tWEW
tCEW
tDS
50
60
30
0
ns
Pulse Width
ns
Data Setup Time
Data Hold Time
Data Hold Time
Address Hold Time
Address Hold Time
Data Off Time
ns
tDH1
ns
8
9
8
9
tDH2
0
ns
tAH1
5
ns
tAH2
5
ns
tWEZ
25
ns
Write Recovery Time
tWR
5
ns
AC CHARACTERISTICS – WRITE CYCLE (3.3V)
(Vcc=3.3V ±10%, TA=Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Write Cycle Time
Address Setup Time
Pulse Width
tWC
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS
120
tWEW
tCEW
tCEW
tDS
100
110
110
80
0
Pulse Width
and CE2 Pulse Width
Data Setup Time
Data Hold Time
Data Hold Time
Address Hold Time
Address Hold Time
Data Off Time
tDH1
tDH2
tAH1
tAH2
tWEZ
tWR
8
9
8
9
0
0
10
40
Write Recovery Time
10
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10
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN AC CHARACTERISTICS (5V)
(Vcc = 5.0V ±10%, TA =Over the operating range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
or
at VIH Before Power-Down
tPD
tF
tFB
tR
tREC
tDR
0
ms
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to VPF(MAX)
Power-Up Recover Time
300
10
0
ms
ms
ms
35
ms
Expected Data-Retention Time (Oscillator ON)
10
years
5, 6
POWER-UP/DOWN TIMING (5V DEVICE)
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS (3.3V)
(Vcc = 3.3V ± 10%, TA = Over the operating range.)
PARAMETER
SYMBOL
tPD
tF
MIN
0
TYP
MAX
UNITS
µs
NOTES
or
at VIH, Before Power-Down
300
0
µs
VCC Fall Time: VPF(MAX) to VPF(MIN)
VCC Rise Time: VPF(MIN) to VPF(MAX)
VPF to RST High
µs
tR
35
ms
tREC
Expected Data-Retention Time (Oscillator ON)
10
years
5, 6
tDR
POWER-UP./DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA=+25℃)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Capacitance On All Input Pins
Capacitance On All Output Pins
CIN
CO
14
10
pF
pF
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25°C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
5) Data-retention time is at +25°C.
6) Each DS1744 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR is
defined for DIP modules and assembled PowerCap modules as a cumulative time in the absence of VCC starting from the time
power is first applied by the user.
7) RTC modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water-washing
techniques is acceptable, provided that ultrasonic vibration is not used.
In addition, for the PowerCap:
a.) ARTSCHIP Semiconductor recommends that PowerCap module bases experience one pass through solder reflow oriented
with the label side up (“live-bug”).
b.) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds. To solder, apply flux
to the pad, heat the lead frame pad, and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder
reflows, and use a solder wick to remove solder.
8) tAH1, tDH1 are measured from
9) tAH2, tDH2 are measured from
going high.
going high.
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
REVISIONS
LTR
DESCRIPTION DATE
APPROVED
A
ECN 35439
ALL DIMENSIONS ARE IN INCHES. SEE PAGE 2 FOR DIMENSIONS IN MM
24 PIN
MIN
28 PIN
MIN
32 PIN 740
MIN
40 PIN 720
MAX
1.340
0.370
0.130
MAX
1.540
0.370
0.130
MAX
1.720
0.370
0.100
MIN
MAX
A
C
D
1.320
0.330
0.100
1.520
0.330
0.100
1.680
2.075
0.280
0.070
2.115
0.320
0.100
0.330
0.070
MIN
MAX
0.72
B
B
0.68
0.720
24 PIN 720, 28 PIN 720 and 40 PIN 720
24 PIN 740, 28 PIN 740 and 32 PIN 740
0.740
ALL PACKAGES
MIN
MAX
E
F
G
H
J
0.010
0.120
0.090
0.590
0.008
0.015
0.040
0.160
0.110
0.630
0.012
0.021
K
www.artschip.com
15
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
REVISIONS
LTR
DESCRIPTION DATE
APPROVED
A
ECN 35439
ALL DIMENSIONS ARE IN MM
24 PIN
28 PIN
MIN
32 PIN 740
MIN
40 PIN 720
MIN
MAX
34.04
9.40
MAX
39.12
9.40
MAX
43.69
9.40
MIN
MAX
A
C
D
33.53
8.38
2.54
38.61
8.38
42.67
8.38
52.71
7.11
1.78
53.72
8.13
2.54
3.30
2.54
3.30
1.78
2.54
MIN
MAX
18.29
18.80
B
B
17.27
18.29
24 PIN 720, 28 PIN 720 and 40 PIN 720
24 PIN 740, 28 PIN 740 and 32 PIN 740
ALL PACKAGES
MIN
0.25
3.05
2.29
14.99
0.20
0.38
MAX
E
F
G
H
J
1.02
4.06
2.79
16.00
0.30
0.53
K
www.artschip.com
16
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.artschip.com
17
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.artschip.com
18
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.artschip.com
19
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