5962-9161706VZX [ATMEL]
Dual-Port SRAM, 8KX16, 45ns, CMOS, 1.150 X 1.150 INCH, MQFP-84;
| 型号： | 5962-9161706VZX |
| 厂家： | 
ATMEL |
| 描述： | Dual-Port SRAM, 8KX16, 45ns, CMOS, 1.150 X 1.150 INCH, MQFP-84 静态存储器 |
| 文件： | 总25页 (文件大小：678K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast access time: 30/45 ns
• Wide temperature range:
– -55°C to +125°C
• Separate upper byte and lower byte control for multiplexed bus compatibility
• Expandable data bus to 32 bits or more using master/slave chip select when using
more than one device
• On chip arbitration logic
• Versatile pin select for master or slave:
– M/S = H for busy output flag on master
– M/S = L for busy input flag on slave
• INT flag for port to port communication
• Full hardware support of semaphore signaling between ports
• Fully asynchronous operation from either port
• Battery back-up operation: 2V data retention
• TTL compatible
Rad Tolerant
High Speed
8 K x 16
• Single 5V + 10% power supply
• QML Q and V with SMD 5962-91617
Dual Port RAM
Introduction
The M67025E is a very low power CMOS dual port static RAM organised as 8192 ×
16. The product is designed to be used as a stand-alone 16 bit dual port RAM or as a
combination MASTER/SLAVE dual port for 32 bit or more width systems. The Atmel
MASTER/SLAVE dual port approach in memory system applications results in full
speed, error free operation without the need of an additional discrete logic.
M67025E
Master and slave devices provide two independant ports with separate control,
address and I/O pins that permit independant, asynchronous access for reads and
writes to any location in the memory. An automatic power down feature controlled by
CS permits the on-chip circuitry of each port in order to enter a very low stand by
power mode.
Using an array of eight transistors (8T) memory cell, the M67025E combines an
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 5 µW.
For military/space applications that demand superior levels of performance and reli-
ability the M67025E is processed according to the methods of the latest revision of the
MIL PRF 38635 (Q and V) and/or ESA SCC 9000.
Rev. H – 21-Aug-01
1
M67025E
Interface
Block Diagram
1. (MASTER): BUSY is output. (SLAVE): BUSY is input.
2. LB = Lower Byte
UB = Upper Byte
Pin Names
LEFT PORT
RIGHT PORT
NAMES
CSL
CSR
Chip select
R/WL
OEL
R/WR
OER
Read/Write Enable
Output Enable
Address
A0L – 12L
I/O0L – 15L
SEML
UBL
A0R – 12R
I/O0R – 15R
SEMR
UBR
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
LBL
LBR
INTL
INTR
BUSYL
BUSYR
M/S
Master or Slave Select
Power
Vcc
GND
Ground
2
Rev. H–21-Aug-01
Functional Description
Functional Description
The M67025E has two ports with separate control, address and I/0 pins that permit inde-
pendent read/write access to any memory location. These devices have an automatic
power-down feature controlled by CS.CS controls on-chip power-down circuitry which
causes the port concerned to go into stand-by mode when not selected (CS high). When
a port is selected access to the full memory array is permitted. Each port has its own
Output Enable control (OE). In read mode, the port’s OE turns the Output drivers on
when set LOW. Non-conflicting READ/WRITE conditions are illustrated in table 1.
The interrupt flag (INT) allows communication between ports or systems. If the user
chooses to use the interrupt function, a memory location (mail box or message center) is
assigned to each port. The left port interrupt flag (INTL) is set when the right port writes
to memory location 1FFE (HEX). The left port clears the interrupt by reading address
location 1FFE. Similarly, the right port interrupt flag (INTR) is set when the left port writes
to memory location 1FFF (HEX), and the right port must read memory location 1FFF in
order to clear the interrupt flag (INTR). The 16 bit message at 1FFE or 1FFF is user-
defined. If the interrupt function is not used, address locations 1FFE and 1FFF are not
reserved for mail boxes but become part of the RAM. See table 3 for the interrupt
function.
Arbitration Logic
Functional Description
The arbitration logic will resolve an address match or a chip select match down to a min-
imum of 5 ns determine which port has access. In all cases, an active BUSY flag will be
set for the inhibited port.
The BUSY flags are required when both ports attempt to access the same location
simultaneously. Should this conflict arise, on-chip arbitration logic will determine which
port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that
3
M67025E
Rev. H – 21-Aug-01
M67025E
allow the processor to hold the operation with its associated address and data. It should
be noted that the operation is invalid for the port for which BUSY is set LOW. The inhib-
ited port will be given access when BUSY goes inactive.
A conflict will occur when both left and right ports are active and the two addresses coin-
cide. The on-chip arbitration determines access in these circumstances. Two modes of
arbitration are provided: (1) if the addresses match and are valid before CS on-chip
control logic arbitrates between CSL and CSR for access ; or (2) if the CSs are low
before an address match, on-chip control logic arbitrates between the left and right
addresses for access (refer to table 4). The inhibited port’s BUSY flag is set and will
reset when the port granted access completes its operation in both arbitration modes.
Data Bus Width
Expansion
Master/Slave Description
Expanding the data bus width to 32 or more bits in a dual-port RAM system means that
several chips may be active simultaneously. If every chips has a hardware arbitrator,
and the addresses for each arrive at the same time one chip may activate in L BUSY
signal while another activates its R BUSY signal. Both sides are now busy and the
CPUs will wait indefinitely for their port to become free.
To overcome this “Busy Lock-Out” problem, Atmel has developped a MASTER/SLAVE
system which uses a single hardware arbitrator located on the MASTER. The SLAVE has
BUSY inputs which allow direct interface to the MASTER with no external components, giving a
speed advantage over other systems.
When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented
from writing until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a
write cycle during a conflict situation. Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is
inherent in all dual-port memory systems where more than one chip is active at the same time.
The write pulse to the SLAVE must be inhibited by the MASTER’s maximum arbitration
time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the
MASTER’s BUSY signal.
Semaphore Logic
Functional Description
The M67025E is an extremely fast dual-port 4k × 16 CMOS static RAM with an additional
locations dedicated to binary semaphore flags. These flags allow either of the processors on the
left or right side of the dual-port RAM to claim priority over the other for functions defined by the
system software. For example, the semaphore flag can be used by oner processor to inhibit the
other from accessing a portion of the dual-port RAM or any other shared resource.
The dual-port RAM has a fast access time, and the two ports are completely indepen-
dent of each another. This means that the activity on the left port cannot slow the access
time of the right port. The ports are identical in function to standard CMOS static RAMs
and can be read from, or written to, at the same time with the only possible conflict aris-
ing from simultaneous writing to, or a simultaneous READ/WRITE operation on, a non-
semaphore location. Semaphores are protected against such ambiguous situations and
may be used by the system program to prevent conflicts in the non-semaphore segment
of the dual-port RAM. The devices have an automatic power-down feature controlled by
CS, the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when
not selected. This conditions is shown in table 1 where CS and SEM are both high.
4
Rev. H–21-Aug-01
Systems best able to exploit the M67025E are based around multiple processors or con-
trollers and are typically very high-speed, software controlled or software-intensive
systems. These systems can benefit from the performance enhancement offered by the
M 67025 hardware semaphores, which provide a lock-out mechanism without the need
for complex programming.
Software handshaking between processors offers the maximum level of system flexibil-
ity by permitting shared resources to be allocated in varying configurations. The
M67025E does not use its semaphore flags to control any resources through hardware,
thus allowing the system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more usual methods of hardware
arbitration is that neither processor ever incurs wait states. This can prove to be a con-
siderable advantage in very high speed systems.
How The Semaphore
Flags Work
The semaphore logic is a set of eight latches independent of the dual-port RAM. These
latches can be used to pass a flag or token, from one port to the other to indicate that a
shared resource is in use. The semaphore provide the hardware context for the “Token
Passing Allocation” method of use assignment. This method uses the state of a sema-
phore latch as a token indicating that a shared resource is in use. If the left processor
needs to use a resource, it requests the token by setting the latch. The processor then
verifies that the latch has been set by reading it. If the latch has been set the processor
assumes control over the shared resource. If the latch has not been set, the left proces-
sor has established that the right processor had set the latch first, has the token and is
using the shared resource. The left processor may then either repeatedly query the sta-
tus of the semaphore, or abandon its request for the token and perform another
operation whilst occasionally attempting to gain control of the token through a set and
test operation. Once the right side has relinquished the token the left side will be able to
take control of the shared resource.
The semaphore flags are active low. A token is requested by writing a zero to a sema-
phore latch, and is relinquished again when the same side writes a one to the latch.
The eight semaphore flags are located in a separate memory space from the dual-port
RAM in the M67025E. The address space is accessed by placing a low input on the
SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins
(address, OE and R/W) as normally used in accessing a standard static RAM. Each of the flags
has a unique address accessed by either side through address pins A0-A2. None of the other
address pins has any effect when accessing the semaphores. Only data pin D0 is used when
writing to a semaphore. If a low level is written to an unused semaphore location, the flag will be
set to zero on that side and to one on the other side (see table 5). The semaphore can now only
be modified by the side showing the zero. Once a one is writen to this location from the same
side, the flag will be set to one for both sides (unless a request is pending from the other side)
and the semaphore can then be written to by either side.
The effect the side writing a zero to a semaphore location has of locking out the other
side is the reason for the use of semaphore logic in interprocessor communication. (A
thorough discussion of the use of this feature follows below). A zero written to the sema-
phore location from the locked-out side will be stored in the semaphore request latch for
that side until the semaphore is relinquished by the side having control. When a sema-
phore flag is read its value is distributed to all data bits so that a flag set at one reads as
one in all data bits and a flag set at zero reads as all zeros. The read value is latched
into the output register of one side when its semaphore select (SEM) and output enable
(OE) signals go active. This prevents the semaphore changing state in the middle of a read
cycle as a result of a write issued by the other side. Because of this latch, a repeated read of a
5
M67025E
Rev. H – 21-Aug-01
M67025E
semaphore flag in a test loop must cause either signal (SEM or OE) to go inactive, otherwise
the output will never change.
The semaphore must use a WRITE/READ sequence in order to ensure that no system
level conflict will occur. A processor requests access to shared resources by attempting
to write a zero to a semaphore location. If the semaphore is already in use, the sema-
phore request latch will contain a zero, yet the semaphore flag will appear as a one, and
the processor will detect this status in the subsequent read (see table 5). For example,
assume a processor writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written successfully to that location
and will assume control over the resource concerned. If a processor on the right side
then attempts to write a zero to the same semaphore flag it will fail, as will be verified by
a subsequent read returning a one from the semaphore location on the right side has a
READ/WRITE sequence been used instead, system conflict problems could have
occurred during the interval between the read and write cycles.
It must be noted that a failed semaphore request needs to be followed by either
repeated reads or by writing a one to the same location. The simple logic diagram for
the semaphore flag in figure 2 illusrates the reason for this quite clearly. Two semaphore
request latches feed into a semaphore flag. The first latch to send a zero to the sema-
phore flag will force its side of the semaphore flag low and other side high. This status
will be maintained until a one is written to the same semaphore request latch. Sould a
zero be written to the other side’s semaphore request latch in the meantime, the sema-
phore flag will flip over to this second side as soon as a one is written to the first side’s
request latch. The second side’s flag will now stay low until its semaphore request latch
is changed to a one. Thus, clearly, if a semaphore flag is requested and the processor
requesting it no longer requires access to the resource, the entire system can hang up
until a one is written to the semaphore request latch concerned.
Semaphore timing becomes critical when both sides request the same token by
attempting to write a zero to it at the same time. Semaphore logic is specially conceived
to resolve this problem. The logic ensures that only one side will receive the token if
simultaneous requests are made. The first side to make a request will receive the token
where request do not arrive at the same time. Where they do arrive at the same time,
the logic will assign the token arbitrarily to one of the ports. It should be noted, however,
that semaphores alone do not guarantee that access to a resource is secure. As with
any powerful programming technique, errors can be introduced if semaphores are mis-
used or misinterpreted. Code integrity is of the utmost performance when semaphores
are being used instead of slower, more restrictive hardware-intensive systems.
Semaphore initialization is not automatic and must therefore be incorporated in the
power up initialization procedures. Since any semaphore flag containing a zero must be
reset to one, initialization should write a one to all request flags from both sides to
ensure that they will be available when required.
Using Semaphores -
Some Examples
Perhaps the simplest application of semaphores is their use as resource markers for the
M67025E’s dual-port RAM. If it is necessary to split the 8 k × 16 RAM into two 4 K × 16
blocks which are to be dedicated to serving either the left or right port at any one time. Sema-
phore 0 can be used to indicate which side is controlling the lower segment of memory and
semaphore 1 can be defined as indicating the upper segment of memory.
To take control of a resource, in this case the lower 4 k of a dual-port RAM, the left port
processor would then write a zero into semaphore flag 0 and then read it back. If suc-
cessful in taking the token (reading back a zero rather than a one), the left processor
could then take control of the lower 4 k of RAM. If the right processor attempts to per-
form the same function to take control of the resource after the left processor has
6
Rev. H–21-Aug-01
already done so, it will read back a one in response to the attempted write of a zero into
semaphore 0. At this point the software may choose to attempt to gain control of the
second 4 k segment of RAM by writing and then reading a zero in semaphore 1. If suc-
cessful, it will lock out the left processor.
Once the left side has completed its task it will write a one to semaphore 0 and may then
attempt to access semaphore 1. If semaphore 1 is still occupied by the right side, the left
side may abandon its semaphore request and perform other operations until it is able to
write and then read a zero in semaphore 1. If the right processor performs the same
operation with semaphore 0, this protocol would then allow the two processes to swap 4
k blocks of dual-port RAM between one another.
The blocks do not have to be any particular size, and may even be of variable size
depending on the complexity of the software using the semaphore flags. All eight sema-
phores could be used to divide the dual-port RAM or other shared resources into eight
parts. Semaphores can even be assigned different meanings on each side, rather than
having a common meaning as is described in the above example.
Semaphores are a useful form of arbitration in systems such as disk interfaces where
the CPU must be locked out of a segment of memory during a data transfer operation,
and the I/0 device cannot tolerate any wait states. If semaphores are used, both the
CPU and the I/0 device can access assigned memory segments, without the need for
wait states, once the two devices have determined which memory area is barred to the
CPU.
Semaphores are also useful in applications where no memory WAIT state is available
on one or both sides. On a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in complex data structures. Block arbitration is very important in
this case, since one processor may be responsible for building and updating a data
structure whilst the other processor reads and interprets it. A major error condition may
be created if the interpreting processor reads an incomplete data structure. Some sort of
arbitration between the two different processors is therefore necessary. The building
processor requests access to the block, locks it and is then able to enter the block to
update the data structure. Once the update is completed the data structure may be
released.
This allows the interpreting processor, to return to read the complete data structure, thus
ensuring a consistent data structure.
7
M67025E
Rev. H – 21-Aug-01
M67025E
Truth Table
Table 1. Non Contention Read/Write Control
Inputs (1)
OE
Outputs
CS
H
X
L
R/W
UB
X
H
H
L
LB
X
H
L
SEM
H
H
H
H
H
H
H
X
IO8-IO15
Hi-Z
I/O0-I/O7
Hi-Z
Mode
X
X
L
X
X
X
X
L
Deselected: Power Down
Deselected: Power Down
Write to Lower Byte Only
Write to Both Bytes
Hi-Z
Hi-Z
Hi-Z
DATAIN
DATAIN
Hi-Z
L
L
L
DATAIN
DATAOUT
Hi-Z
L
H
H
H
X
H
H
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
DATAOUT
DATAOUT
Hi-Z
L
L
L
DATAOUT
Hi-Z
X
H
X
H
X
L
H
L
X
X
H
X
H
L
X
X
H
X
H
X
L
Outputs Disabled
L
DATAOUT
DATAOUT
DATAIN
DATAIN
–
DATAOUT
DATAOUT
DATAIN
DATAIN
–
Read Data in Sema. Flag
Read Data in Sema. Flag
Write DIN0 into Sema. Flag
Write DIN0 into Sema. Flag
Not Allowed
L
L
X
X
X
X
L
L
X
X
L
L
X
L
–
–
Not Allowed
1.AOL - A12 = AOR - A12R
Table 2. Arbitration Options
INPUTS
OUTPUTS
OPTIONS
CS
UB
X
L
LB
L
M/S
H
H
L
SEM
H
BUSY
Output
Signal
Input
Signal
–
INT
Busy Logic Master
L
L
L
L
L
L
H
H
–
X
L
H
Busy Logic Slave
Interrupt Logic
X
L
H
–
–
X
L
L
H
X
L
X
H
Output
Signal
–
X
X
X
X
H
Semaphore Logic*
X
X
H
L
L
H
L
Hi-Z
Note:
* Inputs Signals are for Semaphore Flags set and test (Write and Read) operations.
8
Rev. H–21-Aug-01
Table 3. Interrupt Flag(1, 4)
LEFT PORT
RIGHT PORT
FUNCTION
R/WL
CSL
L
OEL
X
AOL-A12L
1FFF
X
INTL
X
R/WR
CSR
X
OER
X
AOR-A12R
INTR
L(2)
H(3)
X
L
X
X
X
X
X
L
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
X
X
X
L
L
1FFF
1FFE
X
X
X
X
L(3)
H(2)
L
X
L
L
1FFE
X
X
X
X
Reset Left INTL Flag
Notes: 1. Assumes BUSYL = BUSYR = H.
2. If BUSYL = L, then NC.
3. If BUSYR = L, then NC.
4. H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.
Table 4. Arbitration (2)
LEFT PORT
A0L – A12L
RIGHT PORT
FLAGS (1)
FUNCTION
CSL
H
CSR
H
A0R – A12R
BUSYL
BUSYR
X
X
X
H
H
H
H
H
H
H
H
No Contention
L
Any
X
H
No Contention
No Contention
No Contention
H
L
Any
L
≠ A0R – A12R
L
≠ A0L – A12L
ADDRESS ARBITRATION WITH CS LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
RV5L
Same
Same
L
L
L
L
LV5R
RV5L
Same
Same
H
L
L
H
L
L-Port Wins
R-Port Wins
H
L
Arbitration Resolved
Arbitration Resolved
H
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
RL5L
LW5R
LW5R
= A0R – A12R
= A0R – A12R
= A0R – A12R
= A0R – A12R
LL5R
RL5L
LW5R
LW5R
= A0L – A12L
= A0L – A12L
= A0L – A12L
= A0L – A12L
H
L
L
H
L
L-Port Wins
R-Port Wins
H
L
Arbitration Resolved
Arbitration Resolved
H
Notes: 1. INT Flags Don’t Care.
2. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid ≥ 5 ns before right address.
RV5L = Right Address Valid ≥ 5 ns before left address
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW ≥ 5 ns before Right CS.
RL5L = Right CS = LOW ≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
9
M67025E
Rev. H – 21-Aug-01
M67025E
Table 5. Example Semaphore Procurement Sequence
FUNCTION
D0 - D15 LEFT
D0 - D15 RIGHT
STATUS
No Action
1
0
1
1
Semaphore free
Left Port Writes ”0” to Semaphore
Right Port Writes ”0” to Semaphore
Left Port Writes ”1” to Semaphore
Left Port Writes ”0” to Semaphore
Left Port has semaphore token
No change. Right side has no write access
to semaphore
0
1
1
1
0
0
Right port obtains semaphore token
No change. Left port has no write access to
semaphore
Right Port Writes ”1” to Semaphore
Left Port Writes ”1” to Semaphore
Right Port Writes ”0” to Semaphore
Right Port Writes ”1” to Semaphore
Left Port Writes ”0” to Semaphore
Left Port Writes ”1” to Semaphore
0
1
1
1
0
1
1
1
0
1
1
1
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left Port has semaphore token
Semaphore free
Note:
This table denotes a sequence of events for only one of the 8 semaphores on the
M67025E.
Figure 1. Semaphore Logic
10
Rev. H–21-Aug-01
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC-GND):....................... -0.3 V to 7.0 V
Input or output voltage applied: ..................(GND - 0.3 V) to (VCC + 0.3 V)
Storage temperature:..................................-65 ° C to +150 ° C
Note:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device.This is a stress rating only and func-
tional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for extented periods may affect
reliability.
OPERATING SUPPLY
VOLTAGE
OPERATING TEMPERATURE
Military
VCC = 5 V + 10 %
- 55 °C to + 125 °C
DC Parameters
Parameter
Description
67025-30
67025-45
10
UNIT
mA
µA
VALUE
Max
(1)
ICCSB
ICCSB1
ICCOP
Standby supply current (Both ports TTL level inputs)
Standby supply current (Both ports CMOS level inputs)
Operating supply current (Both ports active)
10
(2)
(3)
500
320
500
Max
260
mA
Max
Operating supply current (One port active - One port
standby)
(4)
ICCOP1
200
180
mA
Max
1.
2.
3.
4.
CSL = CSR > 2.2 V.
CSL = CSR > VCC - 0.2 V.
Both ports active - Maximum frequency - Outputs open - OE = VIH.
One port active (f = fMAX) - Output open - One port stand-by TTL or CMOS Level Inputs - CSL = CSR > 2.2 V.
PARAMETER
IL I/O (1)
VIL (2)
DESCRIPTION
Input/Output leakage current
Input low voltage
67025E
+ 10
0.8
2.2
0.4
2.4
5
UNIT
µA
V
VALUE
Max
Max
Min
VIH(2)
Input high voltage
V
VOL (3)
VOH(3)
C IN
Output low voltage (I/O0-I/O15
Output high voltage
)
V
Max
Min
V
Input capacitance
pF
pF
Max
Max
C OUT
Output capacitance
7
1.
2.
3.
Vcc = 5.5 V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc.
VIH max = Vcc + 0.3 V, VIL min = -0.3 V or -1 V pulse width 50 ns.
Vcc min, IOL = 4 mA, IOH = -4 mA.
11
M67025E
Rev. H – 21-Aug-01
M67025E
Data-Retention Mode
Atmel CMOS RAMs are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules insure data
retention:
1. Chip select (CS) must be held high during data retention; within VCC to VCC -
0.2 V.
2. CS must be kept between VCC - 0.2 V and 70 % of VCC during the power up
and power down transitions.
3. The RAM can begin operation > tRC after VCC reaches the minimum operating
voltage (4.5 volts).
(1)
Timing
Value
PARAMETER (max)
TEST CONDITIONS (1)
UNIT
V
ICCDR
@ VCCDR = 2 V Com
20
µA
1.
tRC = Read cycle time.
12
Rev. H–21-Aug-01
AC Test Conditions
Input Pulse Levels: GND to 3.0 V
Input Rise/Fall Times: 5 ns
Output Reference Levels: 1.5 V
Output Load: see figures 2, 3
Input Timing Reference Levels: 1.5 V
Figure 2. Output Load
Figure 3. Output Load (for tHZ, tLZ, tWZ, and tOW)
AC Electrical Characteristics
Table 6. Over the Full Operating Temperature and Supply Voltage Range
M
M
READ CYCLE
UNIT
67025-30
67025-45
PARAMETER
Symbol
(4)
Symbol
(5)
Min.
Max.
Min.
Max.
TAVAVR
TAVQV
TELQV
TBLQV
TGLQV
TAVQX
TELQZ
TEHQZ
TPU
tRC
tAA
Read cycle time
30
-
-
45
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
30
30
30
15
-
45
45
45
25
-
tACS
tABE
tAOE
tOH
tLZ
Chip Select access time (3)
Byte enable access time (3)
Output enable access time
Output hold from address change
Output low Z time (1, 2)
-
-
-
-
-
-
3
3
-
3
5
-
-
-
tHZ
Output high Z time (1, 2)
15
-
20
-
tPU
Chip Select to power up time (2)
Chip disable to power down time (2)
SEM flag update pulse (OE or SEM)
Semaphore Access time (3)
0
-
0
-
TPD
tPD
50
-
50
-
TSOP
tSOP
15
15
-
TSLQV
tACS
-
30
45
Notes: 1. Transition is measured + 500 mV from low or high impedance voltage with load (figures 2 and 3).
2. This parameter is guaranteed but not tested.
3. To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. Refer to table 1.
4. STD symbol.
5. ALT symbol.
13
M67025E
Rev. H – 21-Aug-01
M67025E
(1) (2) (4)
Timing Waveform of Read Cycle n° 1, Either Side
(4)Timing Waveform of Read Cycle n° 2, Either Side (1) (3) (4)
(5)
Timing Waveform of Read Cycle n° 3, Either Side (1)(3)(4)(5)
1.
2.
3.
4.
5.
R/W si high for read cycles
Device is continously enabled, CS=VIL, UB or LB VIL. This waveform cannot be used for semaphore reads.
Addresses valid prior to or coincident with CS transition low.
OE=VIL
To access RAM, CS=VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL. Refer to Table 1.
14
Rev. H–21-Aug-01
AC Electrical Characteristics
Table 7. AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
M
M
WRITE CYCLE
67025-30
67025-45
UNIT
PARAMETER
Symbol
Symbol
(1)
(2)
Min.
Max.
–
Min.
Max.
–
TAVAVW
TELWH
TAVWH
TAVWL
TWLWH
TWHAX
TDVWH
TGHQZ
TWHDX
TWLQZ
TWHQX
TSWRD
TSPS
tWC
tSW
tAW
tAS
Write cycle time
30
25
25
0
45
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write (3)
Address valid to end of write
Address Set-up Time
–
–
–
–
–
–
tWP
tWR
tDW
tHZ
Write Pulse Width
25
0
–
35
0
–
Write Recovery Time
–
–
Data Valid to end of write
20
–
–
25
–
–
(4) (5)
Output high Z time
15
–
20
–
(6)
tDH
Data hold time
0
0
(4)(5)
tWZ
Write enable to output in high Z
–
15
–
–
20
–
tOW
tSWRD
tSPS
Output active from end of write (4)(5)(6)
SEM flag write to read time
0
0
10
10
–
10
10
–
SEM flag contention window
–
–
1.
2.
3.
STD symbol.
ALT symbol.
To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. This condition must be valid
for entire tSW time.
4.
5.
6.
Transition is measured ± 500 mV from low or high impedance voltage with load (figures 2 and 3).
The parameters is guaranteed but not tested.
The specification fot tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH
and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW
.
15
M67025E
Rev. H – 21-Aug-01
M67025E
Timing Waveform of Write Cycle n° 1, R/W Controlled Timing (1, 2, 3, 7)
Timing Waveform of Write Cycle n° 2, CS Controlled Timing (1, 2, 3, 5)
1. R/WC or CS must be high during all address transitions.
2. A write occurs during the overlap (tSW or tWP) of a low CS or SEM and a low R/W.
3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end
of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be
applied.
5. If the CS or SEM low transition occurs simultaneously with or after the R/W low tran-
sition, the outputs remain in the high impedance state.
6. Transition is measured ± 500 mV from steady state with a 5pF load (including scope
and jig).This FG_Leftmeter is sampled and not 100 % tested.
7. If OE is low during a R/W controlled write cycle, the write pulse width must be the
larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tDW. If OE is high during an R/W controlled write cycle, this
requirement does not apply and the write pulse can be as short as the specified tWP
.
8. To access RAM, CS = VIL. SEM = VIH.
9. To access upper byte CS = VIL, UB = VIL, SEM = VIH.
To access lower byte CS = VIL, LB = VIL, SEM = VIH.
16
Rev. H–21-Aug-01
AC Electrical Characteristics
Table 8. AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
M
M
WRITE CYCLE
PARAMETER
67025-30
67025-45
UNIT
Min.
Max.
Min.
Max.
BUSY TIMING (For Master 67025 only)
BUSY Access time
to address
tBAA
–
–
–
–
30
25
25
20
–
–
–
–
35
30
30
25
ns
ns
ns
ns
BUSY Disable time
to address
tBDA
BUSY Access time
to Chip Select
tBAC
BUSY Disable time
to Chip Select
tBDC
(1)
tWDD
tDDD
tAPS
tBDD
Write Pulse to data Delay
–
–
5
–
55
40
–
–
5
–
70
55
ns
ns
ns
ns
Write data valid to read data delay(1)
Arbitration priority set-up time (2)
BUSY disable to valid data
–
–
(3)
(3)
BUSY TIMING (For Slave 67025 only)
(4)
tWB
Write to BUSY input
0
20
–
–
–
0
25
–
–
–
ns
ns
ns
ns
(5)
tWH
Write hold after BUSY
(6)
tWDD
tDDD
Write pulse to data delay
Write data valid to read data delay (6)
55
40
70
55
–
–
1.
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For Mas-
ter 67025 only)”.
2.
3.
4.
5.
6.
To ensure that the earlier of the two ports wins.
tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) ot tDDD - tDW (actual).
To ensure that the write cycle is inhibited during contention.
To ensure that a write cycle is completed after contention.
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)”.
17
M67025E
Rev. H – 21-Aug-01
M67025E
Timing Waveform of Read with BUSY (2, 3, 4) (For Master 67025)
Note:
1. To ensure that the earlier of the two port wins.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OE = L for the reading port.
Timing Waveform of Write with Port-to-Port (1, 2, 3) (For Slave 67025 Only)
Notes: 1. Assume BUSY = H for the writing port, and OE = L for the reading port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
18
Rev. H–21-Aug-01
Timing Waveform of Write with BUSY (For Slave 67025)
Timing Waveform of Contention Cycle n° 1, CS Arbitration
(For Master 67025 only)
19
M67025E
Rev. H – 21-Aug-01
M67025E
Timing Waveform of Contention Cycle n° 2, Address Valid Arbitration
(For Master 67025 only) (1)
Left Address Valid First:
Right Address Valid First:
Notes: 1. CSL = CSR = VIL
20
Rev. H–21-Aug-01
AC Parameters
INTERRUPT
TIMING
67025-30
67025-45
PARAMETER
UNIT
SYMBOL
tAS
Min.
Max.
–
Min.
Max.
–
Address set-up time
0
0
–
–
0
0
–
–
ns
ns
ns
ns
tWR
Write recovery time
Interrupt set time
Interrupt reset time
–
–
tINS
25
25
35
35
tINR
Waveform of Interrupt Timing(1)
Notes: 1. All timing is the same for left and right ports. Port “A” may be either the left or right
port. Port “B” is the port opposite from “A”.
2. See interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
21
M67025E
Rev. H – 21-Aug-01
M67025E
32-bit Master/Slave Dual-Port Memory Systems
Note:
1. No arbitration in M67025E (SLAVE). BUSY-IN inhibits write in M67025E SLAVE.
Timing Waveform of Semaphore Read after Write Timing, Either Side (1)
Note:
1. CS = VIH for the duration of the above timing (both write and read cycle).
22
Rev. H–21-Aug-01
Timing Waveform of Semaphore Contention (1, 3, 4)
Notes: 1. DOR = DOL VIL, CSR = CSL = VIH, seaphore Flag is released from both sides (reads as
ones from both sides) at cycle start.
2. Either side “A” = left and side “B” = rigt, or side “A” = right and side “B” = left.
3. This parameter is measured from the point where R/WA or SEMA goes high until
R/WB or SEMB goes high.
4. IF tSPS is violated, the semaphore will fall positively to one side or the other, but there
is no guarantee which side will obtain the flag.
23
M67025E
Rev. H – 21-Aug-01
M67025E
Ordering Information
Reference Number
MMK2-67025EV-30-E(*)
MMK2-67025EV-30
Temperature Range
25°C
Speed
30ns
30ns
45ns
30ns
45ns
30ns
45ns
30ns
45ns
30ns
45ns
30ns
45ns
30ns
45ns
30ns
30ns
30ns
Package
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
MQFPF84
Die
Quality Flow
Engineering Samples
Mil.
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
-55 to +125°C
25°C
MMK2-67025EV-45
Mil.
SMK2-67025EV-30SB
SMK2-67025EV-45SB
SMK2-67025EV-30SC
SMK2-67025EV-45SC
MMK2-67025EV-30/883(*)
MMK2-67025EV-45/883(*)
SMK2-67025EV-30/883(*)
SMK2-67025EV-45/883(*)
5962-9161709QZC
SCC B
SCC B
SCC C
SCC C
MIL-883 B
MIL-883 B
MIL-883 S
MIL-883 S
QML Q
5962-9161706QZC
QML Q
5962-9161709VZC
QML V
5962-9161706VZC
QML V
MM0-67025EV-30-E(*)
5962-9161709Q9A
Engineering Samples
QML Q
-55 to +125°C
-55 to +125°C
Die
5962-9161709V9A
Die
QML V
Note:
(*)contact factory
24
Rev. H–21-Aug-01
Atmel Wireless & Microcontrollers Sales Offices
France
3, Avenue du Centre
78054 St.-Quentin-en-Yvelines
Cedex
France
Tel: 33130 60 70 00
Fax: 33130 60 71 11
Sweden
Hong Kong
77 Mody Rd., Tsimshatsui East,
Rm.1219
East Kowloon
Hong Kong
Tel: 85223789 789
Fax: 85223755 733
Kavallerivaegen 24, Rissne
17402 Sundbyberg
Sweden
Tel: 468587 48 800
Fax: 468587 48 850
United Kingdom
Germany
Korea
Easthampstead Road
Bracknell, Berkshire RG12 1LX
United Kingdom
Erfurter Strasse 31
85386 Eching
Germany
Ste.605,Singsong Bldg. Young-
deungpo-ku
Tel: 441344707 300
Fax: 441344427 371
150-010 Seoul
Korea
Tel: 8227851136
Fax: 8227851137
Tel: 49893 19 70 0
Fax: 49893 19 46 21
USA
2325 Orchard Parkway
San Jose
Kruppstrasse 6
45128 Essen
Germany
Tel: 492 012 47 30 0
Fax: 492 012 47 30 47
Singapore
California 95131
USA-California
Tel: 1408441 0311
Fax: 1408436 4200
25 Tampines Street 92
Singapore 528877
Rep. of Singapore
Tel: 65260 8223
Fax: 65787 9819
Theresienstrasse 2
74072 Heilbronn
Germany
Tel: 4971 3167 36 36
Fax: 4971 3167 31 63
1465 Route 31, 5th Floor
Annandale
New Jersey 08801
USA-New Jersey
Tel: 1908848 5208
Fax: 1908848 5232
Taiwan
Wen Hwa 2 Road, Lin Kou
Hsiang
244 Taipei Hsien 244
Taiwan, R.O.C.
Tel: 88622609 5581
Fax: 88622600 2735
Italy
Via Grosio, 10/8
20151 Milano
Italy
Tel: 390238037-1
Fax: 390238037-234
Japan
1-24-8 Shinkawa, Chuo-Ku
104-0033 Tokyo
Japan
Spain
Tel: 8133523 3551
Fax: 8133523 7581
Principe de Vergara, 112
28002 Madrid
Spain
Tel: 3491564 51 81
Fax: 3491562 75 14
Web site
http://www.atmel-wm.com
© Atmel Nantes SA, 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Printed on recycled paper.
相关型号：
©2020 ICPDF网 联系我们和版权申明