概述
规格参数
数据手册AT22V10B-10PC 概述
High Speed UV Erasable Programmable Logic Device 高速UV可擦除可编程逻辑器件 可编程逻辑器件
AT22V10B-10PC 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | DIP | 包装说明： | DIP, DIP24,.3 |
| 针数： | 24 | Reach Compliance Code： | unknown |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.28 |
| 其他特性： | 10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS | 架构： | PAL-TYPE |
| 最大时钟频率： | 83 MHz | JESD-30 代码： | R-PDIP-T24 |
| JESD-609代码： | e0 | 长度： | 32 mm |
| 专用输入次数： | 11 | I/O 线路数量： | 10 |
| 输入次数： | 22 | 输出次数： | 10 |
| 产品条款数： | 132 | 端子数量： | 24 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 组织： | 11 DEDICATED INPUTS, 10 I/O | 输出函数： | MACROCELL |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | DIP |
| 封装等效代码： | DIP24,.3 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 5 V | 可编程逻辑类型： | OT PLD |
| 传播延迟： | 10 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 5.08 mm | 子类别： | Programmable Logic Devices |
| 最大供电电压： | 5.5 V | 最小供电电压： | 4.5 V |
| 标称供电电压： | 5 V | 表面贴装： | NO |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 7.62 mm |
AT22V10B-10PC 数据手册
通过下载AT22V10B-10PC数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载AT22V10B
Features
High Performance Programmable Logic Device
•
7.5 ns Max Propagation Delay
Up to 166 MHz Operation
5 V ± 10% Operation
Fully Compatible with Standard 22V10
•
Identical Functionality/Fuse-Map
TTL Compatible Inputs and Outputs
•
10 µA Leakage Maximum
High Speed
Reprogrammable - Tested 100% for Programmability
High Reliability
•
•
UV Erasable
Programmable
Logic Device
Proven UV Erasable CMOS Technology
2000 V ESD Protection
200 mA Latch-Up Protection
Full Military, Commercial and Industrial Temperature Ranges
Dual-In-Line and Surface Mount Packages with Standard Pinouts
•
•
Logic Diagram
OE PRODUCT TERMS
PROGRAMMABLE
INTERCONNECT
AND
12
LOGIC
OPTION
10
I/O PINS
OUTPUT
OPTION
INPUT PINS
COMBINATORIAL
LOGIC ARRAY
8 TO 16
PRODUCT
TERMS
(UP T0 10
FLIP-FLOPS)
1
Description
The AT22V10B is an ultra-high performance CMOS Programmable Logic Device (PLD).
Speeds down to 7.5 ns and operation up to 166 MHz are offered. All pins offer a low± 10 µA
leakage.
The AT22V10B logic functionality is fully compatible with the standard 22V10. The 12 dedi-
cated inputs and ten configurable I/O pins allow implementation of logic requiring up to 22
input signals. The AT22V10B also provides individual output enable product terms for each
of the ten I/Os.
(continued)
PLCC
DIP/SOIC
CLK/IN
IN IN
VCC
I/O
22
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
*
I/O
Pin Configurations
Pin Name Function
2
3
4
5
6
1
IN
IN
IN
IN
IN
I/O
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
CLK/IN
IN
Clock and Logic Input
Logic Inputs
8
*
IN
IN
IN
*
I/O
I/O
7
8
9
10
11
12
I/O
Bidirectional Buffers
No Internal Connection
+5 V Supply
I/O
15
*
*
I/O
IN
GND
VCC
I/O
IN GND IN
0226B
1-109
Description (Continued)
The AT22V10B incorporates a variable product term architec-
ture. Each output is allocated from eight to 16 product terms,
which allows highly complex logic functions to be realized.
are common to all ten registers. All registers are automatically
cleared upon power up.
Register preload simplifies testing. A security fuse prevents un-
authorized copying of programmed fuse patterns.
The AT22V10B includes two additional product terms to pro-
vide synchronous preset and asynchronous reset. These terms
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect de-
vice reliability.
o
o
Temperature Under Bias.................-55 C to +125 C
o
o
Storage Temperature......................-65 C to +150 C
Voltage on Any Pin with
(1)
Respect to Ground........................-2.0 V to +7.0 V
Voltage on Input Pins
with Respect to Ground
During Programming...................-2.0 V to +14.0 V
Note:
1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V
for pulses of less than 20 ns. Maximum output pin voltage is
(1)
V
+0.75 V dc which may overshoot to +7.0 V for pulses of less
CC
Programming Voltage with
Respect to Ground......................-2.0 V to +14.0 V
than 20 ns.
(1)
2
Integrated UV Erase Dose..............7258 W• sec/cm
Logic Options
SP
D
Q
To
To
Output
Output
CK
Q
AR
From
Output
Output Options
OE
OE
From
From
Logic
I/O
Logic
I/O
Option
Option
1-110
AT22V10B
AT22V10B
D.C. and A.C. Operating Conditions
Commercial
AT22V10B
-7
Commercial
AT22V10B
-10
Industrial
AT22V10B
Military
AT22V10B
-10
-10
o
o
o
o
o
o
o
o
Operating Temperature (Case)
Power Supply
0 C - 70 C
0 C - 70 C
-40 C - 85 C
-55 C - 125 C
V
5 V ± 5%
5 V ± 10%
5 V ± 10%
5 V ± 10%
CC
D.C. Characteristics
Symbol Parameter
Condition
Min
Max
10
Units
I
I
Input Load Current
V
IN
= -0.1 V to V +1 V
µA
µA
mA
mA
mA
V
LI
CC
Output Leakage Current
V
OUT
= -0.1 V to V +0.1 V
10
LO
CC
Com.
140
160
-120
0.8
f = 0 MHz to F
, V = MAX,
MAX CC
I
Power Supply Current
CC
V
IN
= GND, Outputs Open
Ind., Mil.
(1)
I
Output Short Circuit Current V
Input Low Voltage
= 0.5 V
-30
-0.6
2.0
OS
OUT
V
V
IL
VCC+0.75
0.5
Input High Voltage
V
IH
I
OL
I
OL
I
OL
= 16 mA
= 12 mA
= 24 mA
Com.,Ind.
Mil.
V
V
V
= V or V ,
IN
IH
IL
V
OL
Output Low Voltage
0.5
V
= MIN
CC
Com.
0.8
V
V
V
= V or V ,
IN
IH
IL
2.4
V
OH
Output High Voltage
I
= -4.0 mA
V
OH
= MIN
CC
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
1-111
A.C. Waveforms(1)
INPUTS,I/O
REG. FEEDBACK
SYNCH. PRESET
tS
tH
tWH
tWP
CP
tP
tAR
ASYNCH. RESET
tAW
tAP
tCO
tER
tER
tEA
tEA
REGISTERED
OUTPUTS
HIGHZ
HIGHZ
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
tPD
COMBINATORIAL
OUTPUTS
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
Note: 1. Timing measurement reference is 1.5 V. Input AC driving levels are 0.0 V and 3.0 V, unless otherwise specified.
A.C. Characteristics
AT22V10B-7
AT22V10B-10
Min
Typ
5
Max
7.5
7.5
7.5
2
Min
Typ
6
Max
Symbol Parameter
Units
ns
t
t
t
t
t
t
t
t
t
t
Input or Feedback to Non-Registered Output
Input to Output Enable
Input to Output Disable
Clock to Feedback
10
10
10
2
PD
EA
ER
CF
CO
S
5
6
ns
5
6
ns
(1)
0
0
1
0
0
1
ns
Clock to Output
3.5
2
5.5
4
7
ns
Input or Feedback Setup Time
Hold Time
3.5
0
5
3
ns
0
ns
H
Clock Period
6
7
ns
P
(1)
Clock Width Low
3
3.5
3.5
ns
WL
WH
Clock Width High
3
ns
External Feedback 1/(t +t
)
111
166
166
83
MHz
MHz
MHz
ns
S
CO
F
MAX
Internal Feedback 1/(t + t
)
CF
142
142
S
No Feedback 1/(t )
P
t
t
Asynchronous Reset Width
6
7
3
4
7
8
4
5
AW
Asynchronous Reset, Synchronous Preset,
Recovery Time
ns
ns
AR
AP
Asynchronous Reset to Registered Output
Reset
t
6
10
8
14
Note: 1. This parameter is only sampled and is not 100% tested.
Input Test Waveforms and
Measurement Levels
Output Test Loads:
Military
Commercial
5.0V
5.0V
3.0V
AC
AC
R1= 338
R1= 250
Ω
Ω
DRIVING
LEVELS
MEASUREMENT
LEVEL
1.5V
OUTPUT
PIN
OUTPUT
PIN
(1)
0.0V
R2= 248
CL= 50pF
CL= 50pF
Ω
R2= 167
Ω
tR, tF < 2 ns (10% to 90%)
Note: 1. CL = 30 pF for AT22V10B-7
1-112
AT22V10B
AT22V10B
Functional Logic Diagram AT22V10B
1-113
Preload of Registered Outputs
The registers in the AT22V10B are provided with circuitry to
allow loading of each register asynchronously with either a high
or a low. This feature will simplify testing since any state can be
Level forced on
registered output pin
during preload cycle
Register state
after cycle
forced into the registers to control test sequencing. A V level
IH
on the I/O pin will force the register high; a V will force it low,
IL
V
V
High
Low
IH
independent of the polarity bit (C0) setting. The preload state is
entered by placing an 10.5-V to 12-V signal on pin 8 on DIPs,
and pin 10 on SMPs. When the clock pin is pulsed high, the data
on the I/O pins is placed into the ten registers.
IL
tD
tD
tD
tD
tD
t
= 100 ns
DMIN
VH
PRELOAD
CLOCK
REGISTERED
OUTPUTS
OUTPUT
PRELOADENA. FORCEI/O’S PRELOAD DATA
OUTPUTSDIS. TO VIH ORVIL CLOCKEDIN
VOLTAGE
REMOVED
PRELOAD
DISABLED
Power Up Reset
3.8 V
The registers in the AT22V10B are designed to reset during
POWER
power up. At a point delayed slightly from V crossing 3.8 V,
CC
tPR
all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
REGISTERED
OUTPUTS
This feature is critical for state machine initialization. However,
due to the asynchronous nature of reset and the uncertainty of
tS
how V actually rises in the system, the following conditions
are required:
CC
tW
CLOCK
1) The V rise must be monotonic,
CC
2) After reset occurs, all input and feedback setup times must be
met before driving the clock pin high, and
Description
Parameter
Min Typ Max Units
Power-Up
Reset Time
3) The clock must remain stable during t
.
PR
t
PR
600 1000
ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
8
Units
pF
Conditions
C
C
5
6
V
V
= 0 V
IN
IN
8
pF
= 0 V
OUT
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Erasure Characteristics
The entire fuse array of an AT22V10B is erased after exposure
to ultraviolet light at a wavelength of 2537 Å. Complete erasure
is assured after a minimum of 20 minutes exposure using 12,000
calculated from the minimum integrated erasure dose of 15
W• sec/cm . To prevent unintentional erasure, an opaque label
is recommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent indoor
lighting or sunlight.
2
2
µW/cm intensity lamps spaced one inch away from the chip.
Minimum erase time for lamps at other intensity ratings can be
1-114
AT22V10B
AT22V10B
SUPPLY CURRENT vs. INPUT FREQUENCY
NORMALIZED ICC vs. AMBIENT TEMP.
AT22V10B (TA = 25C, VCC = 5V)
f = 50 MHz
150
1.4
N
o
r
120
1.2
1.0
0.8
0.6
m
a
l
90
I
i
(mA)
C
z
e
d
C
60
30
0
I
C
C
0
20
40
60
80
100
-55
-25
5
35
65
95
125
Frequency (MHz)
Ambient Temperature (C)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (TA = 25C, VCC = 5V)
0
-20
-40
1.4
1.2
1.0
0.8
0.6
O
u
t
p
u
t
N
o
r
m
a
l
i
(mA)
C
u
r
z
e
d
-60
r
-80
e
n
t
I
C
C
-100
4.0
4.5
5.0
5.5
6.0
6.0
6.0
0
1
2
3
4
5
Supply Voltage (V)
Output Voltage (V)
OUTPUT SOURCE CURRENT
vs. SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (TA = 25C, VCC = 5V)
0
0
-1
-2
O
u
t
p
u
t
O
u
t
p
u
t
-15
(mA)
C
u
r
C
u
r
(mA)
-30
-3
-4
r
r
e
n
t
e
n
t
-45
4.0
4.5
5.0
5.5
3.5
3.7
3.9
4.1
4.3
4.5
Supply Voltage (V)
Output Voltage (V)
OUTPUT SINK CURRENT
vs. SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE (TA = 25C, VCC = 5V)
34
33
32
150
120
O
u
t
p
u
t
O
u
t
p
u
t
90
(mA)
31
(mA)
C
u
r
C
u
r
60
30
0
30
29
28
r
r
e
n
t
e
n
t
4.0
4.5
5.0
5.5
0
1
2
3
4
5
Supply Voltage (V)
Output Voltage (V)
1-115
NORMALIZED TPD
NORMALIZED TPD
vs. TEMPERATURE
vs. SUPPLY VOLTAGE
1.3
1.2
1.1
1.0
0.9
1.5
1.3
1.1
0.9
0.7
N
o
r
m
a
l
N
o
r
m
a
l
i
i
z
e
d
z
e
d
T
P
D
T
P
D
4.0
4.0
4.0
4.5
5.0
5.5
6.0
6.0
6.0
-55
-55
-55
-25
5
35
65
95
95
95
125
125
125
Supply Voltage (V)
Ambient Temperature (C)
NORMALIZED TCO
NORMALIZED TCO
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
1.2
1.1
1.0
0.9
1.5
1.3
1.1
0.9
N
o
r
m
a
l
N
o
r
m
a
l
i
i
z
e
d
z
e
d
T
C
O
T
C
O
4.5
5.0
5.5
-25
5
35
65
Supply Voltage (V)
Ambient Temperature (C)
NORMALIZED TS
NORMALIZED TS
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
1.2
1.1
1.0
0.9
0.8
0.7
1.3
1.1
0.9
0.7
N
o
r
m
a
l
N
o
r
m
a
l
i
i
z
e
d
z
e
d
T
S
T
S
4.5
5.0
5.5
-25
5
35
65
Supply Voltage (V)
Ambient Temperature (C)
DELTA TPD vs. OUTPUT LOADING
DELTA TCO vs. OUTPUT LOADING
(VCC = 4.5V, OUTPUT LOAD = COMMERCIAL)
( VCC = 4.5V, OUTPUT LOAD = COMMERCIAL )
12
12
D
e
l
t
a
D
e
l
t
a
9
6
8
4
T
P
D
T
C
O
3
0
0
n
s
n
s
-4
-3
0
100
200
300
400
0
100
200
300
400
Output Load (jig included) Capacitance pF
Output Load (jig included) Capacitance pF
1-116
AT22V10B
AT22V10B
Ordering Information
t
t
t
CO
(ns)
PD
S
Ordering Code
Package
Operation Range
(ns)
(ns)
7.5
3.5
5.5
AT22V10B-7DC
AT22V10B-7JC
AT22V10B-7PC
24DW3
28J
24P3
Commercial
(0°C to 70°C)
10
5
7
AT22V10B-10DC
AT22V10B-10GC
AT22V10B-10JC
AT22V10B-10PC
AT22V10B-10SC
24DW3
24D3
28J
24P3
24S
Commercial
(0°C to 70°C)
AT22V10B-10DI
AT22V10B-10GI
AT22V10B-10JI
AT22V10B-10PI
AT22V10B-10SI
24DW3
24D3
28J
24P3
24S
Industrial
(-40°C to 85°C)
AT22V10B-10DM
AT22V10B-10GM
AT22V10B-10LM
AT22V10B-10NM
24DW3
24D3
28LW
28L
Military
(-55°C to 125°C)
AT22V10B-10DM/883
AT22V10B-10GM/883
AT22V10B-10LM/883
AT22V10B-10NM/883
AT22V10B-12LM/883
AT22V10B-12NM/883
24DW3
24D3
28LW
28L
28LW
28L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
10
5
7
5962-87539 06 LA
5962-87539 06 3X
24DW3
28L
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
Package Type
24 Lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip)
24DW3
24D3
28J
24 Lead, 0.300" Wide, Non-Windowed (OTP), Ceramic Dual Inline Package (Cerdip)
28 Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)
28LW
28L
28 Pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
28 Pad, Non-Windowed, Ceramic Leadless Chip Carrier OTP (LCC)
24 Lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP)
24 Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)
24P3
24S
1-117
AT22V10B-10PC 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AT22V10B-10PI | ATMEL | High Speed UV Erasable Programmable Logic Device | 获取价格 |
|
| AT22V10B-10SC | ATMEL | High Speed UV Erasable Programmable Logic Device | 获取价格 |
|
| AT22V10B-10SI | ATMEL | High Speed UV Erasable Programmable Logic Device | 获取价格 |
|
| AT22V10B-12DC | ETC | UV-Erasable/OTP PLD | 获取价格 |
|
| AT22V10B-12DI | ETC | UV-Erasable/OTP PLD | 获取价格 |
|
| AT22V10B-12DM | ETC | UV-Erasable/OTP PLD | 获取价格 |
|
| AT22V10B-12DM/883 | ETC | UV-Erasable/OTP PLD | 获取价格 |
|
| AT22V10B-12GC | ETC | UV-Erasable/OTP PLD | 获取价格 |
|
| AT22V10B-12GI | ETC | UV-Erasable/OTP PLD | 获取价格 |
|
| AT22V10B-12GM | ATMEL | OT PLD, 12ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24 | 获取价格 |
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