AT24C01A_04 [ATMEL]
Two-wire Automotive Serial EEPROM; 两线汽车串行EEPROM
| 型号： | AT24C01A_04 |
| 厂家： | 
ATMEL |
| 描述： | Two-wire Automotive Serial EEPROM |
| 文件： | 总19页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 100 kHz (2.7V) and 400 kHz (5V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
• Partial Page Writes are Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
Two-wire
Automotive
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
Description
4K (512 x 8)
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-
trically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead
JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition,
the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
Table 1. Pin Configuration
Pin Name
A0 - A2
SDA
Function
AT24C04
8-lead PDIP
Address Inputs
Serial Data
AT24C08(1)
AT24C16(2)
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
SCL
Serial Clock Input
Write Protect
No Connect
A2
SCL
SDA
WP
Note: 1. This device is not recom-
mended for new designs.
GND
NC
Please refer to AT24C08A.
2. This device is not recom-
mended for new designs.
Please refer to AT24C16A.
8-lead SOIC
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
GND
3256F–SEEPR–10/04
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C01A and the AT24C02. As many as
eight 1K/2K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect.
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AT24C01A/02/04/08/16
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no
connects.
The AT24C16 does not use the device address pins, which limits the number of devices
on a single bus to one. The A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides
hardware data protection. The Write Protect pin allows normal read/write operations
when connected to ground (GND). When the Write Protect pin is connected to VCC, the
write protection feature is enabled and operates as shown see Table 2.
Table 2. Write Protect
Part of the Array Protected
WP Pin
Status
At VCC
At GND
24C01A
24C02
24C04
24C08(1)
Normal
Read/
Write
24C16(2)
Upper
Half
(8K)
Array
Full (1K)
Array
Full (2K)
Array
Full (4K)
Array
Operation
Normal Read/Write Operations
Notes: 1. This device is not recommended for new designs. Please refer to AT24C08A.
2. This device is not recommended for new designs. Please refer to AT24C16A.
Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,
the 1K requires a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,
the 4K requires a 9-bit data word address for random word addressing.
AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,
the 8K requires a 10-bit data word address for random word addressing.
AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.
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Table 3. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V.
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 4. DC Characteristics
Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise
noted).
Symbol
VCC1
VCC2
ICC
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
READ at 100 kHz
WRITE at 100 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ILI
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
−0.6
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Level(1)
VCC x 0.7
V
VOL2
VOL1
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
IOL = 0.15 mA
0.2
V
Notes: 1. VIL min and VIH max are reference only and are not tested.
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AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
Table 5. AC Characteristics
Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C01A/02/04/08,
2.7V
AT24C01A/02/04/08/16,
5.0V
AT24C16, 2.7V
Symbol
fSCL
Parameter
Min
Max
Min
Max
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(2)
Clock Low to Data Out Valid
400(1)
400
400
tLOW
tHIGH
tI
1.2
0.6
1.2
0.6
1.2
0.6
µs
50
50
50
ns
tAA
0.1
1.2
0.9
0.1
1.2
0.9
0.1
1.2
0.9
µs
Time the bus must be free before
a new transmission can start(3)
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
0.6
0.6
0
0.6
0.6
0
µs
µs
µs
ns
ns
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(3)
Inputs Fall Time(3)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
100
100
100
300
300
300
300
300
300
tF
tSU.STO
tDH
0.6
50
0.6
50
0.6
50
tWR
5
5
5
Write
Cycles
Endurance
5.0V, 25°C
1M
1M
1M
Notes: 1. The AT24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on the
topside of the package), guarantees 400 kHz (2.5V, 2.7V).
2. This parameter is characterized and is not 100% tested (TA = 25°C).
3. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
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3256F–SEEPR–10/04
STANDBY MODE: The AT24C01A/02/04/08/16 features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Bus Timing
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
ACK
8th BIT
WORDn
(1)
t
wr
START
CONDITION
STOP
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
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AT24C01A/02/04/08/16
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AT24C01A/02/04/08/16
Figure 4. Data Validity
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
7
3256F–SEEPR–10/04
Device Addressing
The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word
following a start condition to enable the chip for a read or write operation (see Figure 7
on page 9).
The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.
These 3 bits must compare to their corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corre-
sponding hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for
memory page addressing. The A2 bit must compare to its corresponding hard-wired
input pin. The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead the 3 bits are used for mem-
ory page addressing. These page addressing bits on the 4K, 8K and 16K devices
should be considered the most significant bits of the data word address which follows.
The A0, A1 and A2 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally timed write cycle, tWR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see Figure 8 on page 10).
PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K
and 16K devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (see Figure 9 on page 10).
The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally
incremented following the receipt of each data word. The higher data word address bits
are not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data
words are transmitted to the EEPROM, the data word address will “roll over” and previ-
ous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
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AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (see Figure 10 on page 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 11 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi-
tion (see Figure 12 on page 11).
Figure 7. Device Address
9
3256F–SEEPR–10/04
Figure 8. Byte Write
Figure 9. Page Write
(* = DON’T CARE bit for 1K)
Figure 10. Current Address Read
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AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
Figure 11. Random Read
(* = DON’T CARE bit for 1K)
Figure 12. Sequential Read
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3256F–SEEPR–10/04
AT24C01A Ordering Information
Ordering Code
Package
Operation Range
AT24C01A-10PA-5.0C
AT24C01A-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT24C01A-10PA-2.7C
AT24C01A-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low-voltage (2.7V to 5.5V)
12
AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
AT24C02 Ordering Information
Ordering Code
Package
Operation Range
AT24C02-10PA-5.0C
AT24C02N-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT24C02-10PA-2.7C
AT24C02N-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low-voltage (2.7V to 5.5V)
13
3256F–SEEPR–10/04
AT24C04 Ordering Information
Ordering Code
Package
Operation Range
AT24C04-10PA-5.0C
AT24C04N-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT24C04-10PA-2.7C
AT24C04N-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low-voltage (2.7V to 5.5V)
14
AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
AT24C08(1) Ordering Information
Ordering Code
Package
Operation Range
AT24C08-10PA-5.0C
AT24C08N-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT24C08-10PA-2.7C
AT24C08N-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Note:
1. This device is not recommended for new designs. Please refer to AT24C08A.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
8P3
8S1
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low-voltage (2.7V to 5.5V)
15
3256F–SEEPR–10/04
AT24C16(1) Ordering Information
Ordering Code
Package
Operation Range
AT24C16-10PA-5.0C
AT24C16N-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT24C16-10PA-2.7C
AT24C16N-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Note:
1. This device is not recommended for new designs. Please refer to AT24C16A.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
8P3
8S1
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low-voltage (2.7V to 5.5V)
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AT24C01A/02/04/08/16
3256F–SEEPR–10/04
AT24C01A/02/04/08/16
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
17
3256F–SEEPR–10/04
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
5
5
C
D
E1
E
D
2, 3
Side View
L
∅
e
1.27 BSC
4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
TITLE
REV.
DRAWING NO.
2325 Orchard Parkway
San Jose, CA 95131
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
8S2
C
R
18
AT24C01A/02/04/08/16
3256F–SEEPR–10/04
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