AT24C02B-TSU-T [ATMEL]
EEPROM, 256X8, Serial, CMOS, PDSO8, 2.90 X 1.60 MM, 1.60 MM HEIGHT, HALOGEN FREE AND LEAD FREE, PLASTIC, MO-193AB, SOT-23, 5 PIN;
| 型号： | AT24C02B-TSU-T |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDSO8, 2.90 X 1.60 MM, 1.60 MM HEIGHT, HALOGEN FREE AND LEAD FREE, PLASTIC, MO-193AB, SOT-23, 5 PIN 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 256 x 8 (2K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (2K) Write Modes
Two-wire
• Partial Page Writes Allowed
Serial EEPROM
2K (256 x 8)
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
• Lead-free/Halogen-free
• Available in Automotive
• Die Sales: Wafer Form and Tape and Reel
AT24C02B
Not
Description
The AT24C02B provides 2048 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The AT24C02B is available in space-saving
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead
SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire
serial interface. In addition, the AT24C02B is available in 1.8V (1.8V to 5.5V) version.
Recommended
for New Design
Table 0-1.
Pin Name
A0 - A2
SDA
Pin Configuration
Function
8-lead Ultra-Thin
Mini-MAP (MLP 2x3)
8-ball dBGA2
VCC 8
WP 7
1 A0
2 A1
3 A2
4 GND
8
7
6
5
1
2
3
4
A0
VCC
WP
Address Inputs
Serial Data
A1
SCL 6
SDA 5
A2
SCL
SDA
GND
SCL
Serial Clock Input
Write Protect
Ground
Bottom View
Bottom View
WP
8-lead TSSOP
8-lead SOIC
GND
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
VCC
Power Supply
A2
SCL
SDA
A2
SCL
SDA
GND
GND
Note:
For use of 5-lead SOT23, the
software A2, A1, and A0 bits in
the device address word
8-lead PDIP
5-lead SOT23
8
7
6
5
VCC
A0
1
2
3
4
WP
SCL
1
2
3
5
must be set to zero to prop-
erly communicate.
WP
A1
A2
GND
SDA
SCL
SDA
5126H–SEEPR–8/07
VCC
4
GND
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature ................................ –55C to +125C
Storage Temperature.................................... –65C to +150C
Voltage on Any Pin
with Respect to Ground ....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 0-1. Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
LOAD
COMP
LOAD
DATA WORD
DATA RECOVERY
EEPROM
DEVICE
ADDRESS
COMPARATOR
INC
A2
A1
A0
R/W
ADDR/COUNTER
SERIAL MUX
Y DEC
DOUT/ACK
LOGIC
DIN
DOUT
1. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hard wired for the AT24C02B. As many as eight 2K devices may be addressed on a sin-
gle bus system (device addressing is discussed in detail under the Device Addressing section).
WRITE PROTECT (WP): The AT24C02B has a write protect pin that provides hardware data
protection. The write protect pin allows normal read/write operations when connected to ground
2
AT24C02B
5126H–SEEPR–8/07
AT24C02B
(GND). When the write protect pin is connected to VCC, the write protection feature is enabled
and operates as shown in Table 1-1.
Table 1-1.
Write Protect
Part of the Array Protected
WP Pin
Status
24C02B
Full (2K) Array
At VCC
At GND
Normal Read/Write Operations
2. Memory Organization
AT24C02B, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K
requires an 8-bit data word address for random word addressing.
3
5126H–SEEPR–8/07
Table 2-1.
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V
Pin Capacitance(1)
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: TAI = –40C to +85C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V
(unless otherwise noted)
Symbol
VCC1
VCC2
VCC3
VCC4
ICC
Parameter
Test Condition
Min
1.8
2.5
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V
Standby Current VCC = 2.5V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
READ at 100 kHz
WRITE at 100 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ISB3
ISB4
ILI
0.6
3.0
1.4
4.0
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
–0.6
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Level(1)
VCC x 0.7
V
VOL2
VOL1
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
IOL = 0.15 mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested.
Table 2-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40C to +85C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8, 2.5, 2.7
5.0-volt
Symbol
fSCL
Parameter
Min
Max
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
400
1000
tLOW
tHIGH
tI
1.2
0.6
0.4
0.4
µs
50
40
ns
tAA
0.1
0.9
0.05
0.55
µs
4
AT24C02B
5126H–SEEPR–8/07
AT24C02B
Table 2-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40C to +85C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8, 2.5, 2.7
5.0-volt
Symbol
tBUF
Parameter
Min
1.2
0.6
0.6
0
Max
Min
Max
Units
µs
Time the bus must be free before a new transmission can start
Start Hold Time
0.5
0.25
0.25
0
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
µs
Start Setup Time
µs
Data In Hold Time
µs
Data In Setup Time
Inputs Rise Time(1)
100
100
ns
0.3
0.3
µs
tF
Inputs Fall Time(1)
300
100
ns
tSU.STO
tDH
Stop Setup Time
0.6
50
.25
50
µs
Data Out Hold Time
Write Cycle Time
ns
tWR
5
5
ms
Write
Cycles
Endurance(1)
5.0V, 25C, Byte Mode
1 Million
Note:
1. This parameter is ensured by characterization only.
5
5126H–SEEPR–8/07
3. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5-3 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 5-3 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02B features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
2-Wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c)
create another start bit followed by stop bit condition as shown below. The device is ready for
next communication after above steps have been completed.
Figure 3-1. Software reset
Dummy Clock Cycles
Start bit
Stop b
Start bit
1
2
3
8
9
SCL
SDA
6
AT24C02B
5126H–SEEPR–8/07
AT24C02B
4. Bus Timing
Figure 4-1. SCL: Serial Clock, SDA: Serial Data I/O®
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
5. Write Cycle Timing
Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O
SCL
ACK
SDA
8th BIT
WORDn
(1)
t
wr
START
CONDITION
STOP
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5126H–SEEPR–8/07
Figure 5-2. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 5-3. Start and Stop Definition
SDA
SCL
START
STOP
Figure 5-4. Output Acknowledge
1
8
9
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
8
AT24C02B
5126H–SEEPR–8/07
AT24C02B
6. Device Addressing
The 2K EEPROM device requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure 8-1).
The device address word consists of a mandatory one, zero sequence for the first four most sig-
nificant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits
must compare to their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is ini-
tiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the chip will return to a standby state.
7. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing device, such as a microcontroller,
must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page
11).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to seven data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 8-3 on page 11).
The data word address lower three bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol-
lowing byte is placed at the beginning of the same page. If more than eight data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero allowing the read or write sequence to continue.
9
5126H–SEEPR–8/07
8. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page to the first byte of the first page. The
address “roll over” during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input zero but does generate a following stop condition (see Figure 8-4 on
page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a follow-
ing stop condition (see Figure 8-5 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a zero
but does generate a following stop condition (see Figure 8-6 on page 12).
Figure 8-1. Device Address
MSB
LSB
10
AT24C02B
5126H–SEEPR–8/07
AT24C02B
Figure 8-2. Byte Write
Figure 8-3. Page Write
Figure 8-4. Current Address Read
11
5126H–SEEPR–8/07
Figure 8-5. Random Read
Figure 8-6. Sequential Read
12
AT24C02B
5126H–SEEPR–8/07
AT24C02B
AT24C02B Ordering Information
Ordering Code
Voltage
1.8
Package
8P3
Operation Range
AT24C02B-PU (Bulk form only)
AT24C02BN-SH-B(1) (NiPdAu Lead Finish)
AT24C02BN-SH-T(2) (NiPdAu Lead Finish)
AT24C02B-TH-B(1) (NiPdAu Lead Finish)
AT24C02B-TH-T(2) (NiPdAu Lead Finish)
AT24C02BY6-YH-T(2) (NiPdAu Lead Finish)
AT24C02B-TSU-T(2)
1.8
8S1
1.8
8S1
Lead-free/Halogen-free/
Industrial Temperature
1.8
8A2
1.8
8A2
(–40C to 85C)
1.8
8Y6
1.8
5TS1
8U3-1
AT24C02BU3-UU-T(2)
1.8
Industrial Temperature
AT24C02B-W-11(3)
1.8
Die Sale
(–40C to 85C)
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Please contact Serial Interface Marketing.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8-ball, die Ball Grid Array Package (dBGA2)
8P3
8S1
8A2
8Y6
5TS1
8U3-1
Options
–1.8
Low-voltage (1.8V to 5.5V)
13
5126H–SEEPR–8/07
9. Part Marking Scheme
8-PDIP
Seal Year
TOP MARK
|
|
Seal Week
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
|---|---|---|---|---|---|---|---|
0
2
B
1
|---|---|---|---|---|---|---|---|
Lot Number
*
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
U = Material Set
Y = Seal Year
WW = Seal Week
02B = Device
1 = Voltage Indicator
*Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
14
AT24C02B
5126H–SEEPR–8/07
AT24C02B
8-SOIC
Seal Year
TOP MARK
|
|
Seal Week
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
0
2
B
1
|---|---|---|---|---|---|---|---|
Lot Number
*
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
H = Material Set
Y = Seal Year
WW = Seal Week
02B = Device
1 = Voltage Indicator
*Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
15
5126H–SEEPR–8/07
8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
|
|---|---|---|---|
* H Y W W
|---|---|---|---|---|
0 2 B 1
|---|---|---|---|---|
H = Material Set
Y = Seal Year
WW = Seal Week
02B = Device
V = Voltage Indicator
BOTTOM MARK
|---|---|---|---|---|---|---|
X
X
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
Lot Number
XX = Country of Origin
AAAAAA = Lot Number
16
AT24C02B
5126H–SEEPR–8/07
AT24C02B
SOT23
TOP MARK
|---|---|---|---|---|
Line 1 ----------->
2
B
1
W
U
|---|---|---|---|---|
*
|
2B = Device
1 = Voltage Indicator
W = Write Protect Feature
U = Material Set
Pin 1 Indicator (Dot)
BOTTOM MARK
|---|---|---|---|
Y
M
T
C
|---|---|---|---|
Y = One Digit Year Code
M = Seal Month
TC = Trace Code
ULTRA THIN MINI MAP
TOP MARK
|---|---|---|
0
2
B
|---|---|---|
H
1
|---|---|---|
Y
T
C
|---|---|---|
*
|
02B = Device
H = Material Set
1 = Voltage Indicator
Y = Year of Assembly
TC = Trace Code
Pin 1 Indicator (Dot)
17
5126H–SEEPR–8/07
dBGA2
TOP MARK
LINE 1------->
LINE 2------->
02BU
YMTC
|<-- Pin 1 This Corner
02B = Device
U = Material Set
Y = One Digit Year Code
M = Seal Month
TC = Trace Code
18
AT24C02B
5126H–SEEPR–8/07
AT24C02B
10. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
19
5126H–SEEPR–8/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
20
AT24C02B
5126H–SEEPR–8/07
AT24C02B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and ad acent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
2325 Orchard Parkway
San Jose, CA 95131
B
8A2
R
21
5126H–SEEPR–8/07
8Y6 - Mini Map
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A2
A1
1.50 REF..
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
b
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
10/16/07
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
D
R
22
AT24C02B
5126H–SEEPR–8/07
AT24C02B
5TS1 – SOT23
e1
C
4
5
E1
C
E
L
L1
1
3
2
End View
Top View
b
A2
A
Seating
Plane
A1
e
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.10
0.10
1.00
0.20
NOM
–
NOTE
SYMBOL
NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing
MO-193, Variation AB, for additional information.
A
2. Dimension D does not include mold flash, protrusions, or gate burrs.
A1
A2
c
0.00
0.70
0.08
–
Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end.
Dimension E1 does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.15 mm per side.
3. The package top may be smaller than the package bottom. Dimensions
D and E1 are determined at the outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. These dimensions apply to the flat section of the lead between 0.08 mm
and 0.15 mm from the lead tip.
5. Dimension "b" does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08 mm total in excess of the "b" dimension at
maximum material condition. The Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and an adjacent lead
shall not be less than 0.07 mm.
0.90
–
4
D
2.90 BSC
2.80 BSC
1.60 BSC
0.60 REF
0.95 BSC
1.90 BSC
–
2, 3
2, 3
2, 3
E
E1
L1
e
e1
b
0.30
0.50
4, 5
6/25/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink
Small Outline Package (SHRINK SOT)
R
PO5TS1
A
23
5126H–SEEPR–8/07
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
PIN 1 BALL PAD CORNER
Side View
1
2
3
4
(d1)
d
7
6
5
8
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
MIN
0.71
0.10
0.40
0.20
MAX
0.91
0.20
0.50
0.30
NOM
0.81
NOTE
SYMBOL
Bottom View
8 SOLDER BALLS
A
A1
A2
b
0.15
0.45
0.25
D
1.50 BSC
2.00 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
1. Dimension “b” is measured at the maximum solder ball diameter.
This drawing is for general information only.
E
e
e1
d
d1
6/24/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
PO8U3-1
A
R
Small Die Ball Grid Array Package (dBGA2)
24
AT24C02B
5126H–SEEPR–8/07
AT24C02B
11. Revision History
Doc. Rev.
Date
Comments
Updated to new template
Updated common graphics
Added Part Makring Scheme
5126H
8/2007
Removed reference to Waffle Pack on page 1 and Page 13
Added lines to Ordering Code table
Removed NC row in the table
Added note on Pg 1
5126G
4/2007
Corrected format on table 5
Removed Memory Reset section
Added 2-Wire software reset section and figure
Corrected Figures 7-11
Corrected dBGA2 package code on Pg 13
Removed ‘Preliminary’
5126F
5126E
2/2007
2/2007
Added Ultra-Thin on Pg 1
Modified Ordering Information table
Implemented Revision History
5126D
7/2006
Added Preliminary status; Added ‘Available in Automotive’ to
Features
25
5126H–SEEPR–8/07
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Atmel Europe
Le Krebs
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-en-
Yvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
s_eeprom@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF
THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© 2007 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, and others, are registered trademarks or trademarks of
Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
5126H–SEEPR–8/07
相关型号：
AT24C02BN-10SQ-2.7
EEPROM, 256X8, Serial, CMOS, PDSO8, 0.150 INCH, LEAD FREE AND HALOGEN FREE, PLASTIC, MS-012AA, SOIC-8
ATMEL
AT24C02BU3-UU-T
EEPROM, 256X8, Serial, CMOS, PBGA8, 1.50 X 2 MM, 0.50 MM PITCH, HALOGEN FREE AND LEAD FREE, DBGA-8
ATMEL
©2020 ICPDF网 联系我们和版权申明