AT24C04BY6-YH-T [ATMEL]
Two-wire Serial EEPROM 4K (512 x 8) 8K (1024 x 8); 两线串行EEPROM 4K （ 512 ×8 ） 8K （ 1024 ×8 ）
| 型号： | AT24C04BY6-YH-T |
| 厂家： | 
ATMEL |
| 描述： | Two-wire Serial EEPROM 4K (512 x 8) 8K (1024 x 8) |
| 文件： | 总26页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 512 x 8 (4K), or 1024 x 8 (8K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 16-byte Page (4K, 8K) Write Modes
• Partial Page Writes Allowed
Two-wire
Serial EEPROM
4K (512 x 8)
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
8K (1024 x 8)
• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-MAP (MLP 2x3), 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
• Lead-free/Halogen-free
• Die Sales: Wafer Form, Tape and Reel and Bumped Wafers
AT24C04B
AT24C08B
Description
The AT24C04B/08B provides 4096/8192 bits of serial electrically erasable and pro-
grammable read-only memory (EEPROM) organized as 512/1024 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The AT24C04B/08B is
available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra-Thin Mini-
MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is
accessed via a Two-wire serial interface. In addition, the AT24C04B/08B is available
in 1.8V (1.8V to 5.5V) version.
Table 0-1.
Pin Name
A0 - A2
SDA
Pin Configuration
Function
8-lead Ultra-Thin
Mini-MAP (MLP 2x3)
8-ball dBGA2
Address Inputs
Serial Data
VCC 8
WP 7
SCL 6
1 A0
2 A1
3 A2
4 GND
8
7
6
5
1
2
3
4
A0
VCC
WP
A1
A2
SCL
SDA
SCL
Serial Clock Input
Write Protect
No Connect
SDA
5
GND
Bottom View
Bottom View
WP
8-lead TSSOP
8-lead SOIC
NC
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
GND
Ground
A2
SCL
SDA
A2
SCL
SDA
VCC
Power Supply
GND
GND
Note:
For use of 5-lead SOT23
4K: The software A2 and A1 bits in the device
address word must be set to zero to properly
communicate.
8-lead PDIP
5-lead SOT23
8
7
6
5
VCC
A0
1
2
3
4
WP
SCL
GND
SDA
1
2
3
5
WP
A1
A2
8K: The software A2 bit in the device address word
must be set to zero to properly communicate.
SCL
SDA
VCC
4
GND
5226D–SEEPR–7/08
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature..................................–55°C to +125°C
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 0-1. Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
LOAD
COMP
LOAD
DATA WORD
DATA RECOVERY
EEPROM
DEVICE
ADDRESS
COMPARATOR
INC
A2
A1
A0
R/W
ADDR/COUNTER
SERIAL MUX
Y DEC
DOUT/ACK
LOGIC
DIN
DOUT
2
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
1. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The AT24C04B uses the A2 and A1 inputs for hard wire addressing and a toal of four 4K devices
may be addressed on a single bus system. The A0 pin is a no connect and can be connected to
ground (device addressing is discussed in detail under the Device Addressing section).
The AT24C08B only uses the A2 input for hardware addressing and a total of two 8K devices
may be addressed on a single bus system. The A0 and A1 pins are no connects and can be
connected to ground (device addressing is discussed in detail under the Device Addressing
section).
Table 1-1.
Write Protect
Part of the Array Protected
WP Pin
Status
24C04B/08B
Full Array
At VCC
At GND
Normal Read/Write Operations
3
5226D–SEEPR–7/08
2. Memory Organization
AT24C04B, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K
requires an 9-bit data word address for random word addressing.
AT24C08B, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K
requires a 10-bit data word address for random word addressing.
Table 2-1.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Pin Capacitance(1)
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol
VCC1
VCC2
VCC3
VCC4
ICC
Parameter
Test Condition
Min
1.8
2.5
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V
Standby Current VCC = 2.5V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
READ at 100 kHz
WRITE at 100 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ISB3
ISB4
ILI
0.6
3.0
1.4
4.0
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
–0.6
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Level(1)
VCC x 0.7
V
VOL2
VOL1
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
IOL = 0.15 mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
Table 2-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8, 2.5, 2.7
5.0-volt
Symbol
fSCL
Parameter
Min
Max
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before a new transmission can start
Start Hold Time
400
1000
tLOW
tHIGH
tI
1.2
0.6
0.4
0.4
µs
50
40
ns
tAA
0.1
1.2
0.6
0.6
0
0.9
0.05
0.5
0.55
µs
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
0.25
0.25
0
µs
Start Setup Time
µs
Data In Hold Time
µs
Data In Setup Time
100
100
ns
Inputs Rise Time(1)
0.3
0.3
µs
tF
Inputs Fall Time(1)
300
100
ns
tSU.STO
tDH
Stop Setup Time
0.6
50
.25
50
µs
Data Out Hold Time
ns
tWR
Write Cycle Time
5
5
ms
Write
Cycles
Endurance(1)
5.0V, 25°C, Byte Mode
1M
1M
Note:
1. This parameter is ensured by characterization only.
5
5226D–SEEPR–7/08
3. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5-3 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 5-3 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C04B/08B features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by a stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Dummy Clock Cycles
Start bit
Stop bit
Start bit
1
2
3
8
9
SCL
SDA
6
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
4. Bus Timing
Figure 4-1. SCL: Serial Clock, SDA: Serial Data I/O®
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
5. Write Cycle Timing
Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O
SCL
ACK
SDA
8th BIT
WORDn
(1)
t
wr
START
CONDITION
STOP
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5226D–SEEPR–7/08
Figure 5-2. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 5-3. Start and Stop Definition
SDA
SCL
START
STOP
Figure 5-4. Output Acknowledge
1
8
9
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
8
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
6. Device Addressing
The 4K and 8K EEPROM device requires an 8-bit device address word following a start condi-
tion to enable the chip for a read or write operation (refer to Figure 8-1).
The device address word consists of a mandatory one, zero sequence for the first four most sig-
nificant bits as shown. This is common to all the EEPROM devices.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory
page address bit. The two device address bits must compare to their corresponding hard-wired
input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory
page addressing. The A2 must compare to its corresponding hard-wired input pin. The A1 and
A0 pins are no connect.
For the SOT23 Package Offering:
The 4K EEPROM software A2 and A1 bits in the device address word must be set to zero to
properly communicate.
The 8K EEPROM software A2 bit in the device address word must be set to zero to properly
communicate.
7. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing device, such as a microcontroller,
must terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page
11).
PAGE WRITE: The 4K/8K EEPROMs are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to fifteen data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 8-3 on page 11).
The data word address lower four bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol-
lowing byte is placed at the beginning of the same page. If more than sixteen data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a zero allowing the read or write sequence to continue.
9
5226D–SEEPR–7/08
8. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page to the first byte of the first page. The
address “roll over” during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input zero but does generate a following stop condition (see Figure 8-4 on
page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a follow-
ing stop condition (see Figure 8-5 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a zero
but does generate a following stop condition (see Figure 8-6 on page 12).
Figure 8-1. Device Address
10
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
Figure 8-2. Byte Write
Figure 8-3. Page Write
Figure 8-4. Current Address Read
Figure 8-5. Random Read
11
5226D–SEEPR–7/08
Figure 8-6. Sequential Read
12
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
AT24C04B Ordering Information
Ordering Code
Voltage
1.8
Package
8P3
Operation Range
AT24C04B-PU (Bulk form only)
AT24C04BN-SH-B(1) (NiPdAu Lead Finish)
AT24C04BN-SH-T(2) (NiPdAu Lead Finish)
AT24C04B-TH-B(1) (NiPdAu Lead Finish)
AT24C04B-TH-T(2) (NiPdAu Lead Finish)
AT24C04BY6-YH-T(2) (NiPdAu Lead Finish)
AT24C04B-TSU-T(2)
1.8
8S1
1.8
8S1
Lead-free/Halogen-free/
Industrial Temperature
1.8
8A2
1.8
8A2
(–40°C to 85°C)
1.8
8Y6
1.8
5TS1
8U3-1
AT24C04BU3-UU-T(2)
1.8
Industrial Temperature
(–40°C to 85°C)
AT24C04B-W-11(3)
1.8
Die Sale
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8-ball, die Ball Grid Array Package (dBGA2)
8P3
8S1
8A2
8Y6
5TS1
8U3-1
Options
–1.8
Low-voltage (1.8V to 5.5V)
13
5226D–SEEPR–7/08
AT24C08B Ordering Information
Ordering Code
Voltage
1.8
Package
8P3
Operation Range
AT24C08B-PU (Bulk form only)
AT24C08BN-SH-B(1) (NiPdAu Lead Finish)
AT24C08BN-SH-T(2) (NiPdAu Lead Finish)
AT24C08B-TH-B(1) (NiPdAu Lead Finish)
AT24C08B-TH-T(2) (NiPdAu Lead Finish)
AT24C08BY6-YH-T(2) (NiPdAu Lead Finish)
AT24C08B-TSU-T(2)
1.8
8S1
1.8
8S1
Lead-free/Halogen-free/
Industrial Temperature
1.8
8A2
1.8
8A2
(–40°C to 85°C)
1.8
8Y6
1.8
5TS1
8U3-1
AT24C08BU3-UU-T(2)
1.8
Industrial Temperature
(–40°C to 85°C)
AT24C08B-W-11(3)
1.8
Die Sale
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8-ball, die Ball Grid Array Package (dBGA2)
8P3
8S1
8A2
8Y6
5TS1
8U3-1
Options
–1.8
Low-voltage (1.8V to 5.5V)
14
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
9. Part marking scheme
9.1
8-PDIP
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
|
Seal Week
6: 2006
0: 2010
|
|
|
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
|---|---|---|---|---|---|---|---|
50 = Week 50
52 = Week 52
0
4
B
1
|---|---|---|---|---|---|---|---|
Lot Number
*
Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
9.2
8-SOIC
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
|
Seal Week
6: 2006
0: 2010
|
|
|
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
50 = Week 50
52 = Week 52
0
4
B
1
|---|---|---|---|---|---|---|---|
Lot Number
*
Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
15
5226D–SEEPR–7/08
9.3
8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
Y = SEAL YEAR
WW = SEAL WEEK
|
6: 2006
7: 2007
8: 2008
9: 2009
0: 2010
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|
1: 2011
2: 2012
3: 2013
*
H
Y
W
W
|---|---|---|---|---|
0
4
B
1
50 = Week 50
52 = Week 52
|---|---|---|---|---|
BOTTOM MARK
|---|---|---|---|---|---|---|
P
H
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
9.4
8-Ultra Thin Mini MAP
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
0
4
B
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
|---|---|---|
H
1
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y
X
X
|---|---|---|
Y = SEAL YEAR
*
|
6: 2006
7: 2007
8: 2008
0: 2010
1: 2011
2: 2012
Pin 1 Indicator (Dot)
9: 2009
3: 2013
16
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
9.5 ULA
TOP MARK
|---|---|---|
0
4
B
|---|---|---|
Y
X
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y = BUILD YEAR
2006 = 6
2007 = 7
2008 = 8
Etc. . . .
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
9.6 SOT23
TOP MARK
|---|---|---|---|---|
Line 1 ----------->
4
B
1
B
U
|---|---|---|---|---|
*
|
XX = Device
V = Voltage Indicator
W = Write Protect Feature
U = Material Set
Pin 1 Indicator (Dot)
BOTTOM MARK
|---|---|---|---|
Y
M
T
C
|---|---|---|---|
Y = One Digit Year Code
M = Seal Month
(Use Alpha Designator A-L)
TC = Trace Code
9.7 dBGA2
TOP MARK
17
5226D–SEEPR–7/08
LINE 1------->
LINE 2------->
04BU
YMTC
|<-- Pin 1 This Corner
XXX = Device
U = Material Set
Y = One Digit Year Code
M = Seal Month (Use Alpha Designator A-L)
TC = Trace Code
18
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
10. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
19
5226D–SEEPR–7/08
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
20
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
–
A2
b
0.80
0.19
1.00
e
A2
–
4
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
2325 Orchard Parkway
San Jose, CA 95131
B
8A2
R
21
5226D–SEEPR–7/08
8Y6 - Mini Map
A
D2
b
((88XX))
Pin 11
Inddeex
Areaa
Pinn 11 ID
L (8X)
D
e (6X)
A2
A1
1.500 RREEFF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
b
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
10/16/07
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
D
R
22
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
5TS1 – SOT23
e1
C
4
5
E1
C
E
L
L1
1
3
2
End View
Top View
b
A2
A
Seating
Plane
A1
e
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.10
0.10
1.00
0.20
NOM
–
NOTE
SYMBOL
NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing
MO-193, Variation AB, for additional information.
A
2. Dimension D does not include mold flash, protrusions, or gate burrs.
A1
A2
c
0.00
0.70
0.08
–
Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end.
Dimension E1 does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.15 mm per side.
3. The package top may be smaller than the package bottom. Dimensions
D and E1 are determined at the outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. These dimensions apply to the flat section of the lead between 0.08 mm
and 0.15 mm from the lead tip.
5. Dimension "b" does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08 mm total in excess of the "b" dimension at
maximum material condition. The Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and an adjacent lead
shall not be less than 0.07 mm.
0.90
–
4
D
2.90 BSC
2.80 BSC
1.60 BSC
0.60 REF
0.95 BSC
1.90 BSC
–
2, 3
2, 3
2, 3
E
E1
L1
e
e1
b
0.30
0.50
4, 5
6/25/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink
Small Outline Package (SHRINK SOT)
R
PO5TS1
A
23
5226D–SEEPR–7/08
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
PIN 1 BALL PAD CORNER
Side View
1
2
3
4
(d1)
d
7
6
5
8
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
MIN
0.71
0.10
0.40
0.20
MAX
0.91
0.20
0.50
0.30
NOM
0.81
NOTE
SYMBOL
Bottom View
8 SOLDER BALLS
A
A1
A2
b
0.15
0.45
0.25
D
1.50 BSC
2.00 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
1. Dimension “b” is measured at the maximum solder ball diameter.
This drawing is for general information only.
E
e
e1
d
d1
6/24/03
TITLE
REV.
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
PO8U3-1
A
R
Small Die Ball Grid Array Package (dBGA2)
24
AT24C04B/08B
5226D–SEEPR–7/08
AT24C04B/08B
11. Revision History
Doc. Rev.
Date
Comments
5226D
5226C
7/2008
2/2008
Removed ‘Preliminary’ status
Text changes on page 4 and 9
Updated to new template
Updated common Figures
Added Package Marking tables
5226B
5226A
8/2007
6/2007
Initial document release
25
5226D–SEEPR–7/08
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5226D–SEEPR–7/08
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