AT24C256N-10SN-2.7 [ATMEL]
EEPROM, 32KX8, Serial, PDSO8;
| 型号： | AT24C256N-10SN-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 32KX8, Serial, PDSO8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总17页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• Internally Organized 16,384 x 8 and 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 400 kHz Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC SOIC, 8-lead TSSOP
Two-wire
Automotive
Serial
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
Two-wire bus. The device is optimized for use in many automotive applications where
low power and low voltage operation are essential. The devices are available in space-
saving 8-lead JEDEC SOIC and 8-lead TSSOP packages. In addition, the entire family
is available in 2.7V (2.7V to 5.5V) version.
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT24C128
AT24C256
Table 1. Pin Configuration
Pin Name
A0 - A1
SDA
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
Ground
8-lead TSSOP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
SCL
WP
NC
SCL
SDA
GND
NC
GND
8-lead SOIC
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
NC
SCL
SDA
GND
Rev. 5121A–SEEPR–9/05
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature..................................–55°C to +125°C
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
2
AT24C128/256
5121A–SEEPR–9/05
AT24C128/256
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hard-
wired or left not connected for hardware compatibility with other AT24CXX devices. When the
pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
pins are left floating, the A1 and A0 pins will be internally pulled down to GND if the capacitive
coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends con-
necting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to VCC, all write operations to the memory are inhib-
ited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive
coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF, Atmel recommends con-
necting the pin to GND.
Memory
Organization
AT24C128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as
256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word
address.
3
5121A–SEEPR–9/05
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V to +5.5V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAE = −40°C to +125°C, VCC = +2.7V to +5.5V
(unless otherwise noted)
Symbol Parameter
VCC3 Supply Voltage
ICC
Test Condition
Min
Typ
Max
5.5
Units
V
Symbol
VCC3
ICC
2.7
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
READ at 100 kHz
WRITE at 100 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
V
ICC
3.0
ICC
ISB3
ISB4
ILI
1.6
4.0
ISB3
ISB4
ILI
8.0
18.0
3.0
0.10
0.05
ILO
Output Leakage Current
Input Low Level (1)
3.0
ILO
VIL
−0.6
VCC x 0.3
VCC + 0.5
0.4
VIL
VIH
Input High Level (1)
VCC x 0.7
V
VIH
VOL2
VOL1
VOL2
VOL1
Note:
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
IOL = 0.15 mA
0.2
V
1. VIL min and VIH max are reference only and are not tested.
4
AT24C128/256
5121A–SEEPR–9/05
AT24C128/256
Table 4. AC Characteristics
Applicable over recommended operating range from TAE = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
AT24C128/256
Symbol
fSCL
Parameter
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
400
tLOW
1.2
0.6
0.1
tHIGH
tAA
µs
0.9
µs
Time the bus must be free before
a new transmission can start(1)
tBUF
1.2
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
µs
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
3.3V, 25°C, Page Mode
µs
µs
100
ns
300
300
ns
tF
ns
tSU.STO
tDH
0.6
50
µs
ns
tWR
5
ms
Endurance(1)
1M
Write Cycles
Note:
1. This parameter is ensured by characterization only.
5
5121A–SEEPR–9/05
Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on
page 7). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C128/256 features a low power standby mode which is enabled:
a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire
part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in
each cycle while SCL is high and then (c) create a start condition as SDA is high.
6
AT24C128/256
5121A–SEEPR–9/05
AT24C128/256
Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
ACK
8th BIT
WORDn
(1)
t
wr
START
CONDITION
STOP
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
7
5121A–SEEPR–9/05
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
Device
Addressing
The 128K/256K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 7 on page 10). The device address
word consists of a mandatory one, zero sequence for the first five most significant bits as
shown. This is common to all two-wire EEPROM devices.
The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices on
the same bus. These bits must compare to their corresponding hardwired input pins. The A1
and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the
pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24C128/256 has a hardware data protection scheme that allows the
user to write protect the whole memory when the WP pin is at VCC
.
8
AT24C128/256
5121A–SEEPR–9/05
AT24C128/256
Write
Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on
page 10).
PAGE WRITE: The 128K/256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (see Figure 9 on page 11).
The data word address lower 6 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
9
5121A–SEEPR–9/05
Read
Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll
over” during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the read/write select bit set to one is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi-
tion (see Figure 10 on page 11).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol-
lowing stop condition (see Figure 11 on page 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will con-
tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 12 on page 11).
Figure 7. Device Address
Figure 8. Byte Write
10
AT24C128/256
5121A–SEEPR–9/05
AT24C128/256
Figure 9. Page Write
Notes: (* = DON’T CARE bit)
(† = DON’T CARE bit for the 128K)
Figure 10. Current Address Read
Figure 11. Random Read
Notes: (* = DON’T CARE bit)
(† = DON’T CARE bit for the 128K)
Figure 12. Sequential Read
11
5121A–SEEPR–9/05
AT24C128 Ordering Information(1)
Ordering Code
Package
Operation Range
AT24C128-10TE-2.7
AT24C128N-10SE-2.7
8A2
8S1
Automotive Temperature
(–40°C to 125°C)
Lead-free/Halogen-free/
Automotive Temperature
AT24C128-10TQ-2.7(2)
AT24C128N-10SQ-2.7(2)
8A2
8S1
(–40°C to 125°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
2. “Q” designates Green package + RoHS compliant
Package Type
8S1
8A2
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
Options
–2.7
Low-voltage (2.7V to 5.5V)
12
AT24C128/256
5121A–SEEPR–9/05
AT24C128/256
AT24C256 Ordering Information(1)
Ordering Code
Package
Operation Range
AT24C256-10TE-2.7
AT24C256N-10SE-2.7
8A2
8S1
Automotive Temperature
(–40°C to 125°C)
Lead-free/Halogen-free/
Automotive Temperature
AT24C256-10TQ-2.7(2)
AT24C256N-10SQ-2.7(2)
8A2
8S1
(–40°C to 125°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
2. “Q” designates Green Package + RoHS compliant
Package Type
8P3
8S1
8A2
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
Options
–2.7
Low-voltage (2.7V to 5.5V)
13
5121A–SEEPR–9/05
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
14
AT24C128/256
5121A–SEEPR–9/05
AT24C128/256
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
Side View
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
15
5121A–SEEPR–9/05
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
16
AT24C128/256
5121A–SEEPR–9/05
Atmel Corporation
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Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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RF/Automotive
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Tel: (49) 71-31-67-0
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Fax: 1(408) 436-4314
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Microcontrollers
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5121A–SEEPR–9/05
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