AT24C512C-CUD-T [ATMEL]
EEPROM, 64KX8, Serial, PBGA8;
| 型号： | AT24C512C-CUD-T |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 64KX8, Serial, PBGA8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总23页 (文件大小：2041K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and standard-voltage operation
– M for VCC from 1.7V to 3.6V
– D for VCC from 2.5V to 5.5V
• Internally organized 65,536 x 8
• Two-wire serial interface
• Schmitt triggers, filtered inputs for noise suppression
• Bidirectional data transfer protocol
• 1MHz (2.5V, 5.5V), 400kHz (1.7V) compatibility
• Write protect pin for hardware and software data protection
• 128-byte page write mode (partial page writes allowed)
• Self-timed write cycle (5ms max)
• High reliability
Two-wire Serial,
Electrically
Erasable and
Programmable
Read-only Memory
512K (65,536 x 8)
– Endurance: 1,000,000 write cycles
– Data retention: 40 years
• Lead-free/halogen-free devices
• 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead UDFN, and
8-ball VFBGA packages
• Die sales: wafer form, waffle pack and bumped die
Atmel AT24C512C
with Three Device
Address Inputs
Description
The Atmel® AT24C512C provides 524,288 bits of serial, electrically erasable and program-
mable read-only memory (EEPROM) organized as 65,536 words of eight bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire bus.
The device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-saving 8-
lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead UDFN, and 8-ball VFBGA pack-
ages. The M voltage range devices operate from 1.7V to 3.6V. The D voltage range devices
operate from 2.5V to 5.5V.
Figure 0-1.
Pin Configurations
8-lead SOIC
8-lead TSSOP
Pin Name
A0–A2
SDA
Function
A0
A1
VCC
1
2
3
4
8
7
6
5
A0
A1
1
2
3
4
8
7
6
5
VCC
Address Inputs
Serial Data
WP
SCL
SDA
WP
SCL
SDA
A2
A2
GND
GND
SCL
Serial Clock Input
Write Protect
WP
8-lead UDFN
8-ball VFBGA
8
7
6
5
1
2
3
4
VCC
8
7
6
5
1
2
3
4
A0
A1
A2
VCC
WP
SCL
A0
A1
A2
WP
SCL
SDA
GND
SDA
GND
Bottom View
Bottom View
8720A–SEEPR–9/10
1.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only,
and functional operation of the device at these
or any other conditions beyond those indicated
in the operational sections of this specification is
not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect
device reliability.
Operating Temperature..................–55°C to +125°C
Storage Temperature .....................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground..................... –1.0V to +7.0V
Maximum Operating Voltage............................6.25V
DC Output Current ..........................................5.0mA
Figure 1-1.
VCC
Block Diagram
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
LOAD
DEVICE
ADDRESS
COMPARATOR
COMP
DATA RECOVERY
EEPROM
LOAD
INC
A2
A1
A0
R/W
DATA WORD
ADDR/COUNTER
SERIAL MUX
Y DEC
DOUT/ACK
LOGIC
DIN
DOUT
Atmel AT24C512C
2
8720A–SEEPR–9/10
Atmel AT24C512C
2.
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-
ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly
to GND or to Vcc) for compatibility with other Atmel® AT24Cxx devices. When the pins are hardwired, as many as eight
512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device
Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are
left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is
connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using
10kΩ or less.
3
8720A–SEEPR–9/10
3.
Memory Organization
Atmel AT24C512C, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128 bytes each. Random
word addressing requires a 16-bit data word address.
Table 3-1.
Pin Capacitance(1)
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested
DC Characteristics
Table 3-2.
Symbol
VCC1
VCC2
ICC
Parameter
Test Condition
Min
Typ
Max
3.6
Units
V
Supply Voltage
Supply Voltage
Supply Current
Supply Current
1.7
2.5
5.5
V
VCC = 5.0V
READ at 400kHz
WRITE at 400kHz
2.0
mA
mA
µA
µA
µA
µA
µA
µA
V
ICC
VCC = 5.0V
3.0
VCC = 1.7V
1.0
ISB1
Standby Current
Standby Current
VIN = VCC or VSS
VIN = VCC or VSS
VCC = 3.6V
3.0
VCC = 2.5V
2.0
ISB2
VCC = 5.5V
6.0
ILI
Input Leakage Current
Output Leakage Current
Input Low Level(1)
Input High Level(1)
Output Low Level
VIN = VCC or VSS
VIN = VCC or VSS
0.10
0.05
3.0
ILO
3.0
VIL
–0.6
VCC x 0.3
VCC + 0.5
0.2
VIH
VCC x 0.7
V
VOL1
VOL2
Note:
VCC = 1.7V
VCC = 3.0V
IOL = 0.15mA
IOL = 2.1mA
V
Output Low Level
0.4
V
1. VIL min and VIH max are reference only and are not tested
Atmel AT24C512C
4
8720A–SEEPR–9/10
Atmel AT24C512C
Table 3-3.
AC Characteristics (Industrial Temperature)
1.7V
2.5-5.0V
Symbol
fSCL
Parameter
Min
Max
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
400
1000
tLOW
tHIGH
ti
1.3
0.6
0.4
0.4
µs
100
0.9
50
ns
tAA
0.05
1.3
0.05
0.5
0.55
µs
Time the bus must be free before a
new transmission can start(1)
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
0.25
0.25
0
µs
µs
µs
ns
µs
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
100
100
0.3
0.3
tF
300
100
tSU.STO
tDH
0.6
50
0.25
50
tWR
5
5
Write
Cycles
Endurance(1)
25°C, Page Mode, 3.3V
1,000,000
Notes: 1. This parameter is ensured by characterization only
2. AC measurement conditions:
RL (connects to VCC): 1.3kΩ (2.5V, 5V), 10 kΩ (1.7V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤ 50ns
Input and output timing reference voltages: 0.5VCC
5
8720A–SEEPR–9/10
4.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (see Figure 4-4 on page 7). Data changes during SCL high periods will indicate
a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see Figure 4-5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 4-5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The Atmel® AT24C512C features a low-power standby mode which is enabled: a) upon power up and
b) after the receipt of the STOP bit and the completion of any internal operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be protocol reset
by following these steps: (a) Create a start condition, (b) clock nine cycles, (c) create another start condition followed by
a stop condition, as shown below. The device is ready for the next communication after the above steps have been
completed.
Figure 4-1.
Protocol Reset Condition
Dummy Clock Cycles
Start bit
Stop bit
Start bit
1
2
3
8
9
SCL
SDA
Figure 4-2.
SCL
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
tHIGH
tF
tR
tLOW
tLOW
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Atmel AT24C512C
6
8720A–SEEPR–9/10
Atmel AT24C512C
Figure 4-3.
SCL
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
ACK
SDA
8th BIT
WORDn
(1)
t
wr
START
STOP
CONDITION
CONDITION
Notes: 1. The write cycle time, tWR, is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle
Figure 4-4.
SDA
Data Validity
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 4-5.
SDA
Start and Stop Definition
SCL
START
STOP
7
8720A–SEEPR–9/10
Figure 4-6.
SCL
Output Acknowledge
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
5.
6.
8
Device Addressing
The 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write
operation (see Figure 7-1 on page 9). The device address word consists of a mandatory one-zero sequence for the first
four most-significant bits, as shown. This is common to all two-wire EEPROM devices.
The 512K uses the three device address bits A2, A1, and A0 to allow as many as eight devices on the same bus. These
bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit
that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and
a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to
a standby state.
DATA SECURITY: The Atmel® AT24C512C has a hardware data protection scheme that allows the user to write protect
the whole memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit
data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a
microcontroller, then must terminate the write sequence with a stop condition. At this time, the EEPROM enters an
internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle, and the
EEPROM will not respond until the write is complete (see Figure 7-2 on page 10).
PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can
transmit up to 127 more data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (see Figure 7-3 on page 10).
Atmel AT24C512C
8720A–SEEPR–9/10
Atmel AT24C512C
The data word address lower seven bits are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 128
data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.
The address roll over during write is from the last byte of the current page to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero, allowing the read or write sequence to continue.
7.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write select bit in the
device address word is set to one. There are three read operations: current address read, random address read, and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll over during read is from the last byte of the last memory page to the first byte of the first
page.
Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input zero, but does
generate a following stop condition (see Figure 7-4 on page 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another start condition. The microcontroller now initiates a current address read by sending a device address with
the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The
microcontroller does not respond with a zero, but does generate a following stop condition (see Figure 7-5 on page 10).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge,
it will continue to increment the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read
operation is terminated when the microcontroller does not respond with a zero but does generate a following stop
condition (see Figure 7-6 on page 10).
Figure 7-1.
Device Address
1
0
1
0
A2
A1
A0
R/W
LSB
MSB
9
8720A–SEEPR–9/10
Figure 7-2.
Byte Write
Figure 7-3.
Page Write
Figure 7-4.
Current Address Read
Figure 7-5.
Random Read
Figure 7-6.
Sequential Read
Atmel AT24C512C
10
8720A–SEEPR–9/10
Atmel AT24C512C
8.
Ordering Code Detail
A T 2 4 C 5 1 2 C - S S H M - B
Atmel Designator
Product Family
Shipping Carrier Option
B or blank = Bulk (tubes)
T
= Tape and reel
Operating Voltage
M = 1.7V to 3.6V
D
= 2.5V to 5.5V
Device Density
Package Device Grade or
Wafer/Die Thickness
512 = 512k
H
= Green, NiPdAu lead finish,
Industrial Temperature range
(-40°C to +85°C)
Device Revision
U = Green, matte Sn lead finish,
Industrial Temperature range
(-40°C to +85°C)
11 = 11mil wafer thickness
Package Option
SS
S
X
= JEDEC SOIC
= EIAJ SOIC
= TSSOP
MA = UDFN
= VFBGA
WWU = Wafer unsawn
C
11
8720A–SEEPR–9/10
9.
Part Markings
Atmel AT24C512C-SSHM
Top Marking Only
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
2 F C M
@
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 2FC=AT24C512C, M=1.7 to 3.6V, @=COUNTRY OF ASSEMBLY
LINE 3: ATMEL LOT NUMBER
No Bottom Marking
Atmel AT24C512C-SHM
Top Marking Only
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
2 F C M
@
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 2FC=AT24C512C, M=1.7 to 3.6V, @=COUNTRY OF ASSEMBLY
LINE 3: ATMEL LOT NUMBER
No Bottom Marking
Atmel AT24C512C
12
8720A–SEEPR–9/10
Atmel AT24C512C
Atmel AT24C512C-XHM
Top Marking Only
PIN 1 INDICATOR (DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
2 F C M
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: AT=ATMEL, H=MATERIAL SET/GRADE, YWW=DATE CODE
LINE 2: 2FC=AT24C512C, M=1.7 to 3.6V, @=COUNTRY OF ASSEMBLY
LINE 3: ATMEL LOT NUMBER
No Bottom Marking
Atmel AT24C512C-MAHM
Top Marking Only
|---|---|---|
2 F C
|---|---|---|
H M @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 2FC=AT24C512C
LINE 2: H=MATERIAL SET/GRADE, M=1.7 to 3.6V, @=COUNTRY OF ASSEMBLY
LINE 3: Y=DATE CODE, XX=Trace Code
No Bottom Marking
Atmel AT24C512C-CUM
Top Marking Only
|---|---|---|---|---|
2 F C U
|---|---|---|---|---|
@ Y M X X
|---|---|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 2FC=AT24C512C, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=Trace Code
No Bottom Marking
13
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Atmel AT24C512C-SSHD
Top Marking Only
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
2 F C D
@
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 2FC=AT24C512C, D=2.5 to 5.5V, @=COUNTRY OF ASSEMBLY
LINE 3: ATMEL LOT NUMBER
No Bottom Marking
Atmel AT24C512C-SHD
Top Marking Only
|---|---|---|---|---|---|---|---|
A T M L H Y W W
|---|---|---|---|---|---|---|---|
2 F C D
@
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1: ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
LINE 2: 2FC=AT24C512C, D=2.5 to 5.5V, @=COUNTRY OF ASSEMBLY
LINE 3: ATMEL LOT NUMBER
No Bottom Marking
Atmel AT24C512C
14
8720A–SEEPR–9/10
Atmel AT24C512C
Atmel AT24C512C-XHD
Top Marking Only
PIN 1 INDICATOR (DOT)
| |---|---|---|---|---|---|
* A T H Y W W
|---|---|---|---|---|---|
2 F C D
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1: AT=ATMEL, H=MATERIAL SET/GRADE, YWW=DATE CODE
LINE 2: 2FC=AT24C512C, M=2.5 to 5.5V, @=COUNTRY OF ASSEMBLY
LINE 3: ATMEL LOT NUMBER
No Bottom Marking
Atmel AT24C512C-MAHD
Top Marking Only
|---|---|---|
2 F C
|---|---|---|
H D @
|---|---|---|
Y X X
|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 2FC=AT24C512C
LINE 2: H=MATERIAL SET/GRADE, D=2.5 to 5.5V, @=COUNTRY OF ASSEMBLY
LINE 3: Y=DATE CODE, XX=Trace Code
No Bottom Marking
Atmel AT24C512C-CUD
Top Marking Only
|---|---|---|---|---|
2 F C U
|---|---|---|---|---|
@ Y D X X
|---|---|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
LINE 1: 2FC=AT24C512C, U=MATERIAL SET/GRADE
LINE 2: YM=DATE CODE, XX=Trace Code
No Bottom Marking
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8720A–SEEPR–9/10
10. Ordering Codes
Atmel AT24C512C Ordering Information
Ordering Code
Voltage
Package
Operation Range
AT24C512C-SSHM-B(1)(NiPdAu Lead Finish)
AT24C512C-SSHM-T(2) (NiPdAu Lead Finish)
AT24C512C-SSHD-B(1) (NiPdAu Lead Finish)
AT24C512C-SSHD-T(2) (NiPdAu Lead Finish)
AT24C512C-SHM-B(1) (NiPdAu Lead Finish)
AT24C512C-SHM-T(2) (NiPdAu Lead Finish)
AT24C512C-SHD-B(1) (NiPdAu Lead Finish)
AT24C512C-SHD-T(2) (NiPdAu Lead Finish)
AT24C512C-XHM-B(1) (NiPdAu Lead Finish)
AT24C512C-XHM-T(2) (NiPdAu Lead Finish)
AT24C512C-XHD-B(1) (NiPdAu Lead Finish)
AT24C512C-XHD-T(2) (NiPdAu Lead Finish)
AT24C512C-MAHM-T(2) (NiPdAu Lead Finish)
AT24C512C-MAHD-T(2) (NiPdAu Lead Finish)
AT24C512C-CUM-T(2) (matte Sn)
1.7V to 3.6V
1.7V to 3.6V
2.5V to 5.5V
2.5V to 5.5V
1.7V to 3.6V
1.7V to 3.6V
2.5V to 5.5V
2.5V to 5.5V
1.7V to 3.6V
1.7V to 3.6V
2.5V to 5.5V
2.5V to 5.5V
1.7V to 3.6V
2.5V to 5.5V
1.7V to 3.6V
2.5V to 5.5V
8S1
8S1
8S1
8S1
8S2
8S2
8S2
8S2
8A2
8A2
8A2
8A2
8Y6
8Y6
8U2
8U2
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
AT24C512C-CUD-T(2) (matte Sn)
AT24C512C-WWU11M(3)
AT24C512C-WWU11D(3)
1.7V to 3.6V
2.5V to 5.5V
Industrial Temperature
Die Sale
(−40 to 85°C)
Note:
1. "-B" denotes bulk delivery
2. "-T" denotes tape and reel delivery. SOIC = 4K/reel, TSSOP, UDFN, and VFBGA = 5K/reel
3. For wafer sales, please contact Atmel Sales
Package Type
8S1
8S2
8A2
8Y6
8U2
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8-lead, 4.4mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Dual No Lead Package (UDFN)
8-ball, 2.35 x 3.73mm Body, 0.75mm Pitch, Small Die Ball Grid Array (VFBGA)
Atmel AT24C512C
16
8720A–SEEPR–9/10
Atmel AT24C512C
11. Package Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
–
D
–
–
–
SIDEE VIEW
e
1.27 BSC
Notes: This drawing is for general information only.
L
0.40
0°
–
–
1.27
8°
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
Ø
5/19/10
REV.
TITLE
GPC
SWB
DRAWING NO.
8S1
Package Drawing Contact:
packagedrawings@atmel.com
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
F
17
8720A–SEEPR–9/10
8S2 – EIAJ SOIC
C
1
E
E1
L
End View
N
Top View
q
e
b
A
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0˚
NOM
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8˚
NOTE
A
A1
b
D
Side View
4
4
C
D
E1
E
Notes: 1. This drawing is for general information only; refer to EIAJ
Drawing EDR-7320 for additional information
2. Mismatch of the upper and lower dies and resin burrs are
not included
2
3. Determines the true geometric position
4. Values b,C apply to plated terminal. The standard
thickness of the plating layer shall measure between
0.007 to .021mm
L
q
3
e
1.27 BSC
4/15/08
REV.
TITLE
GPC
STN
DRAWING NO.
8S2
Package Drawing Contact:
packagedrawings@atmel.com
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
F
Atmel AT24C512C
18
8720A–SEEPR–9/10
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
2.90
MAX
3.10
NOM
3.00
NOTE
2, 5
SYMBOL
D
A
E
6.40 BSC
4.30
b
E1
A
4.40
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
1.00
e
A2
0.19
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25mm (0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/19/10
REV.
TITLE
GPC
TNR
DRAWING NO.
8A2
Package Drawing Contact:
packagedrawings@atmel.com
8A2, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
E
Atmel AT24C512C
19
8720A–SEEPR–9/10
Atmel AT24C512C
8Y6 – UDFN
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A1
A2
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
2.00 BSC
3.00 BSC
1.50
MAX
NOTE
D
E
1.60
1.40
0.60
0.05
0.55
D2
E2
A
1.40
–
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
–
–
–
2. Dimension b applies to metallized terminal and is
measured between 0.15mm and 0.30mm from the
A1
A2
A3
L
0.00
–
0.02
terminal tip. If the terminal has the optional radius on the
other end of the terminal, the dimension should not be
measured in that radius area.
–
0.20 REF
0.30
3. Soldering the large thermal pad is optional, but not
0.40
0.30
0.20
0.20
recommended. No electrical connection is accomplished to
the device through this pad, so if soldered it should be tied
to ground
e
0.50 BSC
0.25
2
b
11/21/08
REV.
TITLE
GPC
YNZ
DRAWING NO.
8Y6
Package Drawing Contact:
packagedrawings@atmel.com
8Y6, 8-lead, 2.0x3.0mm Body, 0.50mm Pitch,
UltraThin Mini-MAP, Dual No Lead Package
(Sawn)(UDFN)
E
20
8720A–SEEPR–9/10
8U2-1 – dBGA2
f 0.10
C
d 0.10
(4X)
d 0.08
C
A1 BALL
PAD
CORNER
C
D
A
A1 BALL PAD CORNER
2
1
Øb
A
B
C
D
j n0.15 m C A B
j n0.08 m C
e
E
B
(e1)
A1
A2
A
d
(d1)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
8 SOLDER BALLS
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
NOTE
SYMBOL
A
A1
A2
b
0.81 0.91 1.00
0.15 0.20 0.25
0.40 0.45 0.50
0.25 0.30 0.35
2.35 BSC
D
Notess:
E
3.73 BSC
1. TThhiiss ddrraawwiinngg iiss ffoorr ggeenneerraall
e
0.75 BSC
e1
d
0.74 REF
0.75 BSC
2. DDiimmeennssiioonn ''bb'' iiss mmeeaassuurreedd aatt tthhee mmaaxxiimmuumm ssoollddeerr bbaallll ddiiaammeetteerr..
3. SSolderr bbaallll ccoommppoossiittiioonn sshhaallll bbee 9955..55SSnn--44..00AAgg--..55CCuu..
d1
0.80 REF
07/23/10
TITLE
GPC
DRAWING NO.
8U2-1
REV.
Package Drawing Contact:
packagedrawings@atmel.com
8U2-1, 8-ball, 2.35 x 3.73 mm Body,
0.75 mm pitch, VFBGA Package (dBGA2)
GWW
E
Atmel AT24C512C
21
8720A–SEEPR–9/10
Atmel AT24C512C
12. Revision History
Doc. Rev.
Date
Comments
8720A
9/2010
Initial document release
22
8720A–SEEPR–9/10
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相关型号：
AT24C512C-MAHD-T
EEPROM, 64KX8, Serial, CMOS, PDSO8, 2 X 3 MM, 0.50 MM PITCH, GREEN, MO-229, UDFN-8
ATMEL
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