AT24C64D-SSHM-B [ATMEL]
EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8;
| 型号： | AT24C64D-SSHM-B |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, PLASTIC, MS-012AA, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总24页 (文件大小：1080K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT24C64D
I2C-Compatible (2-Wire) Serial EEPROM
64-Kbit (8,192 x 8)
DATASHEET
Features
Low-voltage and standard-voltage operation
VCC = 1.7V to 5.5V
Internally organized as 8,192 x 8 (64K)
I2C-compatible (2-Wire) serial interface
Schmitt Trigger, filtered inputs for noise suppression
Bidirectional data transfer protocol
400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) compatibility
Write Protect pin for hardware protection
32-byte Page Write mode
Partial Page Writes allowed
Self-timed Write cycle (5ms max)
High reliability
Endurance: 1,000,000 write cycles
Data retention: 100 years
Lead-free/Halogen-free devices available
Green package options (Pb/Halide-free/RoHS compliant)
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 6-ball WLCSP,
5-ball WLCSP, and 8-ball VFBGA packages
Die sale options: wafer form, waffle pack, and bumped wafers
Description
The Atmel® AT24C64D provides 65,536-bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 8,192 words of eight bits
each. The device’s cascading feature allows up to eight devices to share a common
2-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices are
available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN,
8-pad XDFN, 6-ball WLCSP, 5-ball WLCSP, and 8-ball VFBGA packages. In addition,
this device operates from 1.7V to 5.5V.
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
1.
Pin Configurations and Pinouts
Table 1-1. Pin Configuration
8-lead SOIC
8-lead TSSOP
Pin
A0
Function
A0
A1
VCC
WP
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A0
A1
VCC
WP
SCL
SDA
Address Input
Address Input
Address Input
Ground
A2
A2
SCL
SDA
A1
GND
GND
A2
Top View
Top View
GND
SDA
SCL
WP
VCC
8-pad UDFN/XDFN
6-ball WLCSP (1)
Serial Data
SCL
SDA
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Serial Clock Input
Write Protect
Device Power Supply
WP
GND
V
A
2
CC
GND
Top View
Bottom View
8-ball VFBGA
Note: 1. For use of the 6-ball WLCSP package,
the software bits A1 and A0 in the device
address word must be set to Logic 0 to
properly communicate. See Section 7.
Device Addressing on page 9 for more
details.
5-ball WLCSP (2)
8
7
6
5
1
2
3
4
VCC
WP
A0
GND
V
CC
A1
SDA
SCL
SDA
A2
SCL
WP
GND
2. For use of the 5-ball WLCSP package,
the three device address pins are not
available. For proper comunication with
the device, the software bits A2 and A1
must be set to Logic 0, while software bit
Bottom View
Bottom View
* Note: Drawings are not to scale
A0 must be set to Logic 1, resulting in a ‘001’ string in the device address byte for bits 3, 2, and 1. See
Section 7. Device Addressing on page 9 for more details.
2.
Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification are not implied. Exposure to
absolute maximum rating conditions for
Operating Temperature . . . . . . . . . . .−55°C to +125°C
Storage Temperature . . . . . . . . . . . −65°C to + 150°C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . . − 1.0 V +7.0V
Maximum Operating Voltage. . . . . . . . . . . . . . . 6.25V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . 5.0mA
extended periods may affect device reliability.
2
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
3.
Block Diagram
V
CC
GND
WP
Start
Stop
Logic
SCL
SDA
Serial
Control
Logic
EN
H.V. Pump/Timing
Data Recovery
LOAD
COMP
Device
Address
Comparator
LOAD
INC
A2
A1
A0
R/W
Data Word
Addr/Counter
EEPROM
Y DEC
Serial MUX
DOUT/ACK
LOGIC
DIN
DOUT
4.
Pin Descriptions
Serial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge
clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device Addresses (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hard wired (directly to GND
or to VCC) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight 64K devices
may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7., “Device Addressing”
on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10k or less.
Write Protect (WP): The Write Protect input, when connected to GND, allows normal Write operations. When WP is
connected directly to VCC, all Write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND: however, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using
10k or less.
Table 4-1. Write Protect
WP Pin Status
At VCC
Part of the Array Protected
Full Array
At GND
Normal Read/Write Operations
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
3
5.
Memory Organization
AT24C64D, 64K Serial EEPROM: The 64K is internally organized as 256 pages of 32-bytes each. Random word
addressing requires a 13-bit data word address.
Table 5-1. Pin Capacitance(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0MHz, VCC = 5.5V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, and SCL)
CIN
6
pF
Note: 1. This parameter is characterized and is not 100% tested.
Table 5-2. DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted)
Symbol
VCC1
ICC1
Parameter
Test Condition
Min
Typ
Max
5.5
1.0
3.0
1.0
6.0
Units
V
Supply Voltage
Supply Current
Supply Current
1.7
VCC = 5.0V
VCC = 5.0V
VCC = 1.7V
VCC = 5.0V
Read at 400kHz
Write at 400kHz
0.4
2.0
mA
mA
μA
ICC2
ISB1
Standby Current
VIN = VCC or VSS
μA
Input Leakage
Current VCC = 5.0V
ILI
VIN = VCC or VSS
0.10
0.05
3.0
3.0
μA
μA
Output Leakage
Current VCC = 5.0V
ILO
VOUT = VCC or VSS
VIL
Input Low Level(1)
Input High Level((1)
Output Low Level
Output Low Level
-0.6
VCC x 0.3
VCC + 0.5
0.2
V
V
V
V
VIH
VCC x 0.7
VOL1
VOL2
VCC = 1.7V
VCC = 3.0V
IOL = 0.15mA
IOL = 2.1mA
0.4
Note: 1. VIL min and VIH max are reference only and are not tested.
4
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
Table 5-3. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = 1.7V to 5.5V, CL = 100pF (unless
otherwise noted). Test conditions are listed in Note 2.
1.7V
Max
2.5V, 5.0V
Symbol
fSCL
Parameter
Min
Min
Max
Units
kHz
ns
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
400
1000
tLOW
tHIGH
tI
1300
600
400
400
ns
100
900
50
ns
tAA
50
50
500
250
250
0
550
ns
tBUF
Time the bus must be free before a new transmission can start(1) 1300
ns
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
600
600
0
ns
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
ns
ns
100
100
ns
300
300
300
100
ns
tF
ns
tSU.STO
tDH
600
50
250
50
ns
ns
tWR
5
5
ms
Write
Cycles
Endurance(1) 25°C, Page Mode, 3.3V
1,000,000
Notes: 1. This parameter is ensured by characterization and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤ 50ns
Input and output timing reference voltages: 0.5 x VCC
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
5
6.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (See Figure 6-1). Data changes during SCL high periods will indicate a start or
stop condition as defined below.
Figure 6-1. Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition that must precede every command
(See Figure 6-2).
Figure 6-2. Start and Stop Definition
SDA
SCL
Start
Condition
Stop
Condition
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a Read sequence, the Stop
Condition will place the EEPROM in a standby power mode (See Figure 6-2).
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
receiving device sends a zero during the ninth clock cycle to acknowledge that it has received each word. This zero
response is referred to as an Acknowledge (See Figure 6-6).
Standby Mode: The AT24C64D features a low-power standby mode that is enabled upon power-up and after the receipt
of the Stop condition and the completion of any internal operations.
6
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by
following these steps:
1. Create a Start condition,
2. Clock nine cycles,
3. Create another Start followed by Stop condition as shown below.
The device is ready for next communication after above steps has been completed.
Figure 6-3. Software Reset
Dummy Clock Cycles
1
2
3
8
9
SCL
SDA
Start
Condition
Start
Condition
Stop
Condition
Figure 6-4. Bus Timing
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tAA
tDH
tBUF
SDA Out
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
7
Figure 6-5. Write Cycle Timing
SCL
ACK
th
SDA
8
Bit
WORD
N
(1)
t
WR
Start
Condition
Stop
Condition
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle.
Figure 6-6. Output Acknowledge
1
8
9
SCL
Data In
Data Out
Start
Condition
Acknowledge
8
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
7.
Device Addressing
The 64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write
operation. The device address word consists of a mandatory ‘1010’ sequence for the first four most significant bits
(bit 7, bit 6, bit 5, and bit 4 as seen in Figure 7-1). This is common to all 2-wire Serial EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits to allow as many as eight devices on the same bus. These
bits must compare to their corresponding hard wired input pins, where applicable. The A2, A1, and A0 pins use an internal
proprietary circuit that pulls them to GND if the pins are allowed to float.
When utilizing the 6-ball WLCSP package, the A1 and A0 pins are not available and are internally pulled to ground;
therefore, the A1 and A0 device address bits must always be set to a Logic 0 condition to communicate with the device.
This condition is depicted in Figure 7-1 below.
When utilizing the 5-ball WLCSP package, the A2, A1 and A0 pins are not available. The A2 and A1 pins are internally
pulled to ground and thus the A2 and A1 device address bits must always be set to a Logic 0 condition to communicate
with the device. The A0 pin is internally connected to VCC in this specific package only; therefore, the A0 software bit must
be set to Logic 1 to communicate to the device. This condition is depicted in Figure 7-1 below.
The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit is high,
and a Write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return
to a standby state.
Figure 7-1. Device Addressing
Package
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SOIC,TSSOP,UDFN,
XDFN, and VFBGA
1
0
1
0
A2
A1
A0
R/W
6-ball WLCSP
5-ball WLCSP
1
0
0
1
1
0
0
A2
0
0
0
0
1
R/W
1
R/W
LSB
MSB
Data Security: AT24C64D has a hardware data protection scheme that allows the user to Write protect the whole
memory when the WP pin is at VCC
.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
9
8.
Write Operations
Byte Write: A Write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero, and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as
a microcontroller, must then terminate the Write sequence with a Stop condition. At this time, the EEPROM enters an
internally-timed Write cycle, tWR, to the nonvolatile memory (See Figure 6-5). All inputs are disabled during this Write
cycle and the EEPROM will not respond until the Write is complete (See Figure 8-1).
Figure 8-1. Byte Write
S
T
A
R
T
W
R
I
S
T
Device
First
Second
T
E
O
P
Data
Address
Word Address
Word Address
SDA Line
M
S
B
R A
A
C
K
A
C
K
A
C
K
/
C
W K
Note: * = Don’t care bit.
Page Write: The 64K EEPROM is capable of 32-byte Page Writes.
A Page Write is initiated the same way as a Byte Write, but the microcontroller does not send a Stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller
can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the Page Write sequence with a Stop condition (See Figure 8-2).
Figure 8-2. Page Write
S
T
A
R
T
W
R
I
S
T
Device
First
Second
T
E
O
P
Address
Data (n)
Data (n + x)
Word Address
Word Address
SDA Line
M
S
B
R A
/ C
A
C
K
A
C
K
A
C
K
A
C
K
W K
Note: * = Don’t care bit.
The data word address lower five bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32
data words are transmitted to the EEPROM, the data word address will roll-over and the previously loaded data will be
altered. The address roll-over during Write is from the last byte of the current page to the first byte of the same page.
Acknowledge Polling: Once the internally-timed Write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
Read/Write bit is representative of the operation desired. Only if the internal Write cycle has completed will the EEPROM
respond with a zero, allowing the Read or Write sequence to continue.
10
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
9.
Read Operations
Read operations are initiated the same way as Write operations with the exception that the Read/Write select bit in the
device address word is set to one. There are three Read operations:
Current Address Read
Random Address Read
Sequential Read
Current Address Read: The internal data word address counter maintains the last address accessed during the last
Read or Write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input zero but does
generate a Stop condition (See Figure 9-1).
Figure 9-1. Current Address Read
S
T
A
R
T
R
E
A
D
S
T
Device
O
P
Address
Data
SDA Line
M
S
B
R A
/ C
N
O
W K
A
C
K
Random Read: A Random Read requires a dummy Byte Write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another Start condition. The microcontroller now initiates a Current Address Read by sending a device address
with the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data
word. The microcontroller does not respond with a zero but does generate a Stop condition. (See Figure 9-2)
Figure 9-2. Random Read
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
Device
Address
First Word
Address
Second Word
Address
Device
Address
Data (n)
SDA LINE
M
S
B
R A
A
C
K
L A
S C
B K
R A
/ C
W K
N
O
/
C
W K
A
C
K
Dummy Write
Note: * = Don’t care bit.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
11
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the
memory address maximum address is reached, the data word address will roll-over and the Sequential Read will
continue from the beginning of the array. The Sequential Read operation is terminated when the microcontroller does not
respond with a zero but does generate a Stop condition (See Figure 9-3).
Figure 9-3. Sequential Read
S
T
A
R
T
W
R
I
Device
Address
First Word
Address
Second Word
Address
T
E
. . .
SDA LINE
M
S
B
R A
A
C
K
L A
S C
B K
/
C
W K
Dummy Write
S
T
A
R
T
R
E
A
D
S
T
Device
Address
O
P
Data (n)
Data (n + 1)
Data (n + 2)
Data (n + x)
. . .
R A
/ C
A
C
K
A
C
K
A
C
K
N
O
W K
A
C
K
Note: * = Don’t care bit.
12
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
10. Ordering Code Detail
A T 2 4 C 6 4 D - S S H M - B
Atmel Designator
Shipping Carrier Option
B
T
= Bulk (Tubes)
= Tape and Reel
Product Family
24C = Standard I2C Serial EEPROM
Operating Voltage
M
= 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
Device Density
64 = 64K
H
= Green, NiPdAu Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
= Green, Matte Sn Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
Device Revision
U
11 = 11mil Wafer Thickness
Package Option
SS
X
= JEDEC SOIC
= TSSOP
MA = UDFN
ME = XDFN
U
U1
C
= 6-ball, 2x3 Grid Array, WLCSP
= 5-ball, 3x3 Grid Array, WLCSP
= VFBGA
WWU = Wafer Unsawn
WDT = Die in Tape and Reel
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
13
11. Part Markings
AT24C64D: Package Marking Information
8-lead TSSOP
8-pad XDFN
8-lead SOIC
1.8 x 2.2 mm Body
ATHYWW
AAAAAAA
###
YXX
ATMLHYWW
###%
AAAAAAAA
###% @
@
8-ball VFBGA
8-pad UDFN
6-ball & 5-ball WLCSP
2.0 x 3.0 mm Body
1.5 x 2.0 mm Body
###
###U
YMXX
###%
H%@
YXX
UYMXX
PIN 1
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24C64D
Truncation Code ###: 64D
Date Codes
Voltages
Y = Year
2: 2012
3: 2013
4: 2014
5: 2015
M = Month
A: January
B: February
...
WW = Work Week of Assembly
% = Minimum Voltage
M: 1.7V min
6: 2016
7: 2017
8: 2018
9: 2019
02: Week 2
04: Week 4
...
L: December
52: Week 52
Country of Assembly
Lot Number
AAA...A = Atmel Wafer Lot Number
Grade/Lead Finish Material
@ = Country of Assembly
U: Industrial/Matte Tin/SnAguCu
H: Industrial/NiPdAu
Trace Code
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/8/13
TITLE
DRAWING NO.
REV.
24C64DSM, AT24C64D Package Marking Information
Package Mark Contact:
24C64DSM
D
DL-CSO-Assy_eng@atmel.com
14
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
12. Ordering Codes
12.1 Atmel AT24C64D Ordering Information
Ordering Code
Lead Finish
Package
Voltage
Operating Range
AT24C64D-SSHM-B(1)
8S1
AT24C64D-SSHM-T(2)
AT24C64D-XHM-B(1)
AT24C64D-XHM-T(2)
AT24C64D-MAHM-T(2)
AT24C64D-MEHM-T(2)
AT24C64D-UUM-T(2)
AT24C64D-U1UM-T(2)
AT24C64D-CUM-T(2)
AT24C64D-WWU11M(3)
NiPdAu
8X
(Lead-free/Halogen-free)
8MA2
8ME1
Industrial Temperature
1.7V to 5.5V
(−40°C to 85°C)
6U-1
SnAgCu
(Lead-free/Halogen-free)
5U-2
8U2-1
—
Wafer Sale
Notes: 1. Bulk delivery in tubes:
SOIC and TSSOP = 100 per tube
2. Tape and reel delivery:
SOIC = 4k per reel
TSSOP, UDFN, XDFN, WLCSP, and VFBGA = 5k per reel
3. Contact Atmel Sales for Wafer sales.
Package Type
8S1
8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.40mm body, Plastic Thin Shrink Small Outline (TSSOP)
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Dual No Lead (UDFN)
8-pad, 1.80mm x 2.20mm body, Extra Thin DFN (XDFN)
6-ball, 2x3 Grid Array, Wafer Level Chip Scale (WLCSP)
5-ball, 3x3 Grid Array, Wafer Level Chip Scale (WLCSP)
8-ball, Die Ball Grid Array (VFBGA)
8X
8MA2
8ME1
6U-1
5U-2
8U2-1
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
15
13. Packaging Information
13.1 8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
–
–
NOTE
SYMBOL
A1
A
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
1.27 BSC
L
0.40
0°
–
–
1.27
8°
Ø
6/22/11
DRAWING NO. REV.
8S1
TITLE
GPC
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
SWB
G
Package Drawing Contact:
packagedrawings@atmel.com
16
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
13.2 8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
e
A2
MIN
-
MAX
1.20
NOM
-
NOTE
2, 5
SYMBOL
D
A
Side View
A1
A2
D
0.05
0.80
2.90
-
0.15
Notes: 1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
1.00
3.00
1.05
3.10
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
E
6.40 BSC
4.50
E1
b
4.30
0.19
4.40
–
3, 5
4
0.30
e
0.65 BSC
0.60
L
0.45
0.75
-
L1
C
1.00 REF
0.09
0.20
6/22/11
TITLE
GPC
TNR
DRAWING NO.
REV.
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
8X
D
Package Drawing Contact:
packagedrawings@atmel.com
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
17
13.3 8MA2 — 8-pad UDFN
E
1
8
7
6
5
Pin 1 ID
2
3
4
D
C
A2
A1
A
E2
COMMON DIMENSIONS
(Unit of Measure = mm)
b (8x)
MIN
1.90
2.90
1.40
1.20
0.50
0.0
MAX
2.10
3.10
1.60
1.40
0.60
0.05
0.55
NOM
2.00
NOTE
SYMBOL
8
1
2
3
4
D
E
3.00
7
6
5
D2
E2
A
1.50
Pin#1 ID
D2
1.30
0.55
A1
A2
C
0.02
–
–
e (6x)
0.152 REF
0.35
L (8x)
K
L
0.30
0.40
e
0.50 BSC
0.25
b
0.18
0.20
0.30
–
3
K
–
9/6/12
DRAWING NO.
TITLE
GPC
REV.
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
YNZ
8MA2
C
Package Drawing Contact:
packagedrawings@atmel.com
18
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
13.4 8ME1 — 8-pad XDFN
D
7
5
4
6
3
8
E
PIN #1 ID
2
1
A1
Top View
A
Side View
e1
b
L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
NOM
–
MAX
0.40
0.05
1.90
2.30
0.25
NOTE
A
A1
D
E
0.10
PIN #1 ID
0.00
1.70
2.10
0.15
–
1.80
0.15
2.20
b
0.20
b
e
0.40 TYP
1.20 REF
0.30
e
e1
L
0.35
0.26
End View
9/10/2012
TITLE
DRAWING NO.
REV.
GPC
8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN
(XDFN)
8ME1
B
DTP
Package Drawing Contact:
packagedrawings@atmel.com
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
19
13.5 6U-1 — 6-ball WLCSP
BALL SIDE
2 1
TOP VIEW
A
D
A1 CORNER
A1 CORNER
1
2
3
3
d
0.015 C
A
A
B
d1
B
nb
e1
B
E
n
n
0.015m C
0.05
j
m C A B
A
A2
SIDE VIEW
C
d
0.075 C
A1
PIN ASSIGNMENT MATRIX
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
TYP
NOTE
SYMBOL
1
2
3
A
A1
A2
E
0.270
0.0779
0.175
0.309
-
0.348
0.139
0.225
SCL
SDA
WP
GND
VCC
A2
A
B
0.200
Contact Atmel for details
e1
D
0.40
Contact Atmel for details
0.40
d1
b
0.148
0.168
0.188
Note: 1. Dimensions are NOT to scale.
3/15/13
TITLE
DRAWING NO.
REV.
GPC
6U-1, 6-ball Wafer Level Chip Scale Package
(WLCSP)
GDM
6U-1
A
Package Drawing Contact:
packagedrawings@atmel.com
20
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
13.6 5U-2 — 5-ball WLCSP
BALL SIDE
TOP VIEW
A1 CORNER
e2
A1 CORNER
1 2 3
1
3 2
-B-
e1
A
B
C
A
d2
B
C
E
Øb(5X)
n 0.015m
n 0.05m C A B
C
j
d1
-A-
0.03 (4X)
D
d
d
0.03 C
SIDE VIEW
A
A2
Note: Dimensions are NOT to scale.
-C-
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
TYP
NOTE
SYMBOL
PIN ASSIGNMENT MATRIX
A
A1
A2
E
0.270
0.078
0.175
0.309
-
0.348
0.139
0.225
1
2
3
0.200
n/a
A
B
C
VCC
n/a
GND
n/a
Contact Atmel for details
e1
e2
D
0.693
SDA
n/a
0.3465
SCL
WP
Contact Atmel for details
d1
d2
b
0.4
0.4
0.148
0.168
0.188
7/30/13
TITLE
DRAWING NO.
REV.
GPC
5U-2, 5-ball Wafer Level Chip Scale Package
(WLCSP)
GPK
5U-2
A
Package Drawing Contact:
packagedrawings@atmel.com
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
21
13.7 8U2-1 — 8-ball VFBGA
f 0.10
C
d 0.10
(4X)
d 0.08
C
A1 BALL
D
C
A
A1 BALL PAD CORNER
PAD
2
1
CORNER
Øb
A
B
C
D
j n0.15 m C A B
j n0.08 m C
e
E
B
(e1)
A1
A2
A
d
(d1)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
8 SOLDER BALLS
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
NOTE
SYMBOL
A
0.81 0.91 1.00
0.15 0.20 0.25
0.40 0.45 0.50
0.25 0.30 0.35
2.35 BSC
A1
A2
b
D
Notes:
E
e
3.73 BSC
0.75 BSC
1. This drawing is for general information.
e1
d
d1
0.74 REF
0.75 BSC
0.80 REF
2. Dimension 'b' is measured at the maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
3/20/12
TITLE
GPC
DRAWING NO.
8U2-1
REV.
F
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
VFBGA Package
GWW
Package Drawing Contact:
packagedrawings@atmel.com
22
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
14. Revision History
Doc. Rev.
Date
Comments
8850A
08/2013
Inital document release.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
23
X
X X X X
X
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
© 2013 Atmel Corporation. / Rev.: Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013.
Atmel®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product
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