AT24HC04B-W-11 [ATMEL]
Two-wire Serial EEPROM 4K (512 x 8); 两线串行EEPROM 4K （ 512 ×8 ）
| 型号： | AT24HC04B-W-11 |
| 厂家： | 
ATMEL |
| 描述： | Two-wire Serial EEPROM 4K (512 x 8) |
| 文件： | 总19页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C04B
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 512 x 8 (4K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V) and 400 kHz (1.8V, 2.5V, 2.7V) Clock Rate
• 16-byte Page
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms Max)
• High Reliability
Two-wire Serial
EEPROM
4K (512 x 8)
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
AT24HC04B
• 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
Description
The AT24HC04B provides 4096 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 512 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The AT24HC04B is available in space-saving
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a
two-wire serial interface. In addition, the entire family is available in 1.8V (1.8V to
5.5V) version.
Table 0-1.
Pin Name
A1, A2
SDA
Pin Configuration
Function
8-lead TSSOP
NC
A1
1
2
3
4
8
7
6
5
VCC
WP
Address Inputs
Serial Data
A2
SCL
SDA
SCL
Serial Clock Input
Write Protect
No-connect
GND
WP
8-lead PDIP
NC
NC
A1
1
2
3
4
8
7
6
5
VCC
WP
A2
SCL
SDA
GND
8-lead SOIC
NC
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
GND
5227E–SEEPR–11/08
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature......................................−40°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 0-1. Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY
LOAD
COMP
DEVICE
ADDRESS
COMPARATOR
LOAD
INC
A2
A1
A0
R/W
DATA WORD
EEPROM
ADDR/COUNTER
Y DEC
SERIAL MUX
DOUT/ACK
LOGIC
DIN
DOUT
2
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
1. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2 and A1 pins are device address inputs that
must be hardwired for the AT24HC04B. As many as four 4K devices may be addressed on a
single bus system. The A0 pin is a no-connect. (Device addressing and Page addressing are
discussed in detail under Device Addressing and Page Addressing, page 8).
WRITE PROTECT (WP): The AT24HC04B has a WP pin that provides hardware data protec-
tion. The WP pin allows normal read/write operations when connected to ground (GND). When
the WP pin is connected to VCC, the write protection feature is enabled and operates as shown.
Table 1-1.
Write Protect
Part of the Array Protected
24HC04B
WP Pin Status
At VCC
Upper Half (2K) Array
Normal Read/Write Operations
At GND
3
5227E–SEEPR–11/08
2. Memory Organization
AT24HC04B, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16 bytes
each. Random word addressing requires an 9-bit data word address.
Table 2-1.
Applicable over recommended operating range from TAI = 25°C, f = 1.0 MHz, VCC = +1.8V
Pin Capacitance(1)
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
VCC1
VCC2
VCC3
VCC4
ICC
Parameter
Test Condition
Min
1.8
2.5
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V
Standby Current VCC = 2.5V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level (1)
READ at 100 kHz
WRITE at 100 kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ISB3
ISB4
ILI
0.6
3.0
1.4
4.0
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
−0.6
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Level (1)
VCC x 0.7
V
VOL2
VOL1
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
IOL = 0.15 mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
Table 2-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8, 2.5, 2.7
5.0-volt
Max
Symbol
fSCL
tLOW
tHIGH
tI
Parameter
Min
Max
Min
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
400
1000
1.2
0.6
0.4
0.4
µs
50
40
ns
tAA
0.1
1.2
0.9
0.05
0.5
0.55
µs
Time the bus must be free before a new
transmission can start
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
0.6
0.6
0
0.25
0.25
0
µs
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
µs
µs
100
100
ns
0.3
0.3
µs
tF
300
100
ns
tSU.STO
tDH
0.6
50
.25
50
µs
ns
tWR
5
5
ms
Endurance(1) 5.0V, 25°C, Byte Mode
Note: 1. This parameter is ensured by characterization only.
1 Million
Write Cycles
5
5227E–SEEPR–11/08
3. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 3-1).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
Figure 3-1. Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must
precede any other command (see Figure 3-2).
Figure 3-2. Start and Stop Definition
SDA
SCL
START
STOP
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 3-2).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words.. The EEPROM sends a “0” to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24HC04B features a low-power standby mode that is enabled: (a)
upon power-up and (b) after the receipt of the Stop bit and the completion of any internal
operations.
6
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b)
Clock nine cycles, (c) Create another start bit followed by stop bit condition as shown below. The
device is ready for next communication after above steps have been completed.
Figure 3-3. Software Reset
Dummy Clock Cycles
Start bit
Stop bit
Start bit
1
2
3
8
9
SCL
SDA
Figure 3-4. Bus Timing
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 3-5. Write Cycle Timing
SCL
ACK
SDA
8th BIT
WORDn
(1)
t
wr
START
CONDITION
STOP
CONDITION
Notes: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5227E–SEEPR–11/08
Figure 3-6. Output Acknowledge
SCL
1
8
9
DATA IN
DATA OUT
START
ACKNOWLEDGE
4. Device Addressing and Page Addressing
The 4K EEPROM device requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation, as shown in Figure 4-1.
Figure 4-1. Device Address
A
A
P
R/W
LSB
4K
1
0
1
0
0
2
1
MSB
The device address word consists of a mandatory “1”, “0” sequence for the first four most signif-
icant bits as shown. This is common to all the EEPROM devices.
The next two bits are the A2 and A1 device address bits for the 4K EEPROM. These two bits
must compare to their corresponding hardwired input pins. The A0 pin is a no-connect.
The next bit is the memory page address bit. This bit is the MSB of the 9-bit data word address.
The eighth bit of the device address is the read/write operation select bit. A read operation is ini-
tiated if this bit is high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,
the chip will return to a standby state.
8
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
5. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgement. Upon receipt of this address, the EEPROM will again
respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must
terminate the write sequence with a stop condition. At this time, the EEPROM enters an inter-
nally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write
cycle, and the EEPROM will not respond until the write is complete, see Figure 5-1 on page 9.
Figure 5-1. Byte Write
S
T
A
R
T
W
R
I
S
T
T
E
O
P
DEVICE
ADDRESS
WORD ADDRESS
DATA
SDA LINE
M
S
B
L R A M
L
A
A
C
K
/
S
C S
S C
W
B
K B
B K
PAGE WRITE: The 4K EEPROM is capable of a 16-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The
EEPROM will respond with a “0” after each data word received. The microcontroller must termi-
nate the page write sequence with a stop condition, see Figure 5-2.
Figure 5-2. Page Write
S
W
T
R
I
S
T
A
R
T
E
O
P
DEVICE
ADDRESS
T
WORD ADDRESS (n)
DATA (n)
DATA (n + 1)
DATA (n + x)
SDA LINE
M
S
B
L R A
A
C
K
A
C
K
A
C
K
A
C
K
/
S
C
B W K
The data word address lower four bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol-
lowing byte is placed at the beginning of the same page. If more than sixteen data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a “0” allowing the read or write sequence to continue.
9
5227E–SEEPR–11/08
6. Read Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to “1”. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll over”
during read is from the last byte of the last memory page to the first byte of the first page. The
address “roll over” during write is from the last byte of the current page to the first byte of the
same page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The microcontroller does
not respond with an input “0” but does generate a following stop condition, see Figure 6-1.
Figure 6-1. Current Address Read
S
T
A
R
T
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
SDA LINE
M
S
B
L R A
DATA
N
O
/
S
C
K
B
W
A
C
K
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a “0” but does generate a following
stop condition, see Figure 6-2.
Figure 6-2. Random Read
S
T
A
R
T
W
R
I
S
T
A
R
T
R
E
A
D
S
T
DEVICE
ADDRESS
T
E
O
P
DEVICE
ADDRESS
WORD
ADDRESS n
SDA LINE
M
S
B
L R A
L A
S C
B K
A
C
K
DATA n
N
O
M
S
B
M
S
B
L
S
B
/
S
C
K
B
W
A
C
K
DUMMY WRITE
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
10
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a “0” but
does generate a following stop condition, see Figure 6-3.
Figure 6-3. Sequential Read
11
5227E–SEEPR–11/08
7. AT24HC04B Ordering Information
Ordering Code
Voltage
Package
8P3
Operation Range
AT24HC04B-PU (Bulk form only)
1.8
1.8
1.8
1.8
1.8
AT24HC04BN-SH-B(1) (NiPdAu Lead Finish)
AT24HC04BN-SH-T(2) (NiPdAu Lead Finish)
AT24HC04B-TH-B(1) (NiPdAu Lead Finish)
AT24HC04B-TH-T(2) (NiPdAu Lead Finish)
8S1
Lead-free/Halogen-free/
Industrial Temperature
8S1
(−40°C to 85°C)
8A2
8A2
Industrial Temperature
AT24HC04B-W-11(3)
1.8
Die Sale
(−40°C to 85°C)
Notes: 1. “-B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
Package Type
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
Options
8P3
8S1
8A2
−1.8
Low Voltage (1.8V to 5.5V)
12
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
8. Part marking scheme
8-PDIP
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
|
Seal Week
6: 2006
0: 2010
02 = Week 2
|
|
|
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
|---|---|---|---|---|---|---|---|
50 = Week 50
52 = Week 52
H
4
B
1
|---|---|---|---|---|---|---|---|
Lot Number
*
Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
8-SOIC
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
02 = Week 2
|
Seal Week
6: 2006
0: 2010
|
|
|
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
50 = Week 50
52 = Week 52
H
4
B
1
|---|---|---|---|---|---|---|---|
Lot Number
*
Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
|
BOTTOM MARK
Pin 1 Indicator (Dot)
No Bottom Mark
13
5227E–SEEPR–11/08
8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
Y = SEAL YEAR
WW = SEAL WEEK
|
6: 2006
7: 2007
8: 2008
9: 2009
0: 2010
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
|---|---|---|---|
1: 2011
2: 2012
3: 2013
*
H
Y
W
W
|---|---|---|---|---|
H
4
B
1
50 = Week 50
52 = Week 52
|---|---|---|---|---|
BOTTOM MARK
|---|---|---|---|---|---|---|
X
X
XX = COUNTRY OF ORIGIN
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
TOP MARK
Seal Year
Y = SEAL YEAR
WW = SEAL WEEK
14
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
9. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
15
5227E–SEEPR–11/08
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0°
–
–
1.27
∅
8°
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
16
AT24HC04B
5227E–SEEPR–11/08
AT24HC04B
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
17
5227E–SEEPR–11/08
Revision History
Doc. Rev.
5227E
Date
Comments
11/2008
1/2008
8/2007
Updated pin configurations
Removed ‘preliminary’ status
Added Part Marking Scheme
5227D
5227C
Updated to new template
Updated Common figures
Added Part Marking tables
5227B
5227A
8/2007
4/2007
Initial document release.
18
AT24HC04B
5227E–SEEPR–11/08
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