AT25020N-10SC [ATMEL]
SPI Serial EEPROMs; SPI串行EEPROM
| 型号： | AT25020N-10SC |
| 厂家： | 
ATMEL |
| 描述： | SPI Serial EEPROMs |
| 文件： | 总15页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0(0,0) and 3(1,1)
• Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• 2.1 MHz Clock Rate (5V) Compatibility
• 8-Byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
• Self-Timed Write Cycle (10 ms Max)
• High Reliability
SPI Serial
EEPROMs
1K (128 x 8)
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP and JEDEC SOIC Packages
2K (256 x 8)
4K (512 x 8)
Description
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-pin PDIP and 8-pin JEDEC (SOIC) packages.
AT25010
AT25020
AT25040
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via
a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
SPI, 1K Serial
E2PROM
Pin Configurations
8-Pin PDIP
Pin Name Function
CS
Chip Select
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
WP
GND
SO
GND
VCC
WP
8-Pin SOIC
Power Supply
Write Protect
CS
SO
WP
1
8
7
6
5
VCC
HOLD
SCK
SI
2
3
4
HOLD
Suspends Serial Input
GND
Rev. 0606E–08/98
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature................................. -55°C to + 125°C
Storage Temperature.................................... -65°C to + 150°C
Voltage on Any Pin
with Respect to Ground....................................-1.0V to + 7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
AT25010/020/040
2
AT25010/020/040
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
COUT
Output Capacitance (SO)
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
1.8
2.7
4.5
Max
5.5
Units
V
(1)
VCC1
Supply Voltage
VCC2
VCC3
ICC1
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Current
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 5.0V at 1 MHz, SO = Open
VCC = 5.0V at 2 MHz, SO = Open
3.0
mA
mA
µA
µA
µA
µA
µA
V
ICC2
6.0
(1)
ISB1
VCC = 1.8V
VCC = 2.7V
VCC = 5.0V
VIN = 0V to VCC
CS = VCC
100
ISB2
ISB3
IIL
CS = VCC
CS = VCC
100
100
-0.6
-0.6
3.0
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(2)
VIL
-0.6
VCC x 0.3
VCC + 0.5
0.4
(2)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
IOL = 2.0 mA
V
IOH = -1.0 mA
IOL = 0.15 mA
IOH = -100 µA
VCC - 0.8
V
0.2
V
VCC - 0.2
V
Notes: 1. This parameter is preliminary and Atmel may change the specifications upon further characterization.
2. VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
2.1
2.1
0.5
fSCK
SCK Clock Frequency
MHz
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
tFI
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
800
tWH
tWL
tCS
tCSS
tCSH
tSU
tH
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
800
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
CS Setup Time
CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50
100
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
100
100
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
400
tHD
tCD
tV
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
400
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
200
400
800
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
tHO
Output Hold Time
AT25010/020/040
4
AT25010/020/040
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
100
100
100
tLZ
Hold to Output Low Z
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
100
tHZ
Hold to Output High Z
Output Disable Time
ns
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
500
1000
tDIS
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
10
tWC
Write Cycle Time
ms
Endurance
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
5
WP going low while CS is still low will interrupt a write to the
AT25010/020/040. If the internal write cycle has already
been initiated, WP going low will have no effect on any
write operation.
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an
input, the AT25010/020/040 always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010/020/040 has
separate pins designated for data transmission (SO) and
reception (SI).
SPI Serial Interface
MSB: The Most Significant Bit (MSB) is the first bit
transmitted and received.
SERIAL OP-CODE: After the device is selected with CS
going low, the first byte will be received. This byte contains
the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the
READ and WRITE instructions.
INVALID OP-CODE: If an invalid op-code is received, no
data will be shifted into the AT25010/020/040, and the
serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reini-
tialize the serial communication.
CHIP SELECT: The AT25010/020/040 is selected when
the CS pin is low. When the device is not selected, data will
not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS
pin to select the AT25010/020/040. When the device is
selected and a serial sequence is underway, HOLD can be
used to pause the serial communication with the master
device without resetting the serial sequence. To pause, the
HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought
high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow
normal read/write operations when held high. When the
WP pin is brought low, all write operations are inhibited.
AT25010/020/040
6
AT25010/020/040
Functional Description
Table 3. Read Status Register Bit Definition
The AT25010/020/040 is designed to interface directly with
the synchronous serial peripheral interface (SPI) of the
6805 and 68HC11 series of microcontrollers.
Bit
Definition
Bit 0 = 0 (RDY) indicates the device is
READY. Bit 0 = 1 indicates the write cycle
is in progress.
Bit 0 (RDY)
The AT25010/020/040 utilizes an 8-bit instruction register.
The list of instructions and their operation codes are con-
tained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low
CS transition.
Bit 1 = 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
See Table 4.
See Table 4.
Table 1. Instruction Set for the AT25010/020/040
Instruction
Name
Instruction
Format
Operation
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
WREN
WRDI
0000 X110
0000 X100
0000 X101
0000 X001
0000 A011
0000 A010
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRITE STATUS REGISTER (WRSR): The WRSR
instruction allows the user to select one of four levels of
protection. The AT25010/020/040 is divided into four array
segments. Top quarter (1/4), Top half (1/2), or all of the
memory segments can be protected. Any of the data within
any selected segment will therefore be READ only. The
block write protection levels and corresponding status reg-
ister control bits are shown in Table 4.
RDSR
WRSR
READ
WRITE
Note:
“A” represents MSB address bit A8.
WRITE ENABLE (WREN): The device will power up in
the write disable state when VCC is applied. All program-
ming instructions must therefore be preceded by a Write
Enable instruction. The WP pin must be held high during a
WREN instruction.
The two bits, BP1 and BP0 are nonvolatile cells that have
the same properties and functions as the regular memory
cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
Status
Register Bits
Array Addresses Protected
Level
0
BP1
BP0
AT25010
AT25020
None
AT25040
0
0
1
1
0
1
0
1
None
60-7F
40-7F
00-7F
None
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
1 (1/4)
2 (1/2)
3 (All)
C0-FF
80-FF
00-FF
180-1FF
100-1FF
000-1FF
READ
SEQUENCE
(READ): Reading
the
AT25010/020/040 via the SO (Serial Output) pin requires
the following sequence. After the CS line is pulled low to
select a device, the READ op-code (including A8) is trans-
mitted via the SI line followed by the byte address to be
read (A7-A0). Upon completion, any data on the SI line will
be ignored. The data (D7-D0) at the specified address is
then shifted out onto the SO line. If only one byte is to be
read, the CS line should be driven high after the data
comes out. The READ sequence can be continued since
the byte address is automatically incremented and data will
continue to be shifted out. When the highest address is
reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one con-
tinuous READ cycle.
Table 2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
BP1 BP0
Bit 1
Bit 0
X
X
X
X
WEN
RDY
7
WRITE SEQUENCE (WRITE): In order to program the
AT25010/020/040, the Write Protect pin (WP) must be held
high and two separate instructions must be executed. First,
the device must be write enabled via the Write Enable
(WREN) Instruction. Then a Write (WRITE) Instruction may
be executed. Also, the address of the memory location(s)
to be programmed must be outside the protected address
field location selected by the Block Write Protection Level.
During an internal write cycle, all commands will be ignored
except the RDSR instruction.
tion. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0
= 0, the WRITE cycle has ended. Only the READ STATUS
REGISTER instruction is enabled during the WRITE pro-
gramming cycle.
The AT25010/020/040 is capable of an 8-byte PAGE
WRITE operation. After each byte of data is received, the
three low order address bits are internally incremented by
one; the six high order bits of the address will remain con-
stant. If more than 8 bytes of data are transmitted, the
address counter will roll over and the previously written
data will be overwritten. The AT25010/020/040 is automati-
cally returned to the write disable state at the completion of
a WRITE cycle.
A Write Instruction requires the following sequence. After
the CS line is pulled low to select the device, the WRITE
op-code (including A8) is transmitted via the SI line fol-
lowed by the byte address (A7-A0) and the data (D7-D0) to
be programmed. Programming will start after the CS pin is
brought high. (The LOW to High transition of the CS pin
must occur during the SCK low time immediately after
clocking in the D0 (LSB) data bit.
Note:
If the WP pin is brought low or if the device is not Write
enabled (WREN), the device will ignore the Write instruc-
tion and will return to the standby state, when CS is
brought high. A new CS falling edge is required to re-ini-
tiate the serial communication.
The READY/BUSY status of the device can be determined
by initiating a READ STATUS REGISTER (RDSR) Instruc-
AT25010/020/040
8
AT25010/020/040
Timing Diagrams
Synchronous Data Timing (for mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
VIH
tH
SI
VALID IN
VIL
tHO
tDIS
tV
VOH
HI-Z
HI-Z
SO
VOL
WREN Timing
WRDI Timing
9
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14
15
0
SCK
INSTRUCTION
DATA IN
5
4
3
2
1
SI
HIGH IMPEDANCE
SO
READ Timing
AT25010/020/040
10
AT25010/020/040
WRITE Timing
CS
0
1
2
3
4
5
6
7
8
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
8
BYTE ADDRESS
2
DATA IN
3
6
5
4
3
1
0
7
6
5
4
2
1
0
9TH BIT OF ADDRESS
HIGH IMPEDANCE
SO
HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
11
AT25010 Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
10
6000
3000
3000
100
100
100
100
100
100
2000
2000
1000
1000
500
AT25010-10PC
AT25010-10SC
8P3
8S1
Commercial
(0°C to 70°C)
AT25010-10PI
AT25010-10SI
8P3
8S1
Industrial
(-40°C to 85°C)
AT25010-10PC-2.7
AT25010-10SC-2.7
8P3
8S1
Commercial
(0°C to 70°C)
AT25010-10PI-2.7
AT25010-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
AT25010-10PC-1.8
AT25010-10SC-1.8
8P3
8S1
Commercial
(0°C to 70°C)
500
AT25010-10PI-1.8
AT25010-10SI-1.8
8P3
8S1
Industrial
(-40°C to 85°C)
Package Type
8P3
8S1
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
AT25010/020/040
12
AT25010/020/040
AT25020 Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
10
6000
3000
3000
100
100
100
100
100
100
2100
2100
2100
2100
500
AT25020-10PC
8P3
8S1
Commercial
AT25020N-10SC
(0°C to 70°C)
AT25020-10PI
8P3
8S1
Industrial
AT25020N-10SI
(-40°C to 85°C)
AT25020-10PC-2.7
AT25020N-10SC-2.7
8P3
8S1
Commercial
(0°C to 70°C)
AT25020-10PI-2.7
AT25020N-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
AT25020-10PC-1.8
AT25020N-10SC-1.8
8P3
8S1
Commercial
(0°C to 70°C)
500
AT25020-10PI-1.8
AT25020N-10SI-1.8
8P3
8S1
Industrial
(-40°C to 85°C)
Package Type
8P3
8S1
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
13
AT25040 Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
10
6000
3000
3000
100
100
100
100
100
100
2100
2100
2100
2100
500
AT25040-10PC
8P3
8S1
Commercial
AT25040N-10SC
(0°C to 70°C)
AT25040-10PI
8P3
8S1
Industrial
AT25040N-10SI
(-40°C to 85°C)
AT25040-10PC-2.7
AT25040N-10SC-2.7
8P3
8S1
Commercial
(0°C to 70°C)
AT25040-10PI-2.7
AT25040N-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
AT25040-10PC-1.8
AT25040N-10SC-1.8
8P3
8S1
Commercial
(0°C to 70°C)
500
AT25040-10PI-1.8
AT25040N-10SI-1.8
8P3
8S1
Industrial
(-40°C to 85°C)
Package Type
8P3
8S1
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
AT25010/020/040
14
AT25010/020/040
Packaging Information
8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
Dimensions in Inches and (Millimeters)
.020 (.508)
.013 (.330)
.400 (10.16)
.355 (9.02)
PIN
1
.244 (6.20)
.228 (5.79)
.157 (3.99)
.150 (3.81)
.280 (7.11)
.240 (6.10)
PIN 1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.050 (1.27) BSC
.100 (2.54) BSC
SEATING
PLANE
.196 (4.98)
.189 (4.80)
.068 (1.73)
.053 (1.35)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.010 (.254)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
8
0
REF
REF
15
.010 (.254)
.007 (.203)
.012 (.305)
.008 (.203)
.430 (10.9) MAX
.050 (1.27)
.016 (.406)
15
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