AT25080B-PU [ATMEL]
SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8); SPI串行EEPROM 8K （ 1024 ×8 ）， 16K （ 2048 ×8 ）
| 型号： | AT25080B-PU |
| 厂家： | 
ATMEL |
| 描述： | SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8) |
| 文件： | 总22页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• 20 MHz Clock Rate (5V)
• 32-byte Page Mode
• Block Write Protection
SPI Serial
EEPROMs
8K (1024 x 8)
16K (2048 x 8)
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
• Self-timed Write Cycle (5 ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead
TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
AT25080B
AT25160B
Description
The AT25080B/160B provides 8192/16384 bits of serial electrically-erasable program-
mable read-only memory (EEPROM) organized as 1024/2048 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where
low-power and low-voltage operation are essential. The AT25080B/160B is available
in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP
2x3) and 8-lead TSSOP packages.
Preliminary
The AT25080B/160B is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate erase cycle is required before write.
Table 0-1.
Pin Name
CS
Pin Configuration
Function
8-lead PDIP
Chip Select
SCK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SI
WP
SO
GND
GND
VCC
Power Supply
Write Protect
WP
8-lead TSSOP
HOLD
Suspends Serial Input
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
WP
GND
5228B–SEEPR–7/08
8-lead SOIC
8-ball dBGA2
8-lead Ultra Thin Mini-MAP (MLP 2x3)
VCC
8
CS
SO
WP
SI
1
2
3
4
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
HOLD 7
SCK 6
SI 5
2 SO
3 WP
4 GND
WP
GND
Bottom View
Bottom View
Block write protection is enabled by programming the status register with one of four blocks of
write protection. Separate program enable and program disable instructions are provided for
additional data protection. Hardware data protection is provided via the WP pin to protect
against inadvertent write attempts to the status register. The HOLD pin may be used to suspend
any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature..................................–55°C to +125°C
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
2
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
Figure 0-1. Block Diagram
Table 0-2.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 0-3.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
VCC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
VCC2
5.5
V
VCC3
5.5
V
ICC1
VCC = 5.0V at 20 MHz, SO = Open, Read
7.5
4.0
10.0
mA
VCC = 5.0V at 20 MHz, SO = Open, Read,
ICC2
Supply Current
10.0
mA
Write
3
5228B–SEEPR–7/08
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
VCC = 5.0V at 5 MHz, SO = Open,
Read, Write
ICC3
Supply Current
4.0
6.0
mA
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V, CS = VCC
VCC = 2.7V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
< 0.1
0.3
6.0(2)
7.0(2)
µA
µA
µA
µA
µA
V
2.0
10.0(2)
–3.0
–3.0
3.0
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
–0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
I
OL = 3.0 mA
V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
IOH = −1.6 mA
VCC - 0.8
VCC - 0.2
V
IOL = 0.15 mA
0.2
V
IOH = −100 µA
V
Notes: 1. VIL min and VIH max are reference only and are not tested.
2. Worst case measured at 85°C
4
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
Table 0-4.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
20
10
5
fSCK
SCK Clock Frequency
MHz
4.5–5.5
2.7–5.5
1.8–5.5
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
µs
µs
ns
4.5–5.5
2.7–5.5
1.8–5.5
2
2
2
tFI
20
40
4.5–5.5
2.7–5.5
1.8–5.5
tWH
80
20
40
4.5–5.5
2.7–5.5
1.8–5.5
tWL
tCS
tCSS
tCSH
tSU
tH
SCK Low Time
CS High Time
ns
ns
ns
ns
ns
ns
80
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
CS Setup Time
CS Hold Time
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
Data In Setup Time
Data In Hold Time
HOLD Setup Time
HOLD Hold Time
Output Valid
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
tHD
tCD
tV
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
ns
ns
ns
20
40
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
80
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
tHO
Output Hold Time
5
5228B–SEEPR–7/08
Table 0-4.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
25
50
100
tLZ
HOLD to Output Low Z
ns
4.5–5.5
2.7–5.5
1.8–5.5
40
80
200
tHZ
HOLD to Output High Z
Output Disable Time
ns
ns
4.5–5.5
2.7–5.5
1.8–5.5
40
80
200
tDIS
4.5–5.5
2.7–5.5
1.8–5.5
5
5
5
tWC
Write Cycle Time
ms
Endurance(1)
3.3V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
1. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080B/160B always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25080B/160B has separate pins designated for data trans-
mission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25080B/160B, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25080B/160B is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a
high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080B/160B.
When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communi-
cation, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg-
ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
6
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is “0”. This will allow the user to install the AT25080B/160B in a system with the WP pin
tied to ground and still be able to write to the status register. All WP pin functions are enabled
when the WPEN bit is set to “1”.
Figure 1-1. SPI Serial Interface
AT25080B/160B
2. Functional Description
The AT25080B/160B is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25080B/160B utilizes an 8-bit instruction register. The list of instructions and their opera-
tion codes are contained in Table 2-1. All instructions, addresses, and data are transferred with
the MSB first and start with a high-to-low CS transition.
Table 2-1.
Instruction Set for the AT25080B/160B
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
WRDI
0000 X100
RDSR
0000 X101
7
5228B–SEEPR–7/08
Table 2-1.
Instruction Set for the AT25080B/160B
Instruction Name
WRSR
Instruction Format
0000 X001
Operation
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
READ
0000 X011
WRITE
0000 X010
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protec-
tion employed. These bits are set by using the WRSR instruction.
Table 2-2.
Bit 7
Status Register Format
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 2-3.
Bit
Read Status Register Bit Definition
Definition
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 0 (RDY)
Bit 1 (WEN)
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
Bit 2 (BP0)
Bit 3 (BP1)
See Table 2-4 on page 9.
See Table 2-4 on page 9.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 2-5 on page 9.
Bits 0–7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080B/160B is divided into four array segments. One-quarter,
one-half, or all of the memory segments can be protected. Any of the data within any selected
segment will therefore be read only. The block write protection levels and corresponding status
register control bits are shown in Table 2-4.
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, tWC, RDSR).
8
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
Table 2-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
AT25080B AT25160B
None None
Level
0
BP1
BP0
0
0
1
1
0
1
0
1
1(1/4)
2(1/2)
3(All)
0300−03FF
0200−03FF
0000−03FF
0600−07FF
0400−07FF
0000−07FF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the status register, including the block protect bits and the WPEN bit, and the block-pro-
tected sections in the memory array are disabled. Writes are only allowed to sections of the
memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as
long as the WP pin is held low.
Table 2-5.
WPEN Operation
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
X
WEN
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writeable
Protected
Writeable
Protected
Writeable
Protected
Writeable
Protected
Protected
Protected
Writeable
X
Low
Low
High
High
READ SEQUENCE (READ): Reading the AT25080B/160B via the Serial Output (SO) pin
requires the following sequence. After the CS line is pulled low to select a device, the read op-
code is transmitted via the SI line followed by the byte address to be read (A15–A0, see Table 2-
6). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the specified
address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The read sequence can be continued since the byte
address is automatically incremented and data will continue to be shifted out. When the highest
address is reached, the address counter will roll over to the lowest address allowing the entire
memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080B/160B, two separate instruc-
tions must be executed. First, the device must be write enabled via the WREN instruction.
Then a write (WRITE) instruction may be executed. Also, the address of the memory location(s)
to be programmed must be outside the protected address field location selected by the block
write protection level. During an internal write cycle, all commands will be ignored except the
RDSR instruction.
9
5228B–SEEPR–7/08
A write instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15–A0)
and the data (D7–D0) to be programmed (see Table 2-6). Programming will start after the CS pin
is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time
immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle
has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25080B/160B is capable of a 32-byte page write operation. After each byte of data is
received, the five low-order address bits are internally incremented by one; the high-order bits of
the address will remain constant. If more than 32 bytes of data are transmitted, the address
counter will roll over and the previously written data will be overwritten. The AT25080B/160B is
automatically returned to the write disable state at the completion of a write cycle.
NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to
reinitiate the serial communication.
Table 2-6.
Address Key
Address
AN
Don’t Care Bits
AT25080B
A9–A0
AT25160B
A10–A0
A15–A10
A15–A11
3. Timing Diagrams
Figure 3-1. Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
tH
VIH
VIL
SI
VALID IN
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
10
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
Figure 3-2. WREN Timing
Figure 3-3. WRDI Timing
Figure 3-4. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
11
5228B–SEEPR–7/08
Figure 3-5. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
6
10 11 12 13 14 15
SCK
DATA IN
INSTRUCTION
SI
7
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 3-6. READ Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
BYTE ADDRESS
...
INSTRUCTION
15 14 13
3 2 1 0
DATA OUT
HIGH IMPEDANCE
SO
7 6 5 4 3 2 1 0
MSB
Figure 3-7. WRITE Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
BYTE ADDRESS
DATA IN
...
INSTRUCTION
SI
15 14 13
3 2 1 0
7 6 5 4 3 2 1 0
HIGH IMPEDANCE
SO
12
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
Figure 3-8. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
13
5228B–SEEPR–7/08
4. AT25080B Ordering Information
Ordering Code
Voltage
1.8
Package
8P3
Operation Range
AT25080B-PU (Bulk form only)
AT25080BN-SH-B(1) (NiPdAu Lead Finish)
AT25080BN-SH-T(2) (NiPdAu Lead Finish)
AT25080B-TH-B(1) (NiPdAu Lead Finish)
AT25080B-TH-T(2) (NiPdAu Lead Finish)
AT25080BY6-YH-T(2) (NiPdAu Lead Finish)
AT25080BD3-DH-T(2)
1.8
8S1
1.8
8S1
Lead-free/Halogen-free/
Industrial Temperature
1.8
8A2
1.8
8A2
(−40 to 85°C)
1.8
8Y6
1.8
8D3
AT25080BU3-UU-T(2) (NiPdAu Lead Finish)
1.8
8U3-1
Industrial Temperature
AT25080B-W-11(3)
1.8
Die Sale
(−40 to 85°C)
Notes: 1. “B” denotes bulk.
2. “-T” deontes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in waffle pack, tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon
request. Please contact Serial Interface Marketing.
Package Type
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
8-lead, 1.8 mm x 2.2 mm Body, Ultra axLanda Grid Array (ULLGA)
8-ball, die Ball Grid Array Package (dBGA2)
8P3
8S1
8A2
8Y6
8D3
8U3-1
Options
−1.8
Low Voltage (1.8 to 5.5V)
14
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
5. AT25160B Ordering Information
Ordering Code
Voltage
1.8
Package
8P3
Operation Range
AT25160B-PU (Bulk form only)
AT25160BN-SH-B(1) (NiPdAu Lead Finish)
AT25160BN-SH-T(2) (NiPdAu Lead Finish)
AT25160B-TH-B(1) (NiPdAu Lead Finish)
AT25160B-TH-T(2) (NiPdAu Lead Finish)
AT25160BY6-YH-T(2) (NiPdAu Lead Finish)
AT25160BD3-DH-T(2)
1.8
8S1
1.8
8S1
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
1.8
8A2
1.8
8A2
1.8
8Y6
1.8
8D3
AT25160BU3-UU-T(2)
1.8
8U3-1
Industrial Temperature
AT25160B-W-11(3)
1.8
Die Sale
(−40 to 85°C)
Notes: 1. “B” denotes bulk.
2. “-T” deontes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP, SOT23, and dBGA2 = 5K per reel.
3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial Interface Marketing.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3mm)
8-lead, 1.8 mm x 2.2 mm Body, Ultra axLanda Grid Array (ULLGA)
8-ball, die Ball Grid Array Package (dBGA2)
8P3
8S1
8A2
8Y6
8D3
8U3-1
Options
−1.8
Low Voltage (1.8 to 5.5V)
15
5228B–SEEPR–7/08
6. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
16
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
–
–
D
–
–
Side View
e
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
∅
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
17
5228B–SEEPR–7/08
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
18
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
8Y6 – Mini MAP
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A2
A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
b
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
C
R
19
5228B–SEEPR–7/08
8D3 - ULLGA
D
e1
b
7
5
6
8
L
E
PIN #1 ID
0.10
PIN #1 ID
A1
0.15
2
4
1
3
b
e
A
BOTTOM VIEW
SIDE VIEW
TOP VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.40
0.05
1.90
2.30
0.25
NOM
–
NOTE
A
A1
D
E
0.00
1.70
2.10
0.15
–
1.80
2.20
b
0.20
e
0.40 TYP
1.20 REF
0.30
e1
L
0.25
0.35
11/15/05
TITLE
DRAWING NO.
8D3
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe
Land Grid Array (ULLGA) D3
0
R
20
AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
AT25080B/160B [Preliminary]
7. Revision History
Lit No.
Date
Comments
5228B
5228A
7/2008
9/2007
Changed ‘Endurance’ parameter on page 6
Initial document release.
21
5228B–SEEPR–7/08
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5228B–SEEPR–7/08
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