AT25080T2-10TC-2.7 [ATMEL]
EEPROM, 1KX8, Serial, CMOS, PDSO20, 0.170 INCH, TSSOP-20;
| 型号： | AT25080T2-10TC-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 1KX8, Serial, CMOS, PDSO20, 0.170 INCH, TSSOP-20 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 ATM 异步传输模式 光电二极管 内存集成电路 |
| 文件： | 总19页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• 3.0 MHz Clock Rate (5V)
• 32-byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
SPI Serial
EEPROMs
• Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
• Self-timed Write Cycle (5 ms Typical)
• High-reliability
8K (1024 x 8)
16K (2048 x 8)
32K (4096 x 8)
64K (8192 x 8)
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-pin PDIP, 8-lead JEDEC SOIC, and 14-lead and 20-lead TSSOP Packages
Description
The AT25080/160/320/640 provides 8192/16384/32768/65536 bits of serial electri-
cally-erasable programmable read only memory (EEPROM) organized as
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25080/160/320/640 is available in space saving 8-pin PDIP, 8-
lead JEDEC SOIC, and 14-lead and 20-lead TSSOP packages.
AT25080
AT25160
AT25320
AT25640
(continued)
Pin Configuration
Pin Name
Function
8-pin PDIP
8-lead SOIC
CS
Chip Select
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
WP
WP
GND
GND
SO
GND
VCC
WP
Power Supply
Write Protect
Suspends Serial Input
No Connect
14-lead TSSOP
20-lead TSSOP*
HOLD
NC
CS
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
HOLD
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
SO
NC
CS
SO
VCC
HOLD
HOLD
NC
NC
NC
SO
NC
NC
NC
DC
Don’t Connect
WP
GND
SCK
SI
NC
NC
8
WP
GND
DC
SCK
SI
DC
NC
NC
Note:
*Pins 3, 4 and 17, 18 are internally connected
for 14-lead TSSOP socket compatibility.
Rev. 0675F–08/01
The AT25080/160/320/640 is enabled through the Chip Select pin (CS) and accessed via a 3-
wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is
required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of four
blocks of write protection. Separate program enable and program disable instructions are pro-
vided for additional data protection. Hardware data protection is provided via the WP pin to
protect against inadvertent write attempts to the status register. The HOLD pin may be used to
suspend any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
2
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance(CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics(1)
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
VCC1
VCC2
VCC3
ICC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
3.6
5.5
5.5
3.0
5.0
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
V
V
VCC = 5.0V at 1 MHz, SO = Open, Read
mA
mA
ICC2
VCC = 5.0V at 2 MHz, SO = Open,
Read, Write
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V, CS = VCC
VCC = 2.7V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
0.1
0.2
2.0
1.0
2.0
5.0
µA
µA
µA
µA
µA
V
-3.0
-3.0
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
-0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
IOL = 3.0 mA
IOH = -1.6 mA
IOL = 0.15 mA
IOH = -100 µA
V
VCC - 0.8
VCC - 0.2
V
0.2
V
V
Note:
1. VIL min and VIH max are reference only and are not tested.
3
0675F–08/01
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
3.0
2.1
0.5
MHz
tRI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
µs
µs
ns
ns
ns
ns
ns
ns
ns
tFI
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
2
2
2
tWH
tWL
tCS
tCSS
tCSH
tSU
tH
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
133
200
800
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
133
200
800
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
CS Setup Time
CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50
100
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
50
50
100
tHD
tCD
tV
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
400
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
200
200
400
ns
ns
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
133
200
800
tHO
Output Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
4
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
tLZ
Hold to Output Low Z
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
0
0
0
100
100
100
ns
tHZ
Hold to Output High Z
Output Disable Time
Write Cycle Time
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
100
100
100
ns
ns
tDIS
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
250
250
1000
tWC
4.5 - 5.5
2.7 - 5.5
1.8 - 3.6
5
10
20
ms
Endurance(1)
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
5
0675F–08/01
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080/160/320/640
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080/160/320/640 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25080/160/320/640, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25080/160/320/640 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25080/160/320/640. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low.
To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK
may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the
high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when
held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta-
tus register are inhibited. WP going low while CS is still low will interrupt a write to the status
register. If the internal write cycle has already been initiated, WP going low will have no effect
on any write operation to the status register. The WP pin function is blocked when the WPEN
bit in the status register is "0". This will allow the user to install the AT25080/160/320/640 in a
system with the WP pin tied to ground and still be able to write to the status register. All WP
pin functions are enabled when the WPEN bit is set to “1”.
6
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
SPI Serial Interface
7
0675F–08/01
Functional
Description
The AT25080/160/320/640 is designed to interface directly with the synchronous serial periph-
eral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25080/160/320/640 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 1. All instructions, addresses, and data are transferred
with the MSB first and start with a high-to-low CS transition.
Table 1. Instruction Set for the AT25080/160/320/640
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 X011
WRITE
0000 X010
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the sta-
tus of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be deter-
mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction.
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
Table 3. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is
in progress.
Bit 1 (WEN)
Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the
device is WRITE ENABLED.
Bit 2 (BP0)
Bit 3 (BP1)
See Table 3.
See Table 3.
Bits 4 - 6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 7.
Bits 0 - 7 are 1s during an internal write cycle.
8
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080/160/320/640 is divided into four array segments. One
quarter (1/4), one half (1/2), or all of the memory segments can be protected. Any of the data
within any selected segment will therefore be READ only. The block write protection levels and
corresponding status register control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status
Register Bits
Array Addresses Protected
Level
0
BP1
BP0
AT25080
AT25160
AT25320
AT25640
0
0
None
None
None
None
1(1/4)
0300
-03FF
0600
-07FF
0C00
-0FFF
1800
-1FFF
0
1
1
1
0
1
2(1/2)
3(All)
0200
-03FF
0400
-07FF
0800
-0FFF
1000
-1FFF
0000
-03FF
0000
-07FF
0000
-0FFF
0000
-1FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-
protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
Table 5. WPEN Operation
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
X
WEN
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
9
0675F–08/01
READ SEQUENCE (READ): Reading the AT25080/160/320/640 via the SO (Serial Output)
pin requires the following sequence. After the CS line is pulled low to select a device, the
READ op-code is transmitted via the SI line followed by the byte address to be read (A15 - A0,
Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0)
at the specified address is then shifted out onto the SO line. If only one byte is to be read, the
CS line should be driven high after the data comes out. The READ sequence can be contin-
ued since the byte address is automatically incremented and data will continue to be shifted
out. When the highest address is reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080/160/320/640, two separate
instructions must be executed. First, the device must be write enabled via the Write Enable
(WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of
the memory location(s) to be programmed must be outside the protected address field location
selected by the Block Write Protection Level. During an internal write cycle, all commands will
be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address
(A15 - A0) and the data (D7 - D0) to be programmed (Refer to Table 6). Programming will start
after the CS pin is brought high. (The LOW-to-High transition of the CS pin must occur during
the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STATUS
REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the
WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during
the WRITE programming cycle.
The AT25080/160/320/640 is capable of a 32-byte PAGE WRITE operation. After each byte of
data is received, the five low order address bits are internally incremented by one; the high
order bits of the address will remain constant. If more than 32 bytes of data are transmitted,
the address counter will roll over and the previously written data will be overwritten. The
AT25080/160/320/640 is automatically returned to the write disable state at the completion of
a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction
and will return to the standby state, when CS is brought high. A new CS falling edge is
required to re-initiate the serial communication.
Table 6. Address Key
Address
AT25080
AT25160
AT25320
AT25640
AN
A9 - A0
A10 - A0
A11 - A0
A12 - A0
Don’t
Care Bits
A15 - A10
A15 - A11
A15 - A12
A15 - A13
10
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
Timing Diagrams
Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
VIH
tH
SI
VALID IN
VIL
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
WREN Timing
WRDI Timing
11
0675F–08/01
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
DATA IN
INSTRUCTION
SI
5
4
3
2
1
0
HIGH IMPEDANCE
SO
READ Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30
SCK
BYTE ADDRESS
...
3 2 1 0
SI
INSTRUCTION
15 14 13
DATA OUT
HIGH IMPEDANCE
SO
7 6 5 4 3 2 1 0
MSB
12
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
WRITE Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
BYTE ADDRESS
...
DATA IN
INSTRUCTION
SI
15 14 13
3 2 1 0
7 6 5 4 3 2 1 0
HIGH IMPEDANCE
SO
HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
13
0675F–08/01
AT25080 Ordering Information
tWC (max)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(ms)
(kHz)
Ordering Code
Package
Operation Range
5
5000
3000
3000
5000
3000
3000
2.0
0.5
0.2
2.0
0.5
0.2
3000
2100
500
AT25080-10PC
8P3
8S1
14T
20T
Commercial
AT25080N-10SC
AT25080T1-10TC
AT25080T2-10TC
(0°C to 70°C)
10
20
5
AT25080-10PC-2.7
AT25080N-10SC-2.7
AT25080T1-10TC-2.7
AT25080T2-10TC-2.7
8P3
8S1
14T
20T
Commercial
(0°C to 70°C)
AT25080-10PC1.8
8P3
8S1
14T
20T
Commercial
AT25080N-10SC-1.8
AT25080T1-10TC-1.8
AT25080T2-10TC-1.8
(0°C to 70°C)
3000
2100
500
AT25080-10PI
8P3
8S1
14T
20T
Industrial
AT25080N-10SI
AT25080T1-10TI
AT25080T2-10TI
(-40°C to 85°C)
10
20
AT25080-10PI-2.7
AT25080N-10SI-2.7
AT25080T1-10TI-2.7
AT25080T2-10TI-2.7
8P3
8S1
14T
20T
Industrial
(-40°C to 85°C)
AT25080-10PI-1.8
AT25080N-10SI-1.8
AT25080T1-10TI-1.8
AT25080T2-10TI-1.8
8P3
8S1
14T
20T
Industrial
(-40°C to 85°C)
Package Type
8P3
8S1
14T
20T
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 3.6V)
14
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
AT25160 Ordering Information
tWC (max)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(ms)
(kHz)
Ordering Code
Package
Operation Range
5
5000
3000
3000
5000
3000
3000
2.0
0.5
0.2
2.0
0.5
0.2
3000
2100
500
AT25160-10PC
8P3
8S1
14T
20T
Commercial
AT25160N-10SC
AT25160T1-10TC
AT25160T2-10TC
(0°C to 70°C)
10
20
5
AT25160-10PC-2.7
AT25160N-10SC-2.7
AT25160T1-10TC-2.7
AT25160T2-10TC-2.7
8P3
8S1
14T
20T
Commercial
(0°C to 70°C)
AT25160-10PC-1.8
AT25160N-10SC-1.8
AT25160T1-10TC-1.8
AT25160T2-10TC-1.8
8P3
8S1
14T
20T
Commercial
(0°C to 70°C)
3000
2100
500
AT25160-10PI
8P3
8S1
14T
20T
Industrial
AT25160N-10SI
AT25160T1-10TI
AT25160T2-10TI
(-40°C to 85°C)
10
20
AT25160-10PI-2.7
AT25160N-10SI-2.7
AT25160T1-10TI-2.7
AT25160T2-10TI-2.7
8P3
8S1
14T
20T
Industrial
(-40°C to 85°C)
AT25160-10PI-1.8
8P3
8S1
14T
20T
Industrial
AT25160N-10SI-1.8
AT25160T1-10TI-1.8
AT225160T2-10TI-1.8
(-40°C to 85°C)
Package Type
8P3
8S1
14T
20T
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 3.6V)
15
0675F–08/01
AT25320 Ordering Information
tWC (max)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
(ms)
Ordering Code
AT25320-10PC
Package
Operation Range
5
10
5
5000
3000
5000
3000
2.0
0.5
2.0
0.5
3000
2100
3000
2100
8P3
8S1
14T
20T
Commercial
AT25320N-10SC
AT25320T1-10TC
AT25320T2-10TC
(0°C to 70°C)
AT25320-10PC-2.7
AT25320N-10SC-2.7
AT25320T1-10TC-2.7
AT25320T2-10TC-2.7
8P3
8S1
14T
20T
Commercial
(0°C to 70°C)
AT25320-10PI
8P3
8S1
14T
20T
Industrial
AT25320N-10SI
AT25320T1-10TI
AT25320T2-10TI
(-40°C to 85°C)
10
AT25320-10PI-2.7
AT25320N-10SI-2.7
AT25320T1-10TI-2.7
AT25320T2-10TI-2.7
8P3
8S
Industrial
(-40°C to 85°C)
14T
20T
Package Type
8P3
8S1
14T
20T
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
16
AT25080/160/320/640
0675F–08/01
AT25080/160/320/640
AT25640 Ordering Information
tWC (max)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(ms)
(kHz)
Ordering Code
Package
Operation Range
5
5000
3000
3000
5000
3000
3000
2.0
0.5
0.2
2.0
0.5
0.2
3000
2100
500
AT25640-10PC
8P3
8S1
14T
20T
Commercial
AT25640N-10SC
AT25640T1-10TC
AT25640T2-10TC
(0°C to 70°C)
10
20
5
AT25640-10PC-2.7
AT25640N-10SC-2.7
AT25640T1-10TC-2.7
AT25640T2-10TC-2.7
8P3
8S1
14T
20T
Commercial
(0°C to 70°C)
AT25640-10PC-1.8
AT25640N-10SC-1.8
AT25640T1-10TC-1.8
AT25640T2-10TC-1.8
8P3
8S1
14T
20T
Commercial
(0°C to 70°C)
3000
2100
500
AT25640-10PI
8P3
8S1
14T
20T
Industrial
AT25640N-10SI
AT25640T1-10TI
AT25640T2-10TI
(-40°C to 85°C)
10
20
AT25640-10PI-2.7
AT25640N-10SI-2.7
AT25640T1-10TI-2.7
AT25640T2-10TI-2.7
8P3
8S1
14T
20T
Industrial
(-40°C to 85°C)
AT25640-10PI-1.8
AT25640N-10SI-1.8
AT25640T1-10TI-1.8
AT25640T2-10TI-1.8
8P3
8S1
14T
20T
Industrial
(-40°C to 85°C)
Package Type
8P3
8S1
14T
20T
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank
-2.7
Standard Device (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 3.6V)
17
0675F–08/01
Packaging Information
P3, 8-pin, 0.300" Wide,
8S1, 8-lead, 0.150" Wide,
Plastic Gull Wing Small Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
.400 (10.16)
.355 (9.02)
.020 (.508)
.013 (.330)
PIN
1
.244 (6.20)
.228 (5.79)
.157 (3.99)
.150 (3.81)
.280 (7.11)
.240 (6.10)
PIN 1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.050 (1.27) BSC
.100 (2.54) BSC
.196 (4.98)
.189 (4.80)
SEATING
PLANE
.068 (1.73)
.015 (.380) MIN
.053 (1.35)
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.010 (.254)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
8
REF
.010 (.254)
.007 (.203)
0
REF
15
.012 (.305)
.008 (.203)
.050 (1.27)
.016 (.406)
.430 (10.9) MAX
14T, 14-lead, 0.170" Wide,
Thin Shrink Small Outline Package (TSSOP)
20T, 20-lead, 0.170" Wide,
Thin Shrink Small Outline Package (TSSOP)
Dimensions in (Inches) and Millimeters*
Dimensions in (Inches) and Millimeters*
INDEX MARK
INDEX MARK
PIN
1
PIN
1
6.50 (.256)
6.25 (.246)
6.50 (.256)
6.25 (.246)
4.50 (.177)
4.30 (.169)
4.50 (.177)
4.30 (.169)
5.10 (.201)
4.90 (.193)
1.20 (.047) MAX
6.60 (.260)
6.40 (.252)
1.20 (.047) MAX
.650 (.026) BSC
0.30 (.012)
0.15 (.006)
0.05 (.002)
SEATING
PLANE
.650 (.026) BSC
0.15 (.006)
0.05 (.002)
SEATING
PLANE
0.30 (.012)
0.19 (.007)
0.19 (.007)
0.20 (.008)
0.09 (.004)
0
8
REF
0.20 (.008)
0.09 (.004)
0
8
REF
0.75 (.030)
0.45 (.018)
0.75 (.030)
0.45 (.018)
*Controlling dimension: millimeters
*Controlling dimension: millimeters
18
AT25080/160/320/640
0675F–08/01
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Atmel Product Operations
Corporate Headquarters
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Japan
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® is the registered trademark of Atmel.
Other terms and product names may be the trademark of others.
Printed on recycled paper.
0675F–08/01/xM
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