AT25320A-W1.8-11 [ATMEL]
EEPROM, 4KX8, Serial, CMOS, DIE;
| 型号： | AT25320A-W1.8-11 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 4KX8, Serial, CMOS, DIE 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总26页 (文件大小：801K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• 20 MHz Clock Rate (5V)
• 32-byte Page Mode
SPI Serial
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
EEPROMs
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
8K (1024 x 8)
16K (2048 x 8)
32K (4096 x 8)
64K (8192 x 8)
• Self-timed Write Cycle (5 ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Available in Automotive
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead MAP, 8-lead Ultra Thin
Mini-MAP (MLP 2x3) and 8-lead TSSOP Packages
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
AT25080A
AT25160A
AT25320A
AT25640A
Description
The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial
electrically-erasable programmable read-only memory (EEPROM) organized as
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25080A/160A/320A/640A is available in space-saving 8-lead
PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-
lead TSSOP and 8-Lead Ultra Leadframe Land Grid Array (ULLGA) packages.
The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and
accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely self-
timed, and no separate erase cycle is required before write.
3347M–SEEPR–06/07
Table 0-1.
Pin Name
CS
Pin Configuration
Function
8-lead SOIC
8-lead PDIP
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Chip Select
WP
WP
GND
GND
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
8-lead Ultra Thin Mini-MAP (MLP 2x
8-lead TSSOP
VCC 8
HOLD 7
SCK 6
SI 5
1
2
3
4
CS
SO
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
SO
WP
GND
GND
VCC
WP
WP
GND
Power Supply
Write Protect
Bottom View
8-lead MAP
8-lead ULLGA
VCC
8
7
6
5
1
2
3
4
CS
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
HOLD
NC
Suspends Serial Input
No Connect
HOLD
SCK
SI
SO
SO
WP
GND
WP
GND
DC
Don’t Connect
Bottom View
Bottom View
Block write protection is enabled by programming the status register with one of four blocks of
write protection. Separate program enable and program disable instructions are provided for
additional data protection. Hardware data protection is provided via the WP pin to protect
against inadvertent write attempts to the status register. The HOLD pin may be used to suspend
any serial communication without resetting the serial sequence.
1. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature..................................–55°C to +125°C
Storage Temperature.....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
2
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
Figure 1-1. Block Diagram
Table 1-1.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Pin Capacitance(1)
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
3
3347L–SEEPR–06/07
Table 1-2.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
VCC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
VCC2
5.5
V
VCC3
5.5
V
ICC1
VCC = 5.0V at 20 MHz, SO = Open, Read
7.5
4.0
10.0
mA
VCC = 5.0V at 20 MHz, SO = Open, Read,
ICC2
ICC3
Supply Current
Supply Current
10.0
mA
mA
Write
VCC = 5.0V at 5 MHz, SO = Open,
Read, Write
4.0
6.0
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V, CS = VCC
VCC = 2.7V, CS = VCC
VCC = 5.0V, CS = VCC
VIN = 0V to VCC
< 0.1
0.3
6.0(2)
7.0(2)
µA
µA
µA
µA
µA
V
2.0
10.0(2)
–3.0
–3.0
3.0
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
–0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
I
OL = 3.0 mA
V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
IOH = −1.6 mA
VCC - 0.8
VCC - 0.2
V
IOL = 0.15 mA
0.2
V
IOH = −100 µA
V
Notes: 1. VIL min and VIH max are reference only and are not tested.
2. Worst case measured at 85°C
4
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
20
10
5
fSCK
SCK Clock Frequency
MHz
4.5–5.5
2.7–5.5
1.8–5.5
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
µs
µs
ns
4.5–5.5
2.7–5.5
1.8–5.5
2
2
2
tFI
20
40
4.5–5.5
2.7–5.5
1.8–5.5
tWH
80
20
40
4.5–5.5
2.7–5.5
1.8–5.5
tWL
tCS
tCSS
tCSH
tSU
tH
SCK Low Time
CS High Time
ns
ns
ns
ns
ns
ns
80
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
CS Setup Time
CS Hold Time
4.5–5.5
2.7–5.5
1.8–5.5
25
50
100
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
Data In Setup Time
Data In Hold Time
HOLD Setup Time
HOLD Hold Time
Output Valid
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
tHD
tCD
tV
4.5–5.5
2.7–5.5
1.8–5.5
5
10
20
ns
ns
ns
20
40
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
80
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
tHO
Output Hold Time
5
3347L–SEEPR–06/07
Table 1-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
4.5–5.5
2.7–5.5
1.8–5.5
0
0
0
25
50
100
tLZ
HOLD to Output Low Z
ns
4.5–5.5
2.7–5.5
1.8–5.5
40
80
200
tHZ
HOLD to Output High Z
Output Disable Time
ns
ns
4.5–5.5
2.7–5.5
1.8–5.5
40
80
200
tDIS
4.5–5.5
2.7–5.5
1.8–5.5
5
5
5
tWC
Write Cycle Time
ms
Endurance(1)
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
6
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
2. Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080A/160A/320A/640A
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated
for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance
state until the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may
still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high
impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held
high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status reg-
ister are inhibited. WP going low while CS is still low will interrupt a write to the status register. If
the internal write cycle has already been initiated, WP going low will have no effect on any write
operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is “0”. This will allow the user to install the AT25080A/160A/320A/640A in a system with
the WP pin tied to ground and still be able to write to the status register. All WP pin functions are
enabled when the WPEN bit is set to “1”.
7
3347L–SEEPR–06/07
Figure 2-1. SPI Serial Interface
AT25080A/160A/320A/640A
8
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
3. Functional Description
The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 3-1. All instructions, addresses, and data are trans-
ferred with the MSB first and start with a high-to-low CS transition.
Table 3-1.
Instruction Set for the AT25080A/160A/320A/640A
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 X011
WRITE
0000 X010
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protec-
tion employed. These bits are set by using the WRSR instruction.
Table 3-2.
Bit 7
Status Register Format
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
9
3347L–SEEPR–06/07
Table 3-3.
Bit
Read Status Register Bit Definition
Definition
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write
cycle is in progress.
Bit 0 (RDY)
Bit 1 (WEN)
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
Bit 2 (BP0)
Bit 3 (BP1)
See Table 3-4 on page 10.
See Table 3-4 on page 10.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 3-5 on page 11.
Bits 0–7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080A/160A/320A/640A is divided into four array segments.
One-quarter, one-half, or all of the memory segments can be protected. Any of the data within
any selected segment will therefore be read only. The block write protection levels and corre-
sponding status register control bits are shown in Table 3-4.
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 3-4.
Block Write Protect Bits
Status
Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25080A
AT25160A
AT25320A
AT25640A
0
0
0
None
None
None
None
0300
−03FF
0600
−07FF
0C00
−0FFF
1800
−1FFF
1(1/4)
2(1/2)
3(All)
0
1
1
1
0
1
0200
−03FF
0400
−07FF
0800
−0FFF
1000
−1FFF
0000
−03FF
0000
−07FF
0000
−0FFF
0000
−1FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the status register, including the block protect bits and the WPEN bit, and the block-pro-
tected sections in the memory array are disabled. Writes are only allowed to sections of the
memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as
long as the WP pin is held low.
10
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
Table 3-5.
WPEN Operation
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
X
WEN
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writeable
Protected
Writeable
Protected
Writeable
Protected
Writeable
Protected
Protected
Protected
Writeable
X
Low
Low
High
High
READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the Serial Output
(SO) pin requires the following sequence. After the CS line is pulled low to select a device, the
read op-code is transmitted via the SI line followed by the byte address to be read (A15–A0, see
Table 3-6). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line
should be driven high after the data comes out. The read sequence can be continued since the
byte address is automatically incremented and data will continue to be shifted out. When the
highest address is reached, the address counter will roll over to the lowest address allowing the
entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080A/160A/320A/640A, two sepa-
rate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a write (WRITE) instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location selected by
the block write protection level. During an internal write cycle, all commands will be ignored
except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15–A0)
and the data (D7–D0) to be programmed (see Table 3-6). Programming will start after the CS pin
is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time
immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle
has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25080A/160A/320A/640A is capable of a 32-byte page write operation. After each byte of
data is received, the five low-order address bits are internally incremented by one; the high-
order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the
address counter will roll over and the previously written data will be overwritten. The
AT25080A/160A/320A/640A is automatically returned to the write disable state at the comple-
tion of a write cycle.
NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to
reinitiate the serial communication.
11
3347L–SEEPR–06/07
Table 3-6.
Address
Address Key
AT25080A
AT25160A
A10–A0
AT25320A
A11–A0
AT25640A
A12–A0
AN
A9–A0
Don’t Care Bits
A15–A10
A15–A11
A15–A12
A15–A13
4. Timing Diagrams
Figure 4-1. Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSH
tCSS
VIH
tWH
tWL
SCK
VIL
tSU
tH
VIH
VIL
SI
VALID IN
tHO
tDIS
tV
VOH
VOL
HI-Z
HI-Z
SO
Figure 4-2. WREN Timing
12
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
Figure 4-3. WRDI Timing
Figure 4-4. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
Figure 4-5. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
7
9
10 11 12 13 14 15
SCK
DATA IN
INSTRUCTION
SI
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
13
3347L–SEEPR–06/07
Figure 4-6. READ Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
BYTE ADDRESS
...
INSTRUCTION
15 14 13
3 2 1 0
DATA OUT
HIGH IMPEDANCE
SO
7 6 5 4 3 2 1 0
MSB
Figure 4-7. WRITE Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
BYTE ADDRESS
...
DATA IN
INSTRUCTION
SI
15 14 13
3 2 1 0
7 6 5 4 3 2 1 0
HIGH IMPEDANCE
SO
Figure 4-8. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
14
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
5. AT25080A Ordering Information(1)
Ordering Code
Package
Operation Range
AT25080A-10PU-2.7(2)
AT25080A-10PU-1.8(2)
AT25080AN-10SU-2.7(2)
AT25080AN-10SU-1.8(2)
AT25080A-10TU-2.7(2)
AT25080A-10TU-1.8(2)
AT25080AY1-10YU-1.8(2) (Not recommended for new design)
AT25080AY6-10YH-1.8(3)
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
Industrial Temperature
AT25080A-W1.8-11(4)
Die Sale
(−40 to 85°C)
Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8S1
8A2
8Y1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP
2x3mm)
8Y6
Options
Low Voltage (2.7 to 5.5V)
−2.7
−1.8
Low Voltage (1.8 to 5.5V)
15
3347L–SEEPR–06/07
6. AT25160A Ordering Information(1)
Ordering Code
Package
Operation Range
AT25160A-10PU-2.7(2)
AT25160A-10PU-1.8(2)
AT25160AN-10SU-2.7(2)
AT25160AN-10SU-1.8(2)
AT25160A-10TU-2.7(2)
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
8D3
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
AT25160A-10TU-1.8(2)
AT25160AY1-10YU-1.8(2) (Not recommended for new design)
AT25160AY6-10YH-1.8(3)
AT25160AD3-10DH-1.8
Industrial Temperature
AT25160A-W1.8-11(4)
Die Sale
(−40 to 85°C)
Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8S1
8A2
8Y1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP
2x3mm)
8Y6
8D3
8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULLGA) D3
Options
Low Voltage (2.7 to 5.5V)
−2.7
−1.8
Low Voltage (1.8 to 5.5V)
16
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
7. AT25320A Ordering Information(1)
Ordering Code
Package
Operation Range
AT25320A-10PU-2.7(2)
AT25320A-10PU-1.8(2)
8P3
8P3
AT25320AN-10SU-2.7(2)
8S1
8S1
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
AT25320AN-10SU-1.8(2)
AT25320A-10TU-2.7(2)
AT25320A-10TU-1.8(2)
AT25320AY1-10YU-1.8(2) (Not recommended for new design)
AT25320AY6-10YH-1.8(3)
8A2
8A2
8Y1
8Y6
Industrial Temperature
AT25320A-W1.8-11(4)
Die Sale
(−40 to 85°C)
Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8S1
8A2
8Y1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP
2x3mm)
8Y6
Options
Low Voltage (2.7 to 5.5V)
−2.7
−1.8
Low Voltage (1.8 to 5.5V)
17
3347L–SEEPR–06/07
8. AT25640A Ordering Information(1)
Ordering Code
Package
Operation Range
AT25640A-10PU-2.7(2)
AT25640A-10PU-1.8(2)
AT25640AN-10SU-2.7(2)
AT25640AN-10SU-1.8(2)
AT25640A-10TU-2.7(2)
AT25640A-10TU-1.8(2)
AT25640AY1-10YU-1.8(2)(Not recommended for new design)
AT25640AY6-10YH-1.8(3)
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
Lead-free/Halogen-free/
Industrial Temperature
(−40 to 85°C)
Industrial Temperature
AT25640A-W1.8-11(3)
Die Sale
(−40 to 85°C)
Notes: 1. For 2.7V devices used in the 4.5 to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8S1
8A2
8Y1
8Y6
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm)
Options
−2.7
−1.8
Low Voltage (2.7 to 5.5V)
Low Voltage (1.8 to 5.5V)
18
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
9. Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
19
3347L–SEEPR–06/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
Side View
1.27 BSC
L
0.40
0˚
–
–
1.27
8˚
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
20
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
21
3347L–SEEPR–06/07
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
4
2
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
7
b
e
A1
E
Bottom View
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
MIN
–
MAX
0.90
0.05
5.10
3.20
1.15
1.15
0.35
NOM
–
NOTE
A
A1
D
0.00
4.70
2.80
0.85
0.85
0.25
–
4.90
3.00
1.00
1.00
0.30
0.65 TYP
0.60
Side View
E
D1
E1
b
e
L
0.50
0.70
2/28/03
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
8Y1
C
R
22
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
8Y6 – Mini MAP
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A2
A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
b
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
C
R
23
3347L–SEEPR–06/07
8D3 - ULLGA
D
e1
b
7
5
6
8
L
E
PIN #1 ID
0.10
PIN #1 ID
A1
0.15
2
4
1
3
b
e
A
BOTTOM VIEW
SIDE VIEW
TOP VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.40
0.05
1.90
2.30
0.25
NOM
–
NOTE
A
A1
D
E
0.00
1.70
2.10
0.15
–
1.80
2.20
b
0.20
e
0.40 TYP
1.20 REF
0.30
e1
L
0.25
0.35
11/15/05
TITLE
DRAWING NO.
8D3
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe
Land Grid Array (ULLGA) D3
0
R
24
AT25080A/160A/320A/640A
3347L–SEEPR–06/07
AT25080A/160A/320A/640A
10. Revision History
Doc. Rev.
Date
Comments
Added 8D3-ULLGA to document
3347M
3347L
3347K
6/2007
Changed Feature descriptions on page 1
Added AT25640AY6-10YU-1.8 ordering code.
4/2007
2/2007
Added ‘Not recommended for new design’ note to AT25640AY1-
10YU-1.8 ordering code.
Implemented revision history.
Added ‘Ultra Thin’ description to 8-lead Mini Map package.
25
3347L–SEEPR–06/07
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Japan
Tel: (81) 3-3523-3551
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Fax: (33) 1-30-60-71-11
Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
s_eeprom@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
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3347L–SEEPR–06/07
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