AT26DF321_技术文档

Features

• Single 2.7V - 3.6V Supply

• Serial Peripheral Interface (SPI) Compatible

– Supports SPI Modes 0 and 3

• 66 MHz Maximum Clock Frequency

• Flexible, Uniform Erase Architecture

– 4-Kbyte Blocks

– 32-Kbyte Blocks

– 64-Kbyte Blocks

32-megabit

2.7-volt Only

Serial Firmware

DataFlash^®

Memory

– Full Chip Erase

• Individual Sector Protection with Global Protect/Unprotect Feature

– Sixty-Four 64-Kbyte Physical Sectors

• Hardware Controlled Locking of Protected Sectors

• Flexible Programming

– Byte/Page Program (1 to 256 Bytes)

• JEDEC Standard Manufacturer and Device ID Read Methodology

• Low Power Dissipation

– 7 mA Active Read Current (Typical)

– 4 µA Deep Power-Down Current (Typical)

• Endurance: 100,000 Program/Erase Cycles

• Data Retention: 20 Years

• Complies with Full Industrial Temperature Range

• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (200-mil wide)

AT26DF321

Preliminary

– 16-lead SOIC (300-mil wide)

1. Description

The AT26DF321 is a serial interface Flash memory device designed for use in a wide

variety of high-volume consumer based applications in which program code is shad-

owed from Flash memory into embedded or external RAM for execution. The flexible

erase architecture of the AT26DF321, with its erase granularity as small as 4-Kbytes,

makes it ideal for data storage as well, eliminating the need for additional data storage

EEPROM devices.

The physical sectoring and the erase block sizes of the AT26DF321 have been opti-

mized to meet the needs of today's code and data storage applications. By optimizing

the size of the physical sectors and erase blocks, the memory space can be used

much more efficiently. Because certain code modules and data storage segments

must reside by themselves in their own protected sectors, the wasted and unused

memory space that occurs with large sectored and large block erase Flash memory

devices can be greatly reduced. This increased memory space efficiency allows addi-

tional code routines and data storage segments to be added while still maintaining the

same overall device density.

See applicable errata in

Section 17.

3633C–DFLASH–08/06

The AT26DF321 also offers a sophisticated method for protecting individual sectors against

erroneous or malicious program and erase operations. By providing the ability to individually pro-

tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while

keeping the remaining sectors of the memory array securely protected. This is useful in applica-

tions where program code is patched or updated on a subroutine or module basis, or in

applications where data storage segments need to be modified without running the risk of errant

modifications to the program code segments. In addition to individual sector protection capabili-

ties, the AT26DF321 incorporates Global Protect and Global Unprotect features that allow the

entire memory array to be either protected or unprotected all at once. This reduces overhead

during the manufacturing process since sectors do not have to be unprotected one-by-one prior

to initial programming.

Specifically designed for use in 3-volt systems, the AT26DF321 supports read, program, and

erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for

programming and erasing.

2. Pin Descriptions and Pinouts

Table 2-1.

Pin Descriptions

Asserted

State

Symbol Name and Function

Type

CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),

and the SO pin will be in a high-impedance state. When the device is deselected, data will not be

accepted on the SI pin.

CS

Low

Input

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition

is required to end an operation. When ending an internally self-timed operation such as a program

or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always

latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the

falling edge of SCK.

SCK

Input

SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK.

SI

Input

SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK.

SO

Output

WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to

“Protection Commands and Features” on page 11 for more details on protection features and the

WP pin.

WP

Low

Input

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will

not be used. However, it is recommended that the WP pin also be externally connected to V_CC

whenever possible.

DEVICE POWER SUPPLY: The V_CCpin is used to supply the source voltage to the device.

V_CC

Power

Operations at invalid V_CCvoltages may produce spurious results and should not be attempted.

GROUND: The ground reference for the power supply. GND should be connected to the system

ground.

GND

2

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

Figure 2-1. 8-SOIC Top View

Figure 2-2. 16-SOIC Top View

CS

SO

1

2

3

4

8

7

6

5

VCC

NC

VCC

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SCK

SI

WP

SCK

SI

NC

GND

WP

GND

NC

CS

SO

3. Block Diagram

CONTROL AND

PROTECTION LOGIC

I/O BUFFERS

AND LATCHES

CS

SRAM

DATA BUFFER

SCK

SI

INTERFACE

CONTROL

AND

Y-DECODER

Y-GATING

LOGIC

SO

FLASH

MEMORY

ARRAY

WP

X-DECODER

4. Memory Array

To provide the greatest flexibility, the memory array of the AT26DF321 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated

regions. Figure 4-1 on page 4 illustrates the breakdown of each erase level as well as the break-

down of each physical sector.

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3633C–DFLASH–08/06

Figure 4-1. Memory Architecture Diagram

Block Erase Detail

Page Program Detail

Internal Sectoring for

Sector Protection

Function

64KB

Block Erase

32KB

Block Erase

4KB

Block Erase

1-256 Byte

Page Program

(02h Command)

Block Address

Range

Page Address

Range

(D8h Command) (52h Command) (20h Command)

3FFFFFh – 3FF000h

3FEFFFh – 3FE000h

3FDFFFh – 3FD000h

3FCFFFh – 3FC000h

3FBFFFh – 3FB000h

3FAFFFh – 3FA000h

3F9FFFh – 3F9000h

3F8FFFh – 3F8000h

3F7FFFh – 3F7000h

3F6FFFh – 3F6000h

3F5FFFh – 3F5000h

3F4FFFh – 3F4000h

3F3FFFh – 3F3000h

3F2FFFh – 3F2000h

3F1FFFh – 3F1000h

3F0FFFh – 3F0000h

3EFFFFh – 3EF000h

3EEFFFh – 3EE000h

3EDFFFh – 3ED000h

3ECFFFh – 3EC000h

3EBFFFh – 3EB000h

3EAFFFh – 3EA000h

3E9FFFh – 3E9000h

3E8FFFh – 3E8000h

3E7FFFh – 3E7000h

3E6FFFh – 3E6000h

3E5FFFh – 3E5000h

3E4FFFh – 3E4000h

3E3FFFh – 3E3000h

3E2FFFh – 3E2000h

3E1FFFh – 3E1000h

3E0FFFh – 3E0000h

256 Bytes

3FFFFFh – 3FFF00h

3FFEFFh – 3FFE00h

3FFDFFh – 3FFD00h

3FFCFFh – 3FFC00h

3FFBFFh – 3FFB00h

3FFAFFh – 3FFA00h

3FF9FFh – 3FF900h

3FF8FFh – 3FF800h

3FF7FFh – 3FF700h

3FF6FFh – 3FF600h

3FF5FFh – 3FF500h

3FF4FFh – 3FF400h

3FF3FFh – 3FF300h

3FF2FFh – 3FF200h

3FF1FFh – 3FF100h

3FF0FFh – 3FF000h

3FEFFFh – 3FEF00h

3FEEFFh – 3FEE00h

3FEDFFh – 3FED00h

3FECFFh – 3FEC00h

3FEBFFh – 3FEB00h

3FEAFFh – 3FEA00h

3FE9FFh – 3FE900h

3FE8FFh – 3FE800h

4KB

32KB

4KB

64KB

(Sector 63)

64KB

4KB

32KB

4KB

32KB

4KB

64KB

(Sector 62)

64KB

256 Bytes

0017FFh – 001700h

0016FFh – 001600h

0015FFh – 001500h

0014FFh – 001400h

0013FFh – 001300h

0012FFh – 001200h

0011FFh – 001100h

0010FFh – 001000h

000FFFh – 000F00h

000EFFh – 000E00h

000DFFh – 000D00h

000CFFh – 000C00h

000BFFh – 000B00h

000AFFh – 000A00h

0009FFh – 000900h

0008FFh – 000800h

0007FFh – 000700h

0006FFh – 000600h

0005FFh – 000500h

0004FFh – 000400h

0003FFh – 000300h

0002FFh – 000200h

0001FFh – 000100h

0000FFh – 000000h

4KB

32KB

4KB

00FFFFh – 00F000h

00EFFFh – 00E000h

00DFFFh – 00D000h

00CFFFh – 00C000h

00BFFFh – 00B000h

00AFFFh – 00A000h

009FFFh – 009000h

008FFFh – 008000h

007FFFh – 007000h

006FFFh – 006000h

005FFFh – 005000h

004FFFh – 004000h

003FFFh – 003000h

002FFFh – 002000h

001FFFh – 001000h

000FFFh – 000000h

4KB

32KB

4KB

64KB

(Sector 0)

64KB

4KB

32KB

4KB

4

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

5. Device Operation

The AT26DF321 is controlled by a set of instructions that are sent from a host controller, com-

monly referred to as the SPI Master. The SPI Master communicates with the AT26DF321 via the

SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial

Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode

differing in respect to the SCK polarity and phase and how the polarity and phase control the

flow of data on the SPI bus. The AT26DF321 supports the two most common modes, SPI

Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal

when in the inactive state (when the SPI Master is in standby mode and not transferring any

data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always

output on the falling edge of SCK.

Figure 5-1. SPI Mode 0 and 3

CS

SCK

MSB

LSB

SI

MSB

LSB

SO

6. Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS

pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.

Following the opcode, instruction dependent information such as address and data bytes would

then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with

the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT26DF321 will be ignored by the device and no operation will be

started. The device will continue to ignore any data presented on the SI pin until the start of the

next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deas-

serted before complete opcode and address information is sent to the device, then no operation

will be performed and the device will simply return to the idle state and wait for the next

operation.

Addressing of the device requires a total of three bytes of information to be sent, representing

address bits A23-A0. Since the upper address limit of the AT26DF321 memory array is

3FFFFFh, address bits A23-A22 are always ignored by the device.

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3633C–DFLASH–08/06

Table 6-1.

Command

Command Listing

Opcode

Address Bytes

Dummy Bytes

Data Bytes

Read Commands

Read Array

0Bh

03h

0000 1011

3

1

0

1+

Read Array (Low Frequency)

Program and Erase Commands

Block Erase (4-KBytes)

Block Erase (32-KBytes)

Block Erase (64-KBytes)

0000 0011

20h

52h

D8h

60h

C7h

02h

0010 0000

0101 0010

1101 1000

0110 0000

1100 0111

0000 0010

3

0

3

0

Chip Erase

0

Byte/Page Program (1 to 256 Bytes)

Protection Commands

Write Enable

1+

06h

04h

36h

39h

0000 0110

0000 0100

0011 0110

0011 1001

0

3

0

Write Disable

Protect Sector

Unprotect Sector

Global Protect/Unprotect

Read Sector Protection Registers

Status Register Commands

Read Status Register

Use Write Status Register command

3Ch

0011 1100

3

0

1+

05h

01h

0000 0101

0000 0001

0

1+

1

Write Status Register

Miscellaneous Commands

Read Manufacturer and Device ID

Deep Power-Down

9Fh

B9h

ABh

1001 1111

1011 1001

1010 1011

0

1 to 4

0

Resume from Deep Power-Down

6

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

7. Read Commands

7.1

Read Array

The Read Array command can be used to sequentially read a continuous stream of data from

the device by simply providing the SCK signal once the initial starting address has been speci-

fied. The device incorporates an internal address counter that automatically increments on every

clock cycle.

Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode

depends on the maximum SCK frequency that will be used to read data from the device. The

0Bh opcode can be used at any SCK frequency up to the maximum specified by f_SCK. The 03h

opcode can be used for lower frequency read operations up to the maximum specified by f_RDLF

.

To perform the Read Array operation, the CS pin must first be asserted and the appropriate

opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the

three address bytes must be clocked in to specify the starting address location of the first byte to

read within the memory array. If the 0Bh opcode is used, then one don’t care byte must also be

clocked in after the three address bytes.

After the three address bytes (and the one don’t care byte if using opcode 0Bh) have been

clocked in, additional clock cycles will result in serial data being output on the SO pin. The data

is always output with the MSB of a byte first. When the last byte (3FFFFFh) of the memory array

has been read, the device will continue reading back at the beginning of the array (000000h). No

delays will be incurred when wrapping around from the end of the array to the beginning of the

array.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-

ance state. The CS pin can be deasserted at any time and does not require that a full byte of

data be read.

Figure 7-1. Read Array – 0Bh Opcode

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

SI

OPCODE

ADDRESS BITS A23-A0

A

DON'T CARE

0

1

0

1

A

X

MSB

DATA BYTE 1

D

HIGH-IMPEDANCE

D

SO

MSB

Figure 7-2. Read Array – 03h Opcode

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

SCK

SI

OPCODE

ADDRESS BITS A23-A0

0

1

A

MSB

DATA BYTE 1

HIGH-IMPEDANCE

D

SO

MSB

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3633C–DFLASH–08/06

8. Program and Erase Commands

8.1

Byte/Page Program

The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of

data to be programmed into previously erased memory locations. An erased memory location is

one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page

Program command can be started, the Write Enable command must have been previously

issued to the device (see Write Enable command description) to set the Write Enable Latch

(WEL) bit of the Status Register to a logical “1” state.

To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device

followed by the three address bytes denoting the first byte location of the memory array to begin

programming at. After the address bytes have been clocked in, data can then be clocked into the

device and will be stored in an internal buffer.

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page

boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations

will be programmed will apply. In this situation, any data that is sent to the device that goes

beyond the end of the page will wrap around back to the beginning of the same page. For exam-

ple, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to

the device, then the first two bytes of data will be programmed at addresses 0000FEh and

0000FFh while the last byte of data will be programmed at address 000000h. The remaining

bytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change.

In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes

sent will be latched into the internal buffer.

When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro-

gram it into the appropriate memory array locations based on the starting address specified by

A23-A0 and the number of complete data bytes sent to the device. If less than 256 bytes of data

were sent to the device, then the remaining bytes within the page will not be altered. The pro-

gramming of the data bytes is internally self-timed and should take place in a time of t_PP.

The three address bytes and at least one complete byte of data must be clocked into the device

before the CS pin is deasserted; otherwise, the device will abort the operation and no data will

be programmed into the memory array. In addition, if the address specified by A23-A0 points to

a memory location within a sector that is in the protected state (see “Protect Sector” on page

12), then the Byte/Page Program command will not be executed, and the device will return to the

idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset

back to the logical “0” state if the program cycle aborts due to an incomplete address being sent,

an incomplete byte of data being sent, or because the memory location to be programmed is

protected.

While the device is programming, the Status Register can be read and will indicate that the

device is busy. For faster throughput, it is recommended that the Status Register be polled

rather than waiting the t_PPtime to determine if the data bytes have finished programming. At

some point before the program cycle completes, the WEL bit in the Status Register will be reset

back to the logical “0” state.

8

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

Figure 8-1. Byte Program

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DATA IN

0

1

0

A

D

MSB

HIGH-IMPEDANCE

SO

Figure 8-2. Page Program

CS

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DATA IN BYTE 1

DATA IN BYTE n

0

1

0

A

D

MSB

HIGH-IMPEDANCE

SO

8.2

Block Erase

A block of 4K-, 32K-, or 64K-bytes can be erased (all bits set to the logical “1” state) in a single

operation by using one of three different opcodes for the Block Erase command. An opcode of

20h is used for a 4K-byte erase, an opcode of 52h is used for a 32K-byte erase, and an opcode

of D8h is used for a 64K-byte erase. Before a Block Erase command can be started, the Write

Enable command must have been previously issued to the device to set the WEL bit of the Sta-

tus Register to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,

52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three

address bytes specifying an address within the 4K-, 32K-, or 64K-byte block to be erased must

be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is

deasserted, the device will erase the appropriate block. The erasing of the block is internally

self-timed and should take place in a time of t_BLKE

.

Since the Block Erase command erases a region of bytes, the lower order address bits do not

need to be decoded by the device. Therefore, for a 4K-byte erase, address bits A11-A0 will be

ignored by the device and their values can be either a logical “1” or “0”. For a 32K-byte erase,

address bits A14-A0 will be ignored, and for a 64K-byte erase, address bits A15-A0 will be

ignored by the device. Despite the lower order address bits not being decoded by the device, the

complete three address bytes must still be clocked into the device before the CS pin is deas-

serted; otherwise, the device will abort the operation and no erase operation will be performed.

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3633C–DFLASH–08/06

If the address specified by A23-A0 points to a memory location within a sector that is in the pro-

tected state, then the Block Erase command will not be executed, and the device will return to

the idle state once the CS pin has been deasserted.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle

aborts due to an incomplete address being sent or because a memory location within the region

to be erased is protected.

While the device is executing a successful erase cycle, the Status Register can be read and will

indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-

ter be polled rather than waiting the t_BLKEtime to determine if the device has finished erasing. At

some point before the erase cycle completes, the WEL bit in the Status Register will be reset

back to the logical “0” state.

Figure 8-3. Block Erase

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

26 27 28 29 30 31

SCK

SI

OPCODE

ADDRESS BITS A23-A0

C

A

MSB

HIGH-IMPEDANCE

SO

8.3

Chip Erase

The entire memory array can be erased in a single operation by using the Chip Erase command.

Before a Chip Erase command can be started, the Write Enable command must have been pre-

viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in

device functionality when utilizing the two opcodes, so they can be used interchangeably. To

perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.

Since the entire memory array is to be erased, no address bytes need to be clocked into the

device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted,

the device will erase the entire memory array. The erasing of the device is internally self-timed

and should take place in a time of t_CHPE

.

The complete opcode must be clocked into the device before the CS pin is deasserted; other-

wise, no erase will be performed. In addition, if any sector of the memory array is in the

protected state, then the Chip Erase command will not be executed, and the device will return to

the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be

reset back to the logical “0” state if a sector is in the protected state.

While the device is executing a successful erase cycle, the Status Register can be read and will

indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-

ter be polled rather than waiting the t_CHPEtime to determine if the device has finished erasing. At

some point before the erase cycle completes, the WEL bit in the Status Register will be reset

back to the logical “0” state.

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AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

Figure 8-4. Chip Erase

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

C

MSB

HIGH-IMPEDANCE

SO

9. Protection Commands and Features

9.1

Write Enable

The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis-

ter to a logical “1” state. The WEL bit must be set before a program, erase, Protect Sector,

Unprotect Sector, or Write Status Register command can be executed. This makes the issuance

of these commands a two step process, thereby reducing the chances of a command being

accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the

issuance of one of these commands, then the command will not be executed.

To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h

must be clocked into the device. No address bytes need to be clocked into the device, and any

data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in

the Status Register will be set to a logical “1”. The complete opcode must be clocked into the

device before the CS pin is deasserted; otherwise, the device will abort the operation and the

state of the WEL bit will not change.

Figure 9-1. Write Enable

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

0

1

0

MSB

HIGH-IMPEDANCE

SO

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3633C–DFLASH–08/06

9.2

Write Disable

The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-

ister to the logical “0” state. With the WEL bit reset, all program, erase, Protect Sector, Unprotect

Sector, and Write Status Register commands will not be executed. The Write Disable command

is also used to exit the Sequential Program Mode. Other conditions can also cause the WEL bit

to be reset; for more details, refer to the WEL bit section of the Status Register description on

page 20.

To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h

must be clocked into the device. No address bytes need to be clocked into the device, and any

data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in

the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the

device before the CS pin is deasserted; otherwise, the device will abort the operation and the

state of the WEL bit will not change.

Figure 9-2. Write Disable

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

0

1

0

MSB

HIGH-IMPEDANCE

SO

9.3

Protect Sector

Every physical sector of the device has a corresponding single-bit Sector Protection Register

that is used to control the software protection of a sector. Upon device power-up or after a

device reset, each Sector Protection Register will default to the logical “1” state indicating that all

sectors are protected and cannot be programmed or erased.

Issuing the Protect Sector command to a particular sector address will set the corresponding

Sector Protection Register to the logical “1” state. The following table outlines the two states of

the Sector Protection Registers.

Table 9-1.

Sector Protection Register Values

Value

Sector Protection Status

0

1

Sector is unprotected and can be programmed and erased.

Sector is protected and cannot be programmed or erased. This is the default state.

Before the Protect Sector command can be issued, the Write Enable command must have been

previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Protect

Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into

the device followed by three address bytes designating any address within the sector to be

locked. Any additional data clocked into the device will be ignored. When the CS pin is deas-

serted, the Sector Protection Register corresponding to the physical sector addressed by A23-

A0 will be set to the logical “1” state, and the sector itself will then be protected from program

12

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

and erase operations. In addition, the WEL bit in the Status Register will be reset back to the log-

ical “0” state.

The complete three address bytes must be clocked into the device before the CS pin is deas-

serted; otherwise, the device will abort the operation, the state of the Sector Protection Register

will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.

As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector

Protection Registers can themselves be locked from updates by using the SPRL (Sector Protec-

tion Registers Locked) bit of the Status Register (please refer to “Status Register Commands”

on page 19 for more details). If the Sector Protection Registers are locked, then any attempts to

issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the

Status Register back to a logical “0” and return to the idle state once the CS pin has been

deasserted.

Figure 9-3. Protect Sector

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

26 27 28 29 30 31

SCK

SI

OPCODE

ADDRESS BITS A23-A0

0

1

0

1

0

A

MSB

HIGH-IMPEDANCE

SO

9.4

Unprotect Sector

Issuing the Unprotect Sector command to a particular sector address will reset the correspond-

ing Sector Protection Register to the logical “0” state (see Table 9-1 on page 12 for Sector

Protection Register values). Every physical sector of the device has a corresponding single-bit

Sector Protection Register that is used to control the software protection of a sector.

Before the Unprotect Sector command can be issued, the Write Enable command must have

been previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the

Unprotect Sector command, the CS pin must first be asserted and the opcode of 39h must be

clocked into the device. After the opcode has been clocked in, the three address bytes designat-

ing any address within the sector to be unlocked must be clocked in. Any additional data clocked

into the device after the address bytes will be ignored. When the CS pin is deasserted, the Sec-

tor Protection Register corresponding to the sector addressed by A23-A0 will be reset to the

logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status

Register will be reset back to the logical “0” state.

The complete three address bytes must be clocked into the device before the CS pin is deas-

serted; otherwise, the device will abort the operation, the state of the Sector Protection Register

will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.

As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Pro-

tection Registers can themselves be locked from updates by using the SPRL (Sector Protection

Registers Locked) bit of the Status Register (please refer to “Status Register Commands” on

page 19 for more details). If the Sector Protection Registers are locked, then any attempts to

13

3633C–DFLASH–08/06

issue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in the

Status Register back to a logical “0” and return to the idle state once the CS pin has been

deasserted.

Figure 9-4. Unprotect Sector

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

26 27 28 29 30 31

SCK

SI

OPCODE

ADDRESS BITS A23-A0

0

1

0

1

A

MSB

HIGH-IMPEDANCE

SO

9.5

Global Protect/Unprotect

The Global Protect and Global Unprotect features can work in conjunction with the Protect Sec-

tor and Unprotect Sector functions. For example, a system can globally protect the entire

memory array and then use the Unprotect Sector command to individually unprotect certain sec-

tors and individually reprotect them later by using the Protect Sector command. Likewise, a

system can globally unprotect the entire memory array and then individually protect certain sec-

tors as needed.

Performing a Global Protect or Global Unprotect is accomplished by writing a certain combina-

tion of data to the Status Register using the Write Status Register command (see “Write Status

Register” section on page 21 for command execution details). The Write Status Register com-

mand is also used to modify the SPRL (Sector Protection Registers Locked) bit to control

hardware and software locking.

To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met and the

system must write a logical “1” to bits 5, 4, 3, and 2 of the Status Register. Conversely, to per-

form a Global Unprotect, the same WP and SPRL conditions must be met but the system must

write a logical “0” to bits 5, 4, 3, and 2 of the Status Register. Table 9-2 details the conditions

necessary for a Global Protect or Global Unprotect to be performed.

14

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

Table 9-2.

Valid SPRL and Global Protect/Unprotect Conditions

New

Write Status

Register Data

Current

SPRL

Value

New

SPRL

Value

WP

State

Bit

7 6 5 4 3 2 1 0

Protection Operation

0 x 0 0 0 0 x x

0 x 0 0 0 1 x x

↕

Global Unprotect – all Sector Protection Registers reset to 0

No change to current protection.

Global Protect – all Sector Protection Registers set to 1

0

0 x 1 1 1 0 x x

0 x 1 1 1 1 x x

0

1

0

1

0

1 x 0 0 0 0 x x

1 x 0 0 0 1 x x

↕

Global Unprotect – all Sector Protection Registers reset to 0

No change to current protection.

Global Protect – all Sector Protection Registers set to 1

1

1 x 1 1 1 0 x x

1 x 1 1 1 1 x x

No change to the current protection level. All sectors currently

protected will remain protected and all sectors currently unprotected

will remain unprotected.

x x x x x x x x

The Sector Protection Registers are hard-locked and cannot be

changed when the WP pin is LOW and the current state of SPRL is 1.

Therefore, a Global Protect/Unprotect will not occur. In addition, the

SPRL bit cannot be changed (the WP pin must be HIGH in order to

change SPRL back to a 0).

0 x 0 0 0 0 x x

0 x 0 0 0 1 x x

↕

Global Unprotect – all Sector Protection Registers reset to 0

No change to current protection.

Global Protect – all Sector Protection Registers set to 1

0

0 x 1 1 1 0 x x

0 x 1 1 1 1 x x

1 x 0 0 0 0 x x

1 x 0 0 0 1 x x

↕

Global Unprotect – all Sector Protection Registers reset to 0

No change to current protection.

Global Protect – all Sector Protection Registers set to 1

1

1 x 1 1 1 0 x x

1 x 1 1 1 1 x x

0 x 0 0 0 0 x x

0 x 0 0 0 1 x x

↕

No change to the current protection level. All sectors

currently protected will remain protected, and all sectors

currently unprotected will remain unprotected.

0

0 x 1 1 1 0 x x

0 x 1 1 1 1 x x

The Sector Protection Registers are soft-locked and cannot

be changed when the current state of SPRL is 1. Therefore,

a Global Protect/Unprotect will not occur. However, the

SPRL bit can be changed back to a 0 from a 1 since the WP

pin is HIGH. To perform a Global Protect/Unprotect, the

Write Status Register command must be issued again after

the SPRL bit has been changed from a 1 to a 0.

1

1 x 0 0 0 0 x x

1 x 0 0 0 1 x x

↕

1

1 x 1 1 1 0 x x

1 x 1 1 1 1 x x

Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection

Registers are not locked), then writing a 00h to the Status Register will perform a Global Unpro-

tect without changing the state of the SPRL bit. Similarly, writing a 7Fh to the Status Register will

perform a Global Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, of

course, be changed to a logical “1” by writing an FFh if software-locking or hardware-locking is

desired along with the Global Protect.

15

3633C–DFLASH–08/06

If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-

tect, then the system can simply write a 0Fh to the Status Register to change the SPRL bit from

a logical “1” to a logical “0” provided the WP pin is deasserted. Likewise, the system can write an

F0h to change the SPRL bit from a logical “0” to a logical “1” without affecting the current sector

protection status (no changes will be made to the Sector Protection Registers).

When writing to the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will be

decoded by the device for the purposes of the Global Protect and Global Unprotect functions.

Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading the Status Register,

bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of

the WP pin and the sector protection status. Please refer to the “Read Status Register” section

and Table 10-1 on page 19 for details on the Status Register format and what values can be

read for bits 5, 4, 3, and 2.

9.6

Read Sector Protection Registers

The Sector Protection Registers can be read to determine the current software protection status

of each sector. Reading the Sector Protection Registers, however, will not determine the status

of the WP pin.

To read the Sector Protection Register for a particular sector, the CS pin must first be asserted

and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address

bytes designating any address within the sector must be clocked in. After the last address byte

has been clocked in, the device will begin outputting data on the SO pin during every subse-

quent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote

the value of the appropriate Sector Protection Register

Table 9-3.

Output Data

00h

FFh

Read Sector Protection Register – Output Data

Sector Protection Register Value

Sector Protection Register value is 0 (sector is unprotected).

Sector Protection Register value is 1 (sector is protected).

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-

ance state. The CS pin can be deasserted at any time and does not require that a full byte of

data be read.

In addition to reading the individual Sector Protection Registers, the Software Protection Status

(SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are

software protected (please refer to “Status Register Commands” on page 19 for more details).

16

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

Figure 9-5. Read Sector Protection Register

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

SCK

SI

OPCODE

ADDRESS BITS A23-A0

0

1

0

A

MSB

DATA BYTE

HIGH-IMPEDANCE

D

SO

MSB

9.7

Protected States and the Write Protect (WP) Pin

The WP pin is not linked to the memory array itself and has no direct effect on the protection sta-

tus of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection

Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism

of the device. For hardware locking to be active, two conditions must be met – the WP pin must

be asserted and the SPRL bit must be in the logical “1” state.

When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit

itself is also locked. Therefore, sectors that are protected will be locked in the protected state,

and sectors that are unprotected will be locked in the unprotected state. These states cannot be

changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and

Write Status Register commands will be ignored. In order to modify the protection status of a

sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be

reset back to the logical “0” state using the Write Status Register command. When resetting the

SPRL bit back to a logical “0”, it is not possible to perform a Global Protect or Global Unprotect

at the same time since the Sector Protection Registers remain soft-locked until after the Write

Status Register command has been executed.

If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”,

the only way to reset the bit back to the logical “0” state is to power-cycle or reset the device.

This allows a system to power-up with all sectors software protected but not hardware locked.

Therefore, sectors can be unprotected and protected as needed and then hardware locked at a

later time by simply setting the SPRL bit in the Status Register.

When the WP pin is deasserted, or if the WP pin is permanently connected to V_CC, the SPRL bit

in the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. This

provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector com-

mands from being processed. When changing the SPRL bit to a logical “1” from a logical “0”, it is

also possible to perform a Global Protect or Global Unprotect at the same time by writing the

appropriate values into bits 5, 4, 3, and 2 of the Status Register.

17

3633C–DFLASH–08/06

The tables below detail the various protection and locking states of the device.

Table 9-4.

Software Protection Register States

Sector Protection Register

n⁽¹⁾

Sector

n⁽¹⁾

WP

0

1

Unprotected

Protected

X

(Don't Care)

Note:

1. “n” represents a sector number

Table 9-5.

Hardware and Software Locking

WP

SPRL

Locking

SPRL Change Allowed

Sector Protection Registers

Unlocked and modifiable using the

Protect and Unprotect Sector

commands. Global Protect and

Unprotect can also be performed.

0

1

0

1

Can be modified from 0 to 1

Locked in current state. Protect and

Unprotect Sector commands will be

ignored. Global Protect and

Hardware

Locked

0

1

Locked

Unprotect cannot be performed.

Unlocked and modifiable using the

Protect and Unprotect Sector

commands. Global Protect and

Unprotect can also be performed.

Can be modified from 0 to 1

Can be modified from 1 to 0

Locked in current state. Protect and

Unprotect Sector commands will be

ignored. Global Protect and

Software

Locked

Unprotect cannot be performed.

18

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

10. Status Register Commands

10.1 Read Status Register

The Status Register can be read to determine the device’s ready/busy status, as well as the sta-

tus of many other functions such as Hardware Locking and Software Protection. The Status

Register can be read at any time, including during an internally self-timed program or erase

operation.

To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be

clocked into the device. After the last bit of the opcode has been clocked in, the device will begin

outputting Status Register data on the SO pin during every subsequent clock cycle. After the last

bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting

again with bit 7 as long as the CS pin remains asserted and the SCK pin is being pulsed. The

data in the Status Register is constantly being updated, so each repeating sequence will output

new data.

Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin

into a high-impedance state. The CS pin can be deasserted at any time and does not require

that a full byte of data be read.

Table 10-1. Status Register Format

Bit⁽¹⁾

Name

Type⁽²⁾

Description

0

1

0

x

0

1

Sector Protection Registers are unlocked (default).

7

SPRL

Sector Protection Registers Locked

R/W

Sector Protection Registers are locked.

Reserved for future use.

6

5

RES

Reserved for future use

R

Reserved for future use (value is undefined).

WP is asserted.

4

WPP

SWP

WEL

Write Protect (WP) Pin Status

Software Protection Status

Write Enable Latch Status

R

WP is deasserted.

All sectors are software unprotected (all Sector

Protection Registers are 0).

00

01

Some sectors are software protected. Read individual

Sector Protection Registers to determine which

sectors are protected.

3:2

10

11

Reserved for future use.

All sectors are software protected (all Sector

Protection Registers are 1 – default).

0

1

0

1

Device is not write enabled (default).

Device is write enabled.

1

0

R

Device is ready.

RDY/BSY Ready/Busy Status

Device is busy with an internal operation.

Notes: 1. Only bit 7 of the Status Register will be modified when using the Write Status Register command.

2. R/W = Readable and writeable

R = Readable only

19

3633C–DFLASH–08/06

10.1.1

SPRL Bit

The SPRL bit is used to control whether the Sector Protection Registers can be modified or not.

When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and can-

not be modified with the Protect Sector and Unprotect Sector commands (the device will ignore

these commands). In addition, the Global Protect and Global Unprotect features cannot be per-

formed. Any sectors that are presently protected will remain protected, and any sectors that are

presently unprotected will remain unprotected.

When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and

can be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Pro-

tect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to the

logical “0” state after a power-up or a device reset.

The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin

is asserted, then the SPRL bit may only be changed from a logical “0” (Sector Protection Regis-

ters are unlocked) to a logical “1” (Sector Protection Registers are locked). In order to reset the

SPRL bit back to a logical “0” using the Write Status Register command, the WP pin will have to

first be deasserted.

The SPRL bit is the only bit of the Status Register than can be user modified via the Write Status

Register command.

10.1.2

10.1.3

WPP Bit

The WPP bit can be read to determine if the WP pin has been asserted or not.

SWP Bits

The SWP bits provide feedback on the software protection status for the device. There are three

possible combinations of the SWP bits that indicate whether none, some, or all of the sectors

have been protected using the Protect Sector command or the Global Protect feature. If the

SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro-

tection Registers can be read with the Read Sector Protection Registers command to determine

which sectors are in fact protected.

10.1.4

WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is

in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect

Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a

device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automati-

cally under the following conditions:

• Write Disable operation completes successfully

• Write Status Register operation completes successfully or aborts

• Protect Sector operation completes successfully or aborts

• Unprotect Sector operation completes successfully or aborts

• Byte/Page Program operation completes successfully or aborts

• Block Erase operation completes successfully or aborts

• Chip Erase operation completes successfully or aborts

20

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts

due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is

deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire

opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-

mand must have been clocked into the device.

10.1.5

RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program

or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase

cycle, new Status Register data must be continually clocked out of the device until the state of

the RDY/BSY bit changes from a logical “1” to a logical “0”.

Figure 10-1. Read Status Register

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCK

SI

OPCODE

0

1

0

1

MSB

STATUS REGISTER DATA

HIGH-IMPEDANCE

D

SO

MSB

10.2 Write Status Register

The Write Status Register command is used to modify the SPRL bit of the Status Register

and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-

ter command can be issued, the Write Enable command must have been previously issued to

set the WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register command, the CS pin must first be asserted and the opcode

of 01h must be clocked into the device followed by one byte of data. The one byte of data con-

sists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or

Unprotect should be performed, and two additional don’t care bits (see Table 10-2). Any addi-

tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the

SPRL bit in the Status Register will be modified and the WEL bit in the Status Register will be

reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before

the Write Status Register command was executed (the prior state of the SPRL bit) will determine

whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global

Protect/Unprotect” section on page 14 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted;

otherwise, the device will abort the operation, the state of the SPRL bit will not change, no

potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register

will be reset back to the logical “0” state.

If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made

to reset the SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register

command will be ignored, and the WEL bit in the Status Register will be reset back to the logical

“0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.

21

3633C–DFLASH–08/06

Table 10-2. Write Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPRL

X

Global Protect/Unprotect

X

Figure 10-2. Write Status Register

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCK

SI

OPCODE

STATUS REGISTER IN

0

1

D

X

D

X

MSB

HIGH-IMPEDANCE

SO

11. Other Commands and Functions

11.1 Read Manufacturer and Device ID

Identification information can be read from the device to enable systems to electronically query

and identify the device while it is in system. The identification method and the command opcode

comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI

Compatible Serial Interface Memory Devices”. The type of information that can be read from the

device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-

dor specific Extended Device Information.

To read the identification information, the CS pin must first be asserted and the opcode of 9Fh

must be clocked into the device. After the opcode has been clocked in, the device will begin out-

putting the identification data on the SO pin during the subsequent clock cycles. The first byte

that will be output will be the Manufacturer ID followed by two bytes of Device ID information.

The fourth byte output will be the Extended Device Information String Length, which will be 00h

indicating that no Extended Device Information follows. After the Extended Device Information

String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional

clock cycles will have no affect on the SO pin and no data will be output. As indicated in the

JEDEC standard, reading the Extended Device Information String Length and any subsequent

data is optional.

Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put

the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not

require that a full byte of data be read.

Table 11-1. Manufacturer and Device ID Information

Byte No.

Data Type

Value

1Fh

47h

1

2

3

4

Manufacturer ID

Device ID (Part 1)

Device ID (Part 2)

00h

Extended Device Information String Length

00h

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AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

Table 11-2. Manufacturer and Device ID Details

Hex

Data Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value

Details

JEDEC Assigned Code

Manufacturer ID

1Fh

JEDEC Code:

0001 1111 (1Fh for Atmel)

0

1

0

1

0

1

0

Family Code

Density Code

1

Family Code:

Density Code:

010 (AT26DFxxx series)

00111 (32-Mbit)

Device ID (Part 1)

Device ID (Part 2)

47h

00h

1

MLC Code

0

1

Product Version Code

MLC Code:

Product Version:

000 (1-bit/cell technology)

00000 (Initial version)

0

Figure 11-1. Read Manufacturer and Device ID

CS

0

6

7

8

14 15 16

22 23 24

30 31 32

38

SCK

SI

OPCODE

9Fh

HIGH-IMPEDANCE

1Fh

46h

00h

SO

MANUFACTURER ID

DEVICE ID

BYTE 1

DEVICE ID

BYTE 2

EXTENDED

DEVICE

INFORMATION

STRING LENGTH

Note: Each transition

shown for SI and SO represents one byte (8 bits)

11.2 Deep Power-Down

During normal operation, the device will be placed in the standby mode to consume less power

as long as the CS pin remains deasserted and no internal operation is in progress. The Deep

Power-Down command offers the ability to place the device into an even lower power consump-

tion state called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands including the Read Status

Register command will be ignored with the exception of the Resume from Deep Power-Down

command. Since all commands will be ignored, the mode can be used as an extra protection

mechanism against program and erase operations.

Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking

in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the

device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the

Deep Power-Down mode within the maximum time of t_EDPD

.

The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device

will abort the operation and return to the standby mode once the CS pin is deasserted. In addi-

tion, the device will default to the standby mode after a power-cycle or a device reset.

The Deep Power-Down command will be ignored if an internally self-timed operation such as a

program or erase cycle is in progress. The Deep Power-Down command must be reissued after

the internally self-timed operation has been completed in order for the device to enter the Deep

Power-Down mode.

23

3633C–DFLASH–08/06

Figure 11-2. Deep Power-Down

CS

t_EDPD

0

1

2

3

4

5

6

7

SCK

OPCODE

1

0

1

0

1

SI

MSB

HIGH-IMPEDANCE

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

11.3 Resume from Deep Power-Down

In order exit the Deep Power-Down mode and resume normal device operation, the Resume

from Deep Power-Down command must be issued. The Resume from Deep Power-Down com-

mand is the only command that the device will recognize while in the Deep Power-Down mode.

To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of

ABh must be clocked into the device. Any additional data clocked into the device after the

opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Power-

Down mode within the maximum time of t_RDPDand return to the standby mode. After the device

has returned to the standby mode, normal command operations such as Read Array can be

resumed.

If the complete opcode is not clocked in before the CS pin is deasserted, then the device will

abort the operation and return to the Deep Power-Down mode.

Figure 11-3. Resume from Deep Power-Down

CS

t_RDPD

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

1

0

1

0

1

0

1

MSB

HIGH-IMPEDANCE

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

24

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

12. Electrical Specifications

12.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground.....................................-0.6V to +4.1V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.5V

12.2 DC and AC Operating Range

AT26DF321

-40°C to +85°C

2.7V to 3.6V

Operating Temperature (Case)

V_CCPower Supply

Ind.

12.3 DC Characteristics

Symbol Parameter

Condition

CS, WP = V_CC

Min

Typ

Max

Units

,

I_SB

Standby Current

25

35

µA

all inputs at CMOS levels

CS, WP = VCC,

I_DPD

Deep Power-Down Current

4

11

10

8

µA

all inputs at CMOS levels

f = 66 MHz, I_OUT= 0 mA,

CS = V_IL, V_CC= Max

15

14

12

10

f = 50 MHz; I_OUT= 0 mA,

CS = V_IL, V_CC= Max

I_CC1

Active Current, Read Operation

mA

f = 33 MHz, I_OUT= 0 mA,

CS = V_IL, V_CC= Max

f = 20 MHz, I_OUT= 0 mA,

CS = V_IL, V_CC= Max

7

I_CC2

I_CC3

I_LI

Active Current, Program Operation CS = V_CC, V_CC= Max

12

14

18

mA

µA

V

Active Current, Erase Operation

Input Leakage Current

Output Leakage Current

Input Low Voltage

_CS= V_CC, V_CC= Max

V_IN= CMOS levels

V_OUT= CMOS levels

20

1

I_LO

V_IL

0.3 x V_CC

V_IH

V_OL

V_OH

Input High Voltage

0.7 x V_CC

V_CC- 0.2

V

Output Low Voltage

I_OL= 1.6 mA, V_CC= Min

I_OH= -100 µA

0.4

V

Output High Voltage

V

25

3633C–DFLASH–08/06

12.4 AC Characteristics

Symbol

f_SCK

Parameter

Min

Max

66

Units

MHz

ns

Serial Clock (SCK) Frequency

SCK Frequency for Read Array (Low Frequency – 03h opcode)

SCK High Time

f_RDLF

33

t_SCKH

t_SCKL

6.8

0.1

50

5

SCK Low Time

ns

(1)

t_SCKR

SCK Rise Time, Peak-to-Peak (Slew Rate)

SCK Fall Time, Peak-to-Peak (Slew Rate)

Chip Select High Time

V/ns

ns

(1)

t_SCKF

t_CSH

t_CSLS

t_CSLH

t_CSHS

t_CSHH

t_DS

Chip Select Low Setup Time (relative to SCK)

Chip Select Low Hold Time (relative to SCK)

Chip Select High Setup Time (relative to SCK)

Chip Select High Hold Time (relative to SCK)

Data In Setup Time

ns

5

ns

5

ns

5

ns

2

ns

t_DH

Data In Hold Time

3

ns

(1)

t_DIS

Output Disable Time

6

ns

t_V

Output Valid Time

ns

t_OH

Output Hold Time

0

ns

(1)(2)

t_WPS

Write Protect Setup Time

20

ns

(1)(2)

t_WPH

Write Protect Hold Time

100

ns

(1)

t_SECP

Sector Protect Time (from Chip Select High)

Sector Unprotect Time (from Chip Select High)

Chip Select High to Deep Power-Down

Chip Select High to Standby Mode

20

3

ns

(1)

t_SECUP

ns

(1)

t_EDPD

µs

(1)

t_RDPD

3

µs

Notes: 1. Not 100% tested (value guaranteed by design and characterization).

2. Only applicable as a constraint for the Write Status Register command when SPRL = 1.

12.5 Program and Erase Characteristics

Symbol

t_PP

Parameter

Min

Typ

Max

Units

ms

Page Program Time (256 Bytes)

Byte Program Time

1.5

6

5.0

t_BP

µs

4-Kbyte

0.05

0.35

0.7

36

0.2

0.6

1.0

56

t_BLKE

Block Erase Time

32-Kbyte

64-Kbyte

sec

(1)

t_CHPE

Chip Erase Time

sec

ns

(1)

t_WRSR

Write Status Register Time

200

Notes: 1. Not 100% tested (value guaranteed by design and characterization).

26

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

12.6 Power-Up Conditions

Parameter

Min

Max

Units

µs

Minimum V_CCto Chip Select Low Time

Power-up Device Delay Before Program or Erase Allowed

Power-On Reset Voltage

50

10

ms

V

1.5

2.5

12.7 Input Test Waveforms and Measurement Levels

2.4V

AC

DRIVING

1.5V

MEASUREMENT

LEVEL

LEVELS

0.45V

t_R, t_F< 2 ns (10% to 90%)

12.8 Output Test Load

DEVICE

UNDER

TEST

30 pF

27

3633C–DFLASH–08/06

13. AC Waveforms

Figure 13-1. Serial Input Timing

t_CSH

CS

t_CSLS

t_CSLH

t_SCKL

t_CSHH

t_SCKH

t_CSHS

SCK

t_DS

t_DH

MSB

LSB

MSB

SI

HIGH-IMPEDANCE

SO

Figure 13-2. Serial Output Timing

CS

t_SCKH

t_SCKL

t_DIS

SCK

SI

t_OH

t_V

SO

Figure 13-3. WP Timing for Write Status Register Command When SPRL = 1

CS

t_WPS

t_WPH

WP

SCK

SI

0

X

MSB

MSB OF

WRITE STATUS REGISTER

OPCODE

LSB OF

WRITE STATUS REGISTER

DATA BYTE

MSB OF

NEXT OPCODE

HIGH-IMPEDANCE

SO

28

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

14. Ordering Information

14.1 Green Package Options (Pb/Halide-free/RoHS Compliant)

f_SCK(MHz)

Ordering Code

AT26DF321-SU

AT26DF321-S3U

Package

8S2

Operation Range

66

Industrial

(-40°C to +85°C)

16S

Package Type

8S2

16S

8-lead, 0.209" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)

29

3633C–DFLASH–08/06

15. Packaging Information

15.1 8S2 – EIAJ SOIC

C

1

E

E1

L

N

θ

TOP VIEW

END VIEWW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.70

0.05

0.35

0.15

5.13

5.18

7.70

0.51

0°

MAX

2.16

0.25

0.48

0.35

5.35

5.40

8.26

0.85

8°

NOM

NOTE

SYMBOL

A1

A

A1

b

5

C

D

E1

E

D

2, 3

L

SIDE VIEW

θ

e

1.27 BSC

4

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs are not included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

4/7/06

TITLE

DRAWING NO.

REV.

8S2, 8-lead, 0.209" Body, Plastic Small

Outline Package (EIAJ)

2325 Orchard Parkway

San Jose, CA 95131

8S2

D

R

30

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

15.2 16S – SOIC

1

E

H

E

End View

N

L

C

Top View

COMMON DIMENSIONS

(Unit of Measure = mm)

e

b

MIN

2.35

0.10

0.31

MAX

2.65

0.30

0.51

NOM

NOTE

SYMBOL

A

A1

b

–

A1

A

–

D

E

H

L

10.30 BSC

7.50 BSC

10.30 BSC

–

2

D

3

Side View

0.40

0.20

1.27

4

e

1.27 BSC

C

0.33

Notes:

1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AA for additional information.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not

exceed 0.15 mm (0.006") per side.

3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm

(0.010") per side.

4. L is the length of the terminal for soldering to a substrate.

11/02/05

TITLE

DRAWING NO.

16S

REV.

2325 Orchard Parkway

San Jose, CA 95131

16S, 16-lead, 0.300" Wide Body, Plastic Gull

Wing Small Outline Package (SOIC)

A

R

31

3633C–DFLASH–08/06

16. Revision History

Revision Level – Release Date

A – May 2006

History

Initial release

B – July 2006

Corrected typographical errors.

Changed description of bit 5 in Table 10-1 from “0” to “x” and specified that the value is

undefined.

Removed MLF package offerings.

C – August 2006

Added 8-lead SOIC (200-mil wide) package.

Changed ordering code for 16-lead SOIC from AT26DF321-SU to AT26DF321-S3U.

Added errata regarding Chip Erase.

32

AT26DF321 [Preliminary]

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

17. Errata

17.1 Chip Erase

17.1.1

Issue

In a certain percentage of units, the Chip Erase feature may not function correctly and may

adversely affect device operation. Therefore, it is recommended that the Chip Erase commands

(opcodes 60h and C7h) not be used.

17.1.2

17.1.3

Workaround

Resolution

Use the Block Erase (4KB, 32KB, or 64KB) commands as an alternative. The Block Erase func-

tion is not affected by the Chip Erase issue.

The Chip Erase feature is being fixed with a new revision of the device. Please contact Atmel for

the estimated availability of devices with the fix.

33

3633C–DFLASH–08/06

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High-Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

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WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

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istered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

3633C–DFLASH–08/06


型号：	AT26DF321
厂家：	ATMEL
描述：	32-megabit 2.7-volt Only Serial Firmware DataFlash Memory 32兆位2.7伏，只有串行固件的DataFlash内存
文件：	总34页 (文件大小：566K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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