AT27C1024-45VJ [ATMEL]
OTP ROM, 64KX16, 45ns, CMOS, PDSO40, 10 X 14 MM, PLASTIC, MO-142CA, VSOP1-40;
| 型号： | AT27C1024-45VJ |
| 厂家： | 
ATMEL |
| 描述： | OTP ROM, 64KX16, 45ns, CMOS, PDSO40, 10 X 14 MM, PLASTIC, MO-142CA, VSOP1-40 OTP只读存储器 光电二极管 |
| 文件： | 总14页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 45 ns
• Low-Power CMOS Operation
– 100 µA Max Standby
– 30 mA Max Active at 5 MHz
• JEDEC Standard Packages
– 40-lead PDIP
– 44-lead PLCC
– 40-lead VSOP
1-Megabit
(64K x 16)
OTP EPROM
• Direct Upgrade from 512K (AT27C516) EPROM
• 5V 10ꢀ Power Supply
• High-Reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
• Rapid Programming Algorithm – 100 µs/Word (Typical)
• CMOS and TTL Compatible Inputs and Outputs
• Integrated Product Identification Code
• Industrial and Automotive Temperature Ranges
• Green (Pb/Halide-free) Packaging Option
AT27C1024
1. Description
The AT27C1024 is a low-power, high-performance 1,048,576 bit one-time program-
mable read-only memory (OTP EPROM) organized 64K by 16 bits. It requires only
one 5V power supply in normal read mode operation. Any word can be accessed in
less than 45 ns, eliminating the need for speed reducing WAIT states. The by-16 orga-
nization make this part ideal for high-performance 16- and 32-bit microprocessor
systems.
In read mode, the AT27C1024 typically consumes 15 mA. Standby mode supply cur-
rent is typically less than 10 µA.
The AT27C1024 is available in industry-standard JEDEC-approved one-time pro-
grammable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features
two-line control (CE, OE) to eliminate bus contention in high-speed systems.
With high density 64K word storage capability, the AT27C1024 allows firmware to be
stored reliably and to be accessed by the system without the delays of mass storage
media.
Atmel’s AT27C1024 have additional features to ensure high quality and efficient pro-
duction use. The RapidProgramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
100 µs/word. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
0019M–EPROM–12/07
2. Pin Configurations
Pin Name
A0 - A15
O0 - O15
CE
Function
Addresses
Outputs
Chip Enable
Output Enable
Program Strobe
No Connect
OE
PGM
NC
Note:
Both GND pins must be connected.
2.1
40-lead PDIP Top View
2.3
44-lead PLCC Top View
VPP
CE
1
2
3
4
5
6
7
8
9
40 VCC
39 PGM
38 NC
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
O15
O14
O13
O12
O11
O10
O9
O12
O11
O10
7
8
9
39 A13
38 A12
37 A11
36 A10
35 A9
34 GND
33 NC
32 A8
31 A7
30 A6
29 A5
O9 10
O8 11
GND 12
NC 13
O7 14
O6 15
O5 16
O4 17
O8 10
GND 11
O7 12
O6 13
O5 14
O4 15
O3 16
O2 17
O1 18
O0 19
OE 20
2.2
40-lead VSOP Top View – Type 1
A9
A10
A11
A12
A13
A14
A15
NC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
2
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
PGM
VCC
VPP
CE
9
A1
10
11
12
13
14
15
16
17
18
19
20
A0
OE
O0
O1
A2
O15
O14
O13
O12
O11
O10
O9
O3
O4
O5
O6
O7
GND
O8
2
AT27C1024
0019M–EPROM–12/07
AT27C1024
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce tran-
sient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the VCC and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
Temperature Under Bias.............................. -55°C to + 125° C
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature................................... -65°C to + 150° C
Voltage on Any Pin with
Respect to Ground ........................................-2.0V to + 7.0V(1)
Voltage on A9 with
Respect to Ground .....................................-2.0V to + 14.0V(1)
VPP Supply Voltage with
Respect to Ground ......................................-2.0V to + 14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
3
0019M–EPROM–12/07
6. Operating Modes
Mode/Pin
CE
VIL
X
OE
VIL
VIH
X
PGM
X(1)
X
Ai
VPP
X
Outputs
DOUT
Read
Ai
Output Disable
Standby
X
X
High Z
High Z
DIN
VIH
VIL
VIL
VIH
X
X
X(5)
VPP
VPP
VPP
Rapid Program(2)
PGM Verify
PGM Inhibit
VIH
VIL
X
VIL
VIH
X
Ai
Ai
DOUT
X
High Z
(3)
A9 = VH
Product Identification(4)
VIL
VIL
X
A0 = VIH or VIL
A1 - A15 = VIL
VCC
Identification Code
Notes: 1. X can be VIL or VIH.
2. Refer to Programming Characteristics.
3. VH = 12.0 0.5V.
4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word.
5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB
.
7. DC and AC Operating Conditions for Read Operation
AT27C1024
-45
-70
Ind.
-40°C - 85°C
-40°C - 85°C
Operating Temp. (Case)
VCC Power Supply
Auto.
5V 10%
5V 10%
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
µA
µA
µA
µA
µA
µA
mA
mA
V
Ind.
1
ILI
Input Load Current
VIN = 0V to VCC
Auto.
Ind.
5
5
10
ILO
Output Leakage Current
VPP(1)) Read/Standby Current
VCC(1) Standby Current
VOUT = 0V to VCC
VPP = VCC
Auto.
(2)
IPP1
10
ISB1 (CMOS), CE = VCC 0.3V
100
1
ISB
ISB2 (TTL), CE = 2.0 to VCC + 0.5V
f = 5 MHz, IOUT = 0 mA, CE = VIL
ICC
VCC Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
30
VIL
-0.6
2.0
0.8
VIH
VOL
VOH
VCC + 0.5
0.4
V
IOL = 2.1 mA
IOH = -400 µA
V
2.4
V
Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP..
4
AT27C1024
0019M–EPROM–12/07
AT27C1024
9. AC Characteristics for Read Operation
AT27C1024
-45
-70
Symbol
Parameter
Condition
CE = OE = VIL
OE = VIL
Min
Max
Min
Max
70
Units
ns
(1)
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
45
45
20
20
(1)
tCE
70
ns
(1)
tOE
CE = VIL
25
ns
(1)
tDF
OE or CE High to Output Float, Whichever Occurred First
25
ns
Output Hold from Address, CE or OE, Whichever
Occurred First
tOH
7
7
ns
Note:
1. See AC Waveforms for Read Operation.
10. AC Waveforms for Read Operation(1)
Notes: 1. Timing measurement reference level is 1.5V for -45. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing measure-
ment reference levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V and VIH
= 2.4V.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
.
3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
5
0019M–EPROM–12/07
11. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
10
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
12. Input Test Waveforms and Measurement Levels
For -45 devices only:
tR, tF < 5 ns (10% to 90%)
For -70 devices only:
tR, tF < 20 ns (10% to 90%)
13. Output Test Load
Note:
1. CL = 100 pF including jig capacitance except -45 devices, where CL = 30 pF.
6
AT27C1024
0019M–EPROM–12/07
AT27C1024
14. Programming Waveforms(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the AT27C1024 a 0.1 µF capacitor is required across VPP and ground to suppress sputious voltage
transients.
15. DC Programming Characteristics
TA = 25 5°C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Limits
Symbol
ILI
Parameter
Test Conditions
Min
Max
10
Units
µA
V
Input Load Current
VIN = VIL, VIH
VIL
Input Low Level
-0.6
2.0
0.8
VIH
Input High Level
VCC + 0.1
0.4
V
VOL
VOH
ICC2
IPP2
VID
Output Low Voltage
IOL = 2.1 mA
IOH = -400 µA
V
Output High Voltage
VCC Supply Current (Program and Verify)
VPP Supply Current
2.4
V
50
30
mA
mA
V
CE = PGM = VIL
A9 Product Identification Voltage
11.5
12.5
7
0019M–EPROM–12/07
16. AC Programming Characteristics
TA = 25 5° C, VCC = 6.5 0.25V, VPP = 13.0 0.25V
Limits
Symbol
tAS
Parameter
Test Conditions(1)
Min
2
Max
Units
µs
Address Setup Time
CE Setup Time
tCES
tOES
tDS
2
µs
OE Setup Time
Input Rise and Fall Times
2
µs
(10% to 90%) 20 ns
Data Setup Time
2
µs
tAH
Address Hold Time
0
µs
Input Pulse Levels
tDH
Data Hold Time
2
µs
0.45V to 2.4V
tDFP
tVPS
tVCS
tPW
OE High to Output Float Delay(2)
VPP Setup Time
0
130
ns
Input Timing Reference Level
0.8V to 2.0V
2
µs
VCC Setup Time
2
µs
PGM Program Pulse Width(3)
95
105
150
µs
Output Timing Reference Level
0.8V to 2.0V
tOE
Data Valid from OE
ns
VPP Pulse Rise Time During
Programming
tPRT
50
ns
Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven – see timing diagram.
3. Program Pulse width tolerance is 100 µsec 5%.
17. Atmel’s AT27C1024 Integrated Product Identification Code
Pins
Hex
Codes
A0
0
O15-O8
O7
0
O6
0
O5
0
O4
1
O3
1
O2
1
O1
1
O0
0
Data
001E
00F1
Manufacturer
Device Type
0
0
1
1
1
1
1
0
0
0
1
8
AT27C1024
0019M–EPROM–12/07
AT27C1024
18. Rapid Programming Algorithm
A 100 µs PGM pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs
PGM pulse without verification. Then a verification/reprogramming loop is executed for each
address. In the event a word fails to pass verification, up to 10 successive 100 µs pulses are
applied with a verification after each pulse. If the word fails to verify after 10 pulses have been
applied, the part is considered failed. After the word verifies properly, the next address is
selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words
are read again and compared with the original data to determine if the device passes or fails.
9
0019M–EPROM–12/07
19. Ordering Information
19.1 Standard Package
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
AT27C1024-45JI
AT27C1024-45PI
AT27C1024-45VI
44J
Industrial
45
70
30
0.1
0.1
40P6
40V(1)
(-40°C to 85°C)
AT27C1024-70JI
AT27C1024-70PI
AT27C1024-70VI
44J
Industrial
30
40P6
40V(1)
(-40°C to 85°C)
Note:
Not recommended for new designs. Use Green package option.
19.2 Green Package (Pb/Halide-free)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
AT27C1024-45JU
AT27C1024-45PU
44J
Industrial
45
70
30
0.1
0.1
40P6
(-40°C to 85°C)
AT27C1024-70JU
AT27C1024-70PU
44J
Industrial
30
40P6
(-40°C to 85°C)
Note:
1. The 40-lead VSOP package is not recommended for new designs.
Package Type
44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
44J
40P6
40V
40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
40-Lead, Plastic Thin Small Outline Package (VSOP) 10 x 14 mm
10
AT27C1024
0019M–EPROM–12/07
AT27C1024
20. Packaging Information
20.1 44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
44J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
11
0019M–EPROM–12/07
20.2 40P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
52.070
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
52.578 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
40P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
12
AT27C1024
0019M–EPROM–12/07
AT27C1024
20.3 40V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
14.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
13.80
12.30
9.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation CA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
14.00
12.40
10.00
0.60
D1
E
12.50 Note 2
10.10 Note 2
0.70
L
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
40V
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
B
R
13
0019M–EPROM–12/07
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Sales Contact
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0019M–EPROM–12/07
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