AT27C512R_07 [ATMEL]
512K (64K x 8) OTP EPROM; 512K （ 64K ×8 ） OTP EPROM
| 型号： | AT27C512R_07 |
| 厂家： | 
ATMEL |
| 描述： | 512K (64K x 8) OTP EPROM |
| 文件： | 总15页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 45 ns
• Low-Power CMOS Operation
– 100 µA Max Standby
– 20 mA Max Active at 5 MHz
• JEDEC Standard Packages
– 28-lead PDIP
– 32-lead PLCC
– 28-lead TSOP and SOIC
512K (64K x 8)
OTP EPROM
• 5V 10% Supply
• High-Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Rapid Programming Algorithm – 100 µs/Byte (Typical)
• CMOS and TTL Compatible Inputs and Outputs
• Integrated Product Identification Code
• Industrial and Automotive Temperature Ranges
• Green (Pb/Halide-free) Packaging Option
AT27C512R
1. Description
The AT27C512R is a low-power, high-performance 524,288-bit one-time programma-
ble read-only memory (OTP EPROM) organized 64K by 8 bits. It requires only one 5V
power supply in normal read mode operation. Any byte can be accessed in less than
45 ns, eliminating the need for speed reducing WAIT states on high-performance
microprocessor systems.
Atmel’s scaled CMOS technology provides high-speed, lower active power consump-
tion, and significantly faster programming. Power consumption is typically only 8 mA
in Active Mode and less than 10 µA in Standby.
The AT27C512R is available in a choice of industry-standard JEDEC-approved one-
time programmable (OTP) plastic PDIP, PLCC, SOIC, and TSOP packages. All
devices feature two-line control (CE, OE) to give designers the flexibility to prevent
bus contention.
With 64K byte storage capability, the AT27C512R allows firmware to be stored reli-
ably and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C512R has additional features to ensure high quality and efficient pro-
duction use. The Rapid Programming Algorithm reduces the time required to program
the part and guarantees reliable programming. Programming time is typically only
100 µs/byte. The Integrated Product Identification Code electronically identifies the
device and manufacturer. This feature is used by industry-standard programming
equipment to select the proper programming algorithms and voltages.
0015O–EPROM–12/07
2. Pin Configurations
Pin Name
A0 - A15
O0 - O7
CE
Function
Addresses
Outputs
Chip Enable
OE/VPP
NC
Output Enable/ Program Supply
No Connect
2.1
28-lead PDIP/SOIC Top View
2.3
28-lead TSOP Top View – Type 1
A15
A12
A7
1
2
3
4
5
6
7
8
9
28 VCC
27 A14
26 A13
25 A8
OE/VPP
A11
A9
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A6
A8
A5
24 A9
A13
A14
VCC
A15
A12
A7
A4
23 A11
22 OE/VPP
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
A3
A2
8
A1
9
A0 10
O0 11
O1 12
O2 13
GND 14
10
11
12
13
14
A6
A5
A4
A1
A3
A2
2.2
32-lead PLCC Top View
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE/VPP
24 A10
23 CE
22 O7
21 O6
A1 10
A0 11
NC 12
O0 13
Note:
PLCC Package Pins 1 and 17 are Don’t Connect.
2
AT27C512R
0015O–EPROM–12/07
AT27C512R
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce tran-
sient voltage excursions. Unless accommodated by the system design, these transients may
exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high
frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the VCC and Ground terminals of the device, as close
to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit
boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again
connected between the VCC and Ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and func-
tional operation of the device at these or any other
conditions beyond those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias............................... -55°C to + 125°C
Storage Temperature.................................... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground ........................................-2.0V to + 7.0V(1)
Voltage on A9 with
Respect to Ground .....................................-2.0V to + 14.0V(1)
VPP Supply Voltage with
Respect to Ground ......................................-2.0V to + 14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V DC which may overshoot to +7.0 volts for pulses of less than 20 ns.
3
0015O–EPROM–12/07
6. Operating Modes
Mode/Pin
CE
VIL
VIL
VIH
VIL
VIH
OE/VPP
VIL
Ai
Ai
Outputs
DOUT
Read
Output Disable
Standby
VIH
X(1)
High Z
High Z
DIN
X(1)
X
Rapid Program(2)
VPP
Ai
PGM Inhibit
VPP
X(1)
High Z
(3)
A9 =VH
Product Identification(4)
VIL
VIL
A0 = VIH or VIL
A1 - A15 = VIL
Identification Code
Notes: 1. X can be VIL or VIH.
2. Refer to Programming Characteristics.
3. VH = 12.0 0.5V.
4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled
low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7. DC and AC Operating Conditions for Read Operation
AT27C512R
-45
-70
Ind.
-40°C - 85°C
-40°C - 85°C
-40°C - 125°C
5V 10%
Operating Temp.(Case)
CC Supply
Auto.
V
5V 10%
8. DC and Operating Characteristics for Read Operation
Symbol
Parameter
Condition
Min
Max
Units
µA
µA
µA
µA
µA
mA
mA
V
Ind.
1
ILI
Input Load Current
VIN = 0V to VCC
Auto.
Ind.
5
5
10
ILO
Output Leakage Current VOUT = 0V to VCC
Auto.
I
SB1 (CMOS), CE = VCC 0.3V
100
1
ISB
VCC(1) Standby Current
ISB2 (TTL), CE = 2.0 to VCC +0.5V
f = 5 MHz, IOUT = 0 mA, CE = VIL
ICC
VCC Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
20
VIL
-0.6
2.0
0.8
VIH
VOL
VOH
VCC + 0.5
0.4
V
IOL = 2.1 mA
IOH = -400 µA
V
2.4
V
Note:
1. VCC must be applied simultaneously with or before OE/VPP, and removed simultaneously with or after OE/VPP..
4
AT27C512R
0015O–EPROM–12/07
AT27C512R
9. AC Characteristics for Read Operation
AT27C512R
-45
-70
Symbol
Parameter
Condition
Min
Max
Min
Max
70
Units
ns
(1)
tACC
Address to Output Delay
CE to Output Delay
OE/VPP to Output Delay
CE = OE/VPP = VIL
OE/VPP = VIL
CE = VIL
45
45
20
20
(1)
tCE
70
ns
(1)
tOE
30
ns
(1)
tDF
OE/VPP or CE High to Output Float, Whichever Occurred First
25
ns
Output Hold from Address, CE or OE/VPP, Whichever Occurred
First
tOH
7
7
ns
Note:
1. See AC Waveforms for Read Operation.
10. AC Waveforms for Read Operation(1)
Notes: 1. Timing measurement reference level is 1.5V for -45 devices. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing mea-
surement reference levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V
and VIH = 2.4V.
2. OE/VPP may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
.
3. OE/VPP may be delayed up to tACC - tOE after the address is valid without impact on tACC
.
4. This parameter is only sampled and is not 100% tested.
5. Output float is defined as the point when data is no longer driven.
5
0015O–EPROM–12/07
11. Input Test Waveforms and Measurement Levels
For -45 devices only:
tR, tF < 5 ns (10% to 90%)
For -70 devices:
tR, tF < 20 ns (10% to 90%)
12. Output Test Load
Note:
1. CL = 100 pF including jig capacitance, except for the -45 devices, where CL = 30 pF.
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
6
AT27C512R
0015O–EPROM–12/07
AT27C512R
14. Programming Waveforms(1)
Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH.
2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer.
15. DC Programming Characteristics
TA = 25 5°C, VCC = 6.5 0.25V, OE/VPP = 13.0 0.25V
Limits
Symbol
ILI
Parameter
Test Conditions
Min
Max
10
Units
µA
V
Input Load Current
VIN = VIL,VIH
VIL
Input Low Level
-0.6
2.0
0.8
VIH
Input High Level
VCC + 1
0.4
V
VOL
VOH
ICC2
IPP2
VID
Output Low Voltage
Output High Voltage
VCC Supply Current (Program and Verify)
OE/VPP Current
IOL = 2.1 mA
IOH = -400 µA
V
2.4
V
25
25
mA
mA
V
CE = VIL
A9 Product Identification Voltage
11.5
12.5
7
0015O–EPROM–12/07
16. AC Programming Characteristics
TA = 25 5°C, VCC = 6.5 0.25V, OE/VPP = 13.0 0.25V
Limits
Symbol
tAS
Parameter
Test Conditions(1)
Min
2
Max
Units
µs
Address Setup Time
OE/VPP Setup Time
OE/VPP Hold Time
Data Setup Time
tOES
tOEH
tDS
2
µs
Input Rise and Fall Times
2
µs
(10% to 90%) 20 ns
2
µs
tAH
Address Hold Time
0
µs
Input Pulse Levels
tDH
Data Hold Time
2
µs
0.45V to 2.4V
tDFP
tVCS
tPW
CE High to Output Float Delay(2)
VCC Setup Time
0
130
ns
Input Timing Reference Level
0.8V to 2.0V
2
µs
CE Program Pulse Width(3)
Data Valid from CE(2)
OE/VPP Recovery Time
95
105
1
µs
Output Timing Reference Level
0.8V to 2.0V
tDV
µs
tVR
2
µs
OE/VPP Pulse Rise Time During
Programming
tPRT
50
ns
Notes: 1. VCC must be applied simultaneously or before OE/VPP and removed simultaneously or after OE/VPP.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven – see timing diagram.
3. Program Pulse width tolerance is 100 µsec 5%.
17. Atmel’s AT27C512R Integrated Product Identification Code
Pins
Hex
Codes
A0
0
O7
0
O6
0
O5
0
O4
1
O3
1
O2
1
O1
1
O0
0
Data
Manufacturer
Device Type
1E
1
0
0
0
0
1
1
0
1
0D
8
AT27C512R
0015O–EPROM–12/07
AT27C512R
18. RapidProgramming Algorithm
A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is
raised to 6.5V and OE/VPP is raised to 13.0V. Each address is first programmed with one
100 µs CE pulse without verification. Then a verification/reprogramming loop is executed for
each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses
are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have
been applied, the part is considered failed. After the byte verifies properly, the next address is
selected until all have been checked. OE/VPP is then lowered to VIL and VCC to 5.0V. All bytes
are read again and compared with the original data to determine if the device passes or fails.
9
0015O–EPROM–12/07
19. Ordering Information
19.1 Standard Package
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
45
20
0.1
AT27C512R-45JI
AT27C512R-45PI
AT27C512R-45RI
AT27C512R-45TI
32J
Industrial
28P6
28R(1)
28T
(-40°C to 85°C)
70
20
20
0.1
0.1
AT27C512R-70JI
AT27C512R-70PI
AT27C512R-70RI
AT27C512R-70TI
32J
Industrial
28P6
28R(1)
28T
(-40°C to 85°C)
AT27C512R-70JA
AT27C512R-70PA
AT27C512R-70RA
32J
Automotive
28P6
28R(1)
(-40°C to 125°C)
Note:
Not recommended for new designs. Use Green package option.
19.2 Green Package (Pb/Halide-free)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
45
20
0.1
AT27C512R-45JU
AT27C512R-45PU
AT27C512R-45RU
AT27C512R-45TU
32J
Industrial
28P6
28R(1)
28T
(-40°C to 85°C)
70
20
0.1
AT27C512R-70JU
AT27C512R-70PU
AT27C512R-70RU
AT27C512R-70TU
32J
Industrial
28P6
28R(1)
28T
(-40°C to 85°C)
Note:
1. The 28-pin SOIC package is not recommended for new designs.
Package Type
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32J
28P6
28R
28T
28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28-Lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC)
28-Lead, Thin Small Outline Package (TSOP)
10
AT27C512R
0015O–EPROM–12/07
AT27C512R
Packaging Information
19.3 32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
11
0015O–EPROM–12/07
19.4 28P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
36.703
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
37.338 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AB.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
28P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
12
AT27C512R
0015O–EPROM–12/07
AT27C512R
19.5 28R – SOIC
B
E
E
1
PIN 1
e
D
A
A
1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
2.39
MAX
2.79
NOM
NOTE
SYMBOL
0º ~ 8º
A
–
C
A1
D
E
0.050
18.00
11.70
8.59
–
0.356
18.50
12.50
8.79
–
Note 1
Note 1
L
–
E1
B
–
0.356
0.203
0.94
–
0.508
0.305
1.27
C
L
–
–
Note: 1. Dimensions D and E1 do not include mold Flash
or protrusion. Mold Flash or protrusion shall not exceed
0.25 mm (0.010").
e
1.27 TYP
5/18/2004
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
28R, 28-lead, 0.330" Body Width,
Plastic Gull Wing Small Outline (SOIC)
28R
R
C
13
0015O–EPROM–12/07
19.6 28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
28T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
C
R
14
AT27C512R
0015O–EPROM–12/07
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International
Atmel Corporation
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San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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0015O–EPROM–12/07
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