AT28C040-20FJ [ATMEL]
EEPROM, 512KX8, 200ns, Parallel, CMOS, CDFP32, CERAMIC, MO-115AA, FP-32;![AT28C040-20FJ](http://pdffile.icpdf.com/pdf2/p00239/img/icpdf/AT28C040-20L_1446545_icpdf.jpg)
型号: | AT28C040-20FJ |
厂家: | ![]() |
描述: | EEPROM, 512KX8, 200ns, Parallel, CMOS, CDFP32, CERAMIC, MO-115AA, FP-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 ATM 异步传输模式 CD 内存集成电路 |
文件: | 总15页 (文件大小:368K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
Features
• Read Access Time – 200 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 256 Bytes
– Internal Control Timer
• Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 256 Byte Page Write Operation
• Low Power Dissipation
4-Megabit
(512K x 8)
Paged Parallel
EEPROMs
– 50 mA Active Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
AT28C040
1. Description
The AT28C040 is a high-performance electrically erasable and programmable read-
only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 440 mW.
The AT28C040 is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 256-byte page register to allow
writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to
256 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by Data Polling of I/O7. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
Atmel's AT28C040 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra 256
bytes of EEPROM for device identification or tracking.
0542F–PEEPR–2/09
2.2
32-lead Flatpack – Top View
2. Pin Configurations
Pin Name
A0 - A18
CE
Function
A18
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 WE
30 A17
29 A14
28 A13
27 A8
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
A6
WE
A5
26 A9
I/O0 - I/O7
NC
A4
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A3
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
2.1
44-lead LCC – Top View
A12
A7
7
8
9
39 A13
38 A8
37 A9
36 A11
35 NC
34 NC
33 NC
32 NC
31 OE
30 A10
29 CE
A6
A5 10
NC 11
NC 12
NC 13
A4 14
A3 15
A2 16
A1 17
2
AT28C040
0542F–PEEPR–2/09
AT28C040
3. Block Diagram
4. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Temperature Under Bias................................ -55°C to +125°C
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
3
0542F–PEEPR–2/09
5. Device Operation
5.1
Read
The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
5.2
Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write
cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-
cally time itself to completion. Once a programming operation has been initiated and for the
duration of tWC, a read operation will effectively be a polling operation.
5.3
Page Write
The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 255 additional
bytes. Each successive byte must be written within 150 μs (tBLC) of the previous byte. If the tBLC
limit is exceeded, the AT28C040 will cease accepting data and commence the internal program-
ming operation. All bytes during a page write operation must reside on the same page as
defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page
write operation, A8 - A18 must be the same.
The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are spec-
ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.
5.4
5.5
5.6
Data Polling
Toggle Bit
The AT28C040 features Data Polling to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all
outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write
cycle.
In addition to Data Polling, the AT28C040 provides another method for determining the end of a
write cycle. During the write operation, successive attempts to read data from the device will
result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-
gling and valid data will be read. Reading the toggle bit may begin at any time during the write
cycle.
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel® has incorporated both hardware and software features that will protect the
memory against inadvertent writes.
4
AT28C040
0542F–PEEPR–2/09
AT28C040
5.6.1
5.6.2
Hardware Protection
Hardware features protect against inadvertent writes to the AT28C040 in the following ways:
(a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on
delay – once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before
allowing a write: (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
Software Data Protection
A software controlled data protection feature has been implemented on the AT28C040. When
enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP
feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP
disabled.
SDP is enabled when the host system issues a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be
protected against inadvertent write operations. It should be noted that once protected, the host
can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command
sequence used to enable SDP must precede the data to be written.
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device, and the
memory addresses used in the sequence may be written with data in either a byte or page write
operation.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
5.7
5.8
Device Identification
An extra 256 bytes of EEPROM memory are available to the user for device identification. By
raising A9 to 12V ± 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be writ-
ten to or read from in the same manner as the regular memory array.
Optional Chip Erase Mode
The entire device can be erased using a 6-byte software erase code. Please see Software Chip
Erase application note for details.
5
0542F–PEEPR–2/09
6. DC and AC Operating Range
AT28C040-20 Operation
Read
Program
-40°C - 85°C
-40°C - 85°C
5V ± 10%
Industrial
Operating Temperature (Case)
Extended
-40°C - 85°C
-55°C - 125°C
5V ± 10%
VCC Power Supply
7. Operating Modes
Mode
CE
VIL
VIL
X
OE
VIL
VIH
X
WE
VIH
VIL
VIH
X
I/O
Read
DOUT
DIN
Write(2)
Write Inhibit
Write Inhibit
Output Disable
Notes: 1. X can be VIL or VIH.
X
VIL
VIH
X
X
High Z
2. Refer to AC Programming Waveforms.
8. DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
ILI
Input Load Current
Output Leakage Current
VCC Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
µA
µA
mA
V
ILO
10
ICC
f = 5 MHz; IOUT = 0 mA
50
VIL
0.8
VIH
2.0
V
VOL
VOH1
VOH2
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
6
AT28C040
0542F–PEEPR–2/09
AT28C040
9. AC Read Characteristics
AT28C040-20
Symbol
Parameter
Min
Max
200
Units
ns
tACC
Address to Output Delay
CE to Output Delay
(1)
tCE
200
55
ns
(2)
tOE
OE to Output Delay
0
0
0
ns
(3)(4)
tDF
CE or OE to Output Float
Output Hold from OE, CE or Address, whichever occurred first
55
ns
tOH
ns
10. AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE May be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
11. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
10
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
0542F–PEEPR–2/09
14. AC Write Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
50
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
100
50
0
ns
tDS
ns
t
DH, tOEH
Data, OE Hold Time
ns
15. AC Write Waveforms
15.1 WE Controlled
15.2 CE Controlled
8
AT28C040
0542F–PEEPR–2/09
AT28C040
16. Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
tAS
0
50
50
0
tAH
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
ns
tBLC
tWPH
150
μs
50
ns
17. Page Mode Write Waveforms(1)(2)
Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
9
0542F–PEEPR–2/09
18. Software Data
19. Software Data
Protection Enable Algorithm(1)
Protection Disable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
LOAD DATA A0
TO
ADDRESS 5555
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA AA
TO
LOAD DATA XX
TO
ANY ADDRESS(4)
ADDRESS 5555
LOAD DATA 55
TO
LOAD LAST BYTE
TO
ADDRESS 2AAA
LAST ADDRESS
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
2. Write Protect state will be activated at end of write
even if no other data is loaded.
LOAD DATA XX
TO
ANY ADDRESS(4)
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 256 bytes of data are loaded.
LOAD LAST BYTE
TO
LAST ADDRESS
20. Software Protected Program Cycle Waveform(1)(2)(3)
Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must
be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
10
AT28C040
0542F–PEEPR–2/09
AT28C040
21. Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
22. Data Polling Waveforms
23. Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
24. Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
0542F–PEEPR–2/09
25. Ordering Information
25.1 Standard Packaging
I
CC (mA)
tACC
(ns)
Active
Ordering Code
AT28C040-20FI
Package
32F
Operation Range
Industrial
50
50
(-40° to 85°C)
AT28C040-20LI
44L
200
AT28C040-20FI SL703
AT28C040-20LI SL703
32F
Extended
(See DC and AC Operating Range Table)
44L
Note:
1. SL703 requires testing to Mil-883 standards; SL703 is marked on the package.
Package Type
32F
44L
32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
12
AT28C040
0542F–PEEPR–2/09
AT28C040
26. Packaging Information
26.1 32F – Flatpack
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
JEDEC Outline MO-115 AA
PIN #1 ID
9.40(0.370)
6.86(0.270)
0.51(0.020)
0.38(0.015)
21.08(0.830)
20.60(0.811)
1.27(0.050) BSC
1.14(0.045) MAX
12.40(0.488)
11.99(0.472)
3.05(0.120)
2.49(0.098)
0.18(0.007)
0.10(0.004)
10.36(0.408)
9.02(0.355)
1.14(0.045)
0.66(0.026)
1.83(0.072)
0.76(0.030)
10/21/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
32F, 32-lead, Non-windowed, Ceramic Bottom-brazed
Flat Package (FlatPack)
32F
B
R
13
0542F–PEEPR–2/09
26.2 44L – LCC
Dimensions in Millimeters and (Inches)
Controlling dimension: Inches
MIL-STD-1835 C-5
16.81(0.662)
16.26(0.640)
2.74(0.108)
2.16(0.085)
16.81(0.662)
16.26(0.640)
2.03(0.080)
1.40(0.055)
PIN 1
1.40(0.055)
1.14(0.045)
INDEX CORNER
2.41(0.095)
1.91(0.075)
0.635(0.025)
X 45˚
0.381(0.015)
0.305(0.012)
0.178(0.007)
RADIUS
12.70(0.500) BSC
0.737(0.029)
0.533(0.021)
1.27(0.050) TYP
1.02(0.040) X 45˚
2.16(0.085)
1.65(0.065)
12.70(0.500) BSC
04/11/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44L, 44-pad (0.600" Wide), Non-windowed, Ceramic Lid, Leadless
Chip Carrier (LCC)
44L
A
R
14
AT28C040
0542F–PEEPR–2/09
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Atmel Europe
Le Krebs
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
Hong Kong
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-en-
Yvelines Cedex
France
Tel: (852) 2245-6100
Fax: (852) 2722-1369
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
p_eeprom@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF
THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, and others are registered trademarks or trade-
marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
0542F–PEEPR–2/09
相关型号:
©2020 ICPDF网 联系我们和版权申明