AT28C64E-15PJ [ATMEL]
EEPROM, 8KX8, 150ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28;型号: | AT28C64E-15PJ |
厂家: | ATMEL |
描述: | EEPROM, 8KX8, 150ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
文件: | 总12页 (文件大小:318K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 120 ns
• Fast Byte Write – 200 µs or 1 ms
• Self-timed Byte Write Cycle
– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write
• Direct Microprocessor Control
– READY/BUSY Open Drain Output
– DATA Polling
• Low Power
64K (8K x 8)
Parallel
EEPROMs
– 30 mA Active Current
– 100 µA CMOS Standby Current
• High Reliability
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
• 5V 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Commercial and Industrial Temperature Ranges
AT28C64
AT28C64X
Description
The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile elec-
trically erasable and programmable read only memory with popular, easy-to-use fea-
tures. The device is manufactured with Atmel’s reliable nonvolatile technology.
(continued)
Pin Configurations
PDIP, SOIC
Top View
Pin Name
A0 - A12
CE
Function
RDY/BUSY (or NC)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
Addresses
A12
A7
2
3
Chip Enable
A6
4
A8
A5
5
A9
OE
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy Output
No Connect
A4
6
A11
OE
A3
7
A2
8
A10
CE
WE
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0 - I/O7
RDY/BUSY
NC
I/O0
I/O1
I/O2
GND
LCC, PLCC
Top View
DC
Don’t Connect
TSOP
Top View
OE
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
A11
2
A9
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
A8
4
28 A9
NC
5
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
WE
6
VCC
7
RDY/BUSY (or NC)
8
A1 10
A0 11
A12
A7
A6
A5
A4
A3
9
10
11
12
13
14
NC 12
I/O0 13
A1
A2
Rev. 0001H–12/99
Note: PLCC package pins 1 and 17 are
DON’T CONNECT.
The AT28C64 is accessed like a Static RAM for the read or
write cycles without the need for external components. Dur-
ing a byte write, the address and data are latched inter-
nally, freeing the microprocessor address and data bus for
other operations. Following the initiation of a write cycle,
the device will go to a busy state and automatically clear
and write the latched data using an internal control timer.
The device includes two methods for detecting the end of a
write cycle, level detection of RDY/BUSY (unless pin 1 is
N.C.) and DATA Polling of I/O7. Once the end of a write
cycle has been detected, a new access for a read or write
can begin.
The CMOS technology offers fast access times of 120 ns at
low power dissipation. When the chip is deselected the
standby current is less than 100 µA.
Atmel’s AT28C64 has additional features to ensure high
quality and manufacturability. The device utilizes error cor-
rection internally for extended endurance and for improved
data retention characteristics. An extra 32 bytes of
EEPROM are available for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground...................................-0.6V to +13.5V
AT28C64(X)
2
AT28C64(X)
Device Operation
READ: The AT28C64 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high
impedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
same RDY/BUSY line. The RDY/BUSY pin is not con-
nected for the AT28C64X.
DATA POLLING: The AT28C64 provides DATA Polling to
signal the completion of a write cycle. During a write cycle,
an attempted read of the data being written results in the
complement of that data for I/O7 (the other outputs are
indeterminate). When the write cycle is finished, true data
appears on all outputs.
BYTE WRITE: Writing data into the AT28C64 is similar to
writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) ini-
tiates a byte write. The address location is latched on the
falling edge of WE (or CE); the new data is latched on the
rising edge. Internally, the device performs a self-clear
before write. Once a byte write has been started, it will
automatically time itself to completion. Once a program-
ming operation has been initiated and for the duration of
tWC, a read operation will effectively be a polling operation.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways: (a) VCC sense –
if VCC is below 3.8V (typical) the write function is inhibited;
(b) VCC power on delay – once VCC has reached 3.8V the
device will automatically time out 5 ms (typical) before
allowing a byte write; and (c) write inhibit – holding any one
of OE low, CE high or WE high inhibits byte write cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C64 may be set to the high state by the CHIP CLEAR
operation. By setting CE low and OE to 12 volts, the chip is
cleared when a 10 msec low pulse is applied to WE.
FAST BYTE WRITE: The AT28C64E offers a byte write
time of 200 µs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
DEVICE IDENTIFICATION: An extra 32 bytes of
EEPROM memory are available to the user for device iden-
tification. By raising A9 to 12 0.5V and using address
locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
READY/BUSY: Pin 1 is an open drain RDY/BUSY output
that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and
is released at the completion of the write. The open drain
connection allows for OR-tying of several devices to the
3
DC and AC Operating Range
AT28C64-12
AT28C64-15
0°C - 70°C
-40°C - 85°C
5V 10%
AT28C64-20
0°C - 70°C
-40°C - 85°C
5V 10%
AT28C64-25
0°C - 70°C
-40°C - 85°C
5V 10%
Com.
Ind.
0°C - 70°C
-40°C - 85°C
5V 10%
Operating
Temperature (Case)
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
I/O
DOUT
DIN
Read
Write(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Chip Erase
High Z
VIH
X
X
VIL
VIH
X
X
High Z
High Z
(3)
VIL
VH
VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
100
2
Units
µA
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
ILO
µA
ISB1
CE = VCC - 0.3V to VCC + 1.0V
µA
Com.
Ind.
mA
mA
mA
mA
V
ISB2
VCC Standby Current TTL
VCC Active Current AC
CE = 2.0V to VCC + 1.0V
3
Com.
Ind.
30
45
0.8
f = 5 MHz; IOUT = 0 mA
CE = VIL
ICC
VIL
VIH
Input Low Voltage
Input High Voltage
2.0
2.4
V
IOL = 2.1 mA
VOL
VOH
Output Low Voltage
Output High Voltage
0.45
V
V
= 4.0 mA for RDY/BUSY
IOH = -400 µA
AT28C64(X)
4
AT28C64(X)
AC Read Characteristics
AT28C64-12
AT28C64-15
AT28C64-20
AT28C64-25
Symbol
Parameter
Min
Max
120
120
60
Min
Max
150
150
70
Min
Max
200
200
80
Min
Max
250
250
100
60
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE High to Output Float
(1)
tCE
ns
(2)
tOE
10
0
10
0
10
0
10
0
ns
(3)(4)
tDF
45
50
55
ns
Output Hold from OE, CE or
Address, whichever occurred first
tOH
0
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 20 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
Parameter
Min
10
50
100
50
10
0
Max
Units
ns
t
AS, tOES
Address, OE Setup Time
Address Hold Time
tAH
tWP
tDS
ns
Write Pulse Width (WE or CE)
Data Setup Time
1000
ns
ns
t
t
DH, tOEH
CS, tCH
Data, OE Hold Time
ns
CE to WE and WE to CE Setup and Hold Time
Time to Device Busy
ns
tDB
50
1
ns
AT28C64
AT28C64E
ms
µs
tWC
Write Cycle Time (option available)
200
AC Write Waveforms
WE Controlled
CE Controlled
AT28C64(X)
6
AT28C64(X)
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics”.
Data Polling Waveforms
Chip Erase Waveforms
tS = tH = 1 µsec (min.)
t
W = 10 msec (min.)
VH = 12.0 0.5V
7
AT28C64(X)
8
AT28C64(X)
AT28C64 Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
150
200
250
30
0.1
AT28C64(E)-12JC
AT28C64(E)-12PC
AT28C64(E)-12SC
AT28C64(E)-12TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
45
30
45
30
45
30
45
0.1
0.1
0.1
0.1
0.1
0.1
0.1
AT28C64(E)-12JI
AT28C64(E)-12PI
AT28C64(E)-12SI
AT28C64(E)-12TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
AT28C64(E)-15JC
AT28C64(E)-15PC
AT28C64(E)-15SC
AT28C64(E)-15TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64(E)-15JI
AT28C64(E)-15PI
AT28C64(E)-15SI
AT28C64(E)-15TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
AT28C64(E)-20JC
AT28C64(E)-20PC
AT28C64(E)-20SC
AT28C64(E)-20TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64(E)-20JI
AT28C64(E)-20PI
AT28C64(E)-20SI
AT28C64(E)-20TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
AT28C64(E)-25JC
AT28C64(E)-25PC
AT28C64(E)-25SC
AT28C64(E)-25TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64(E)-25JI
AT28C64(E)-25PI
AT28C64(E)-25SI
AT28C64(E)-25TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
Options
28P6
28S
28T
Blank
E
Standard Device: Endurance = 10K Write Cycles; Write Time = 1 ms
High Endurance Option: Endurance = 100K Write Cycles; Write Time = 200 µs
9
AT28C64X Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
150
200
250
30
0.1
AT28C64X-15JC
AT28C64X-15PC
AT28C64X-15SC
AT28C64X-15TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
45
30
45
30
45
0.1
0.1
0.1
0.1
0.1
AT28C64X-15JI
AT28C64X-15PI
AT28C64X-15SI
AT28C64X-15TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
AT28C64X-20JC
AT28C64X-20PC
AT28C64X-20SC
AT28C64X-20TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64X-20JI
AT28C64X-20PI
AT28C64X-20SI
AT28C64X-20TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
AT28C64X-25JC
AT28C64X-25PC
AT28C64X-25SC
AT28C64X-25TC
32J
Commercial
28P6
28S
28T
(0°C to 70°C)
AT28C64X-25JI
AT28C64X-25PI
AT28C64X-25SI
AT28C64X-25TI
32J
Industrial
28P6
28S
28T
(-40°C to 85°C)
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28C64 X
Speed
12
Package and Temperature Combinations
JC, JI, PC, PI, SC, SI, TC, TI
JC, JI, PC, PI, SC, SI, TC, TI
JC, JI, PC, PI, SC, SI, TC, TI
JC, JI, PC, PI, SC, SI, TC, TI
AT28C64 X
15
AT28C64 X
20
AT28C64 X
25
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type
32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
28P6
28S
28T
28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
AT28C64(X)
10
AT28C64(X)
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6, 28-lead, 0.600" Wide, Plastic Dual Inline
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
1.47(37.3)
1.44(36.6)
.025(.635) X 30˚ - 45˚
.045(1.14) X 45˚ PIN NO. 1
PIN
1
.012(.305)
.008(.203)
IDENTIFY
.530(13.5)
.490(12.4)
.566(14.4)
.530(13.5)
.553(14.0)
.547(13.9)
.595(15.1)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.585(14.9)
.090(2.29)
MAX
1.300(33.02) REF
.030(.762)
.220(5.59)
MAX
.050(1.27) TYP
.005(.127)
MIN
.300(7.62) REF
.430(10.9)
.390(9.90)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
SEATING
PLANE
AT CONTACT
POINTS
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
.022(.559) X 45˚ MAX (3X)
0
15
.453(11.5)
.447(11.4)
REF
.012(.305)
.008(.203)
.495(12.6)
.485(12.3)
.690(17.5)
.610(15.5)
28S, 28-lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
28T, 28-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
13.7 (0.539)
13.1 (0.516)
11.9 (0.469)
11.7 (0.461)
0.27 (0.011)
0.18 (0.007)
0.55 (0.022)
BSC
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.10 (0.004)
0
REF
5
0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
*Controlling dimension: millimeters
11
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© Atmel Corporation 1999.
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®
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Printed on recycled paper.
0001H–12/99/xM
相关型号:
AT28C64E-15PL
EEPROM, 8KX8, 150ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28
ATMEL
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