AT28HC64B-90JI [ATMEL]
64K 8K x 8 High Speed CMOS E2PROM with Page Write and Software Data Protection; 64K 8K ×8高速CMOS E2PROM与页写入和软件数据保护
| 型号： | AT28HC64B-90JI |
| 厂家： | 
ATMEL |
| 描述： | 64K 8K x 8 High Speed CMOS E2PROM with Page Write and Software Data Protection |
| 文件： | 总12页 (文件大小：664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT28HC64B
Features
Fast Read Access Time - 55 ns
Automatic Page Write Operation
•
•
Internal Address and Data Latches for 64-Bytes
Fast Write Cycle Times
•
Page Write Cycle Time: 10 ms Maximum
1 to 64-Byte Page Write Operation
Low Power Dissipation
•
40 mA Active Current
100 µA CMOS Standby Current
64K (8K x 8)
High Speed
CMOS
Hardware and Software Data Protection
DATA Polling and Toggle Bit for End of Write Detection
High Reliability CMOS Technology
Endurance: 100,000 Cycles
Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
•
•
•
•
E2PROM with
Page Write and
Software Data
Protection
•
•
Commercial and Industrial Temperature Ranges
•
Description
The AT28HC64B is a high-performance electrically erasable and programmable read
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 55 ns with power dissipation of just 220 mW. When the device is
deselected, the CMOS standby current is less than 100 µA.
The AT28HC64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
(continued)
Pin Configurations
Pin Name
A0 - A12
CE
Function
TSOP
Top View
AT28HC64B
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
DC
Don’t Connect
PLCC
Top View
PDIP, SOIC
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
0274D
2-267
Description (Continued)
writing of up to 64-bytes simultaneously. During a write cy-
cle, the addresses and 1 to 64-bytes of data are internally
latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device
will automatically write the latched data using an internal
control timer. The end of a write cycle can be detected by
DATA Polling of I/O7. Once the end of a write cycle has
been detected, a new access for a read or write can begin.
Atmel’s AT28HC64B has additional features to ensure
high quality and manufacturability. The device utilizes in-
ternal error correction for extended endurance and im-
proved data retention. An optional software data protec-
tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 64-bytes of
EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V + 0.6V
CC
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-268
AT28HC64B
AT28HC64B
Device Operation
READ: The AT28HC64B is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high-
impedance state when either CE or OE is high. This dual
line control gives designers flexibility in preventing bus
contention in their systems.
read. Toggle bit reading may begin at any time during the
write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write has been
started, it will automatically time itself to completion. Once
a programming operation has been initiated and for the
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent writes to the AT28HC64B in
the following ways: (a) V
sense - if V
is below 3.8V
CC
CC
(typical), the write function is inhibited; (b) V power-on
CC
delay - once V has reached 3.8V, the device will auto-
CC
matically time out 5 ms (typical) before allowing a write; (c)
write inhibit - holding any one of OE low, CE high or WE
high inhibits write cycles; (d) noise filter - pulses of less
than 15 ns (typical) on the WE or CE inputs will not initiate
a write cycle.
duration of t , a read operation will effectively be a poll-
WC
ing operation.
PAGE WRITE: The page write operation of the
AT28HC64B allows 1 to 64-bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; after the first byte is written, it can then be fol-
lowed by 1 to 63 additional bytes. Each successive byte
SOFTWARE DATA PROTECTION: A software-control-
led data protection feature has been implemented on the
AT28HC64B. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28HC64B
is shipped from Atmel with SDP disabled.
must be loaded within 150 µs (t
) of the previous byte.
BLC
If the t
limit is exceeded, the AT28HC64B will cease
BLC
SDP is enabled by the user issuing a series of three write
commands in which three specific bytes of data are written
to three specific addresses (refer to the Software Data
Protection Algorithm diagram in this data sheet). After writ-
accepting data and commence the internal programming
operation. All bytes during a page write operation must re-
side on the same page as defined by the state of the A6 to
A12 inputs. For each WE high to low transition during the
page write operation, A6 to A12 must be the same.
ing the 3-byte command sequence and waiting t , the
WC
entire AT28HC64B will be protected against inadvertent
writes. It should be noted that even after SDP is enabled,
the user may still perform a byte or page write to the
AT28HC64B. This is done by preceding the data to be
written by the same 3-byte command sequence used to
enable SDP.
The A0 to A5 inputs specify which bytes within the page
are to be written. The bytes may be loaded in any order
and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnec-
essary cycling of other bytes within the page does not oc-
cur.
Once set, SDP remains active unless the disable com-
mand sequence is issued. Power transitions do not dis-
able SDP, and SDP protects the AT28HC64B during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifica-
tions. The data in the enable and disable command se-
quences is not actually written into the device; their ad-
dresses may still be written with user data in either a byte
or page write operation.
DATA POLLING: The AT28HC64B features DATA Poll-
ing to indicate the end of a write cycle. During a byte or
page write cycle, an attempted read of the last byte written
will result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at any time during the
write cycle.
TOGGLE BIT: I n a d d i t i o n t o DATA Polling, the
AT28HC64B provides another method for determining the
end of a write cycle. During the write operation, succes-
sive attempts to read data from the device will result in
I/O6 toggling between one and zero. Once the write has
completed, I/O6 will stop toggling, and valid data will be
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device, however.
For the duration of t , read operations will effectively be
WC
polling operations.
(continued)
2-269
Device Operation (Continued)
DEVICE IDENTIFICATION: An extra 64-bytes of
EEPROM memory are available to the user for device
identification. By raising A9 to 12V ± 0.5V and using ad-
dress locations 1FC0H to 1FFFH, the additional bytes
may be written to or read from in the same manner as the
regular memory array.
DC and AC Operating Range
AT28HC64B-55
AT28HC64B-70
0°C - 70°C
AT28HC64B-90
0°C - 70°C
AT28HC64B-120
0°C - 70°C
Com.
Ind.
0°C - 70°C
Operating
Temperature (Case)
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
V
Power Supply
5V ± 10%
CC
Operating Modes
Mode
CE
OE
WE
I/O
Read
V
V
V
V
D
D
IL
IL
IH
IL
IH
OUT
IN
(2)
Write
V
V
IH
IL
(1)
Standby/Write Inhibit
Write Inhibit
V
X
X
High Z
X
X
V
IH
Write Inhibit
X
X
V
X
IL
Output Disable
Chip Erase
V
X
High Z
High Z
IH
(3)
V
V
V
IL
IL
H
Notes: 1. X can be VIL or VIH.
3. VH = 12.0V ± 0.5V.
2. Refer to the AC Write Waveforms diagrams
in this data sheet.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
mA
mA
V
I
I
I
I
I
Input Load Current
Output Leakage Current
V
V
= 0V to V + 1V
CC
LI
IN
= 0V to V
CC
10
LO
I/O
(1)
V
V
V
Standby Current CMOS CE = V - 0.3V to V + 1V Com., Ind.
100
SB1
SB2
CC
CC
CC
CC
CC
CC
(1)
Standby Current TTL
Active Current
CE = 2.0V to V + 1V
2
CC
f = 5 MHz; I
= 0 mA
40
OUT
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.8
IL
2.0
2.4
V
IH
I
I
= 2.1 mA
.40
V
OL
OH
OL
= -400 µA
V
OH
Note: 1. ISB1 and ISB2 for the 55 ns part is 40 mA maximum.
2-270
AT28HC64B
AT28HC64B
AC Read Characteristics
AT28HC64B-55 AT28HC64B-70 AT28HC64B-90 AT28HC64B-120
Min
Max
55
55
30
30
Min
Max
70
70
35
35
Min
Max
90
90
40
40
Min
Max
120
120
50
Symbol Parameter
Units
ns
t
t
t
t
t
Address to Output Delay
CE to Output Delay
OE to Output Delay
OE to Output Float
Output Hold
ACC
(1)
ns
CE
OE
DF
OH
(2)
0
0
0
0
0
0
0
0
0
0
0
0
ns
(3, 4)
50
ns
ns
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE, whichever occurs first
(CL = 5 pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Output Test Load
Input Test Waveforms and
Measurement Level
t , t < 5ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
2-271
AC Write Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
AS OES
50
0
ns
AH
CS
CH
WP
DS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
100
50
0
ns
ns
, t
Data, OE Hold Time
ns
DH OEH
AC Write Waveforms
WE Controlled
CE Controlled
2-272
AT28HC64B
AT28HC64B
Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
t
t
t
t
t
t
t
t
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
ms
ns
ns
ns
ns
ns
µs
ns
WC
0
50
50
0
AS
AH
DS
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
WP
BLC
WPH
150
50
Page Mode Write Waveforms (1, 2)
Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
Chip Erase Waveforms
tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V ± 0.5V
2-273
Software Data
Software Data
Protection Disable Algorithm (1)
Protection Enable Algorithm (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 1555
ADDRESS 1555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 0AAA
ADDRESS 0AAA
LOAD DATA 80
TO
ADDRESS 1555
LOAD DATA A0
TO
ADDRESS 1555
WRITES ENABLED (2)
LOAD DATA AA
TO
ADDRESS 1555
LOAD DATA XX
TO
ANY ADDRESS (4)
LOAD DATA 55
TO
ADDRESS 0AAA
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
ADDRESS 1555
EXIT DATA
PROTECT STATE (3)
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A12 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no
other data is loaded.
LOAD DATA XX
TO
ANY ADDRESS (4)
3. Write Protect state will be deactivated at end of write period
even if no other data is loaded.
4. 1 to 64-bytes of data are loaded.
LOAD LAST BYTE
TO
LAST ADDRESS
Software Protected Write Cycle Waveforms (1, 2)
Notes: 1. A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after
the software code has been entered.
2. OE must be high only when WE and CE are both low.
2-274
AT28HC64B
AT28HC64B
Data Polling Characteristics (1)
Symbol
Parameter
Min
0
Typ
Max
Units
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
ns
ns
ns
ns
DH
0
OEH
OE
(2)
Write Recovery Time
0
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms (1, 2, 3)
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
3. Any address location may be used, but the
address should not vary.
2. Beginning and ending state of I/O6 will vary.
2-275
2-276
AT28HC64B
AT28HC64B
Ordering Information (1)
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
Active Standby
(ns)
55
40
40
0.1
AT28HC64B-55JC
AT28HC64B-55PC
AT28HC64B-55SC
32J
28P6
28S
Commercial
(0°C to 70°C)
70
0.1
AT28HC64B-70JC
AT28HC64B-70PC
AT28HC64B-70SC
AT28HC64B-70TC
32J
Commercial
(0°C to 70°C)
28P6
28S
28T
40
40
40
40
40
0.1
0.1
0.1
0.1
0.1
AT28HC64B-70JI
AT28HC64B-70PI
AT28HC64B-70SI
AT28HC64B-70TI
32J
Industrial
(-40°C to 85°C)
28P6
28S
28T
90
AT28HC64B-90JC
AT28HC64B-90PC
AT28HC64B-90SC
AT28HC64B-90TC
32J
Commercial
(0°C to 70°C)
28P6
28S
28T
AT28HC64B-90JI
AT28HC64B-90PI
AT28HC64B-90SI
AT28HC64B-90TI
32J
Industrial
(-40°C to 85°C)
28P6
28S
28T
120
AT28HC64B-12JC
AT28HC64B-12PC
AT28HC64B-12SC
AT28HC64B-12TC
32J
Commercial
(0°C to 70°C)
28P6
28S
28T
AT28HC64B-12JI
AT28HC64B-12PI
AT28HC64B-12SI
AT28HC64B-12TI
32J
Industrial
(-40°C to 85°C)
28P6
28S
28T
Note: 1. See Valid Part Number table below.
2-277
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28HC64B
AT28HC64B
AT28HC64B
AT28HC64B
Speed
Package and Temperature Combinations
PC, SC
55
70
90
12
JI, PC, PI, SC, SI, TC, TI
JI, PC, PI, SC, SI, TC, TI
JI, PC, PI, SC, SI, TC, TI
Package Type
32J
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
28P6
28S
28T
28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28 Lead, Plastic Thin Small Outline Package (TSOP)
2-278
AT28HC64B
相关型号：
AT28HC64B-90JU
64K (8K x 8) High-speed Parallel EEPROM with Page Write and Software Data Protection
ATMEL
AT28HC64B-90PL
EEPROM, 8KX8, 90ns, Parallel, CMOS, PDIP28, 0.600 INCH, PLASTIC, MS-011AB, DIP-28
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