AT28LV256-25 [ATMEL]
256K 32K x 8 Low Voltage CMOS E2PROM; 256K 32K ×8低电压CMOS E2PROM
| 型号： | AT28LV256-25 |
| 厂家： | 
ATMEL |
| 描述： | 256K 32K x 8 Low Voltage CMOS E2PROM |
| 文件： | 总10页 (文件大小：605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT28LV256
Features
Fast Read Access Time - 200 ns
Automatic Page Write Operation
•
•
Internal Address and Data Latches for 64-Bytes
Internal Control Timer
Fast Write Cycle Times
•
Page Write Cycle Time: 10 ms Maximum
1 to 64-Byte Page Write Operation
Low Power Dissipation
•
15 mA Active Current
256K (32K x 8)
Low Voltage
CMOS
20 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 10,000 Cycles
Data Retention: 10 Years
Single 3.3V ± 5% Supply
JEDEC Approved Byte-Wide Pinout
Commercial and Industrial Temperature Ranges
•
•
•
E2PROM
•
•
•
Description
The AT28LV256 is a high-performance Electrically Erasable and Programmable
Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 200 µA.
The AT28LV256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64-bytes simultaneously. During a write cycle, the addresses and 1 to
(continued)
Pin Configurations
AT28LV256
PDIP, SOIC
Top View
Pin Name
A0 - A14
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
DC
Don’t Connect
PLCC
Top View
TSOP
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
0273E
2-145
Description (Continued)
64-bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a
write cycle can be detected by DATA polling of I/O7. Once
the end of a write cycle has been detected a new access
for a read or write can begin.
Atmel’s 28LV256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. An optional software data
protection mechanism is available to guard against inad-
vertent writes. The device also includes an extra 64-bytes
2
of E PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V + 0.6V
CC
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-146
AT28LV256
AT28LV256
Device Operation
READ: The AT28LV256 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28LV256 in the follow-
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cy-
cle. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first
rising edge of CE or WE. Once a byte write has been
started it will automatically time itself to completion. Once
a programming operation has been initiated and for the
ing ways: (a) V power-on delay - once V has reached
CC CC
1.8V (typical) the device will automatically time out 10 ms
(typical) before allowing a write: (b) write inhibit - holding
any one of OE low, CE high or WE high inhibits write cy-
cles; (c) noise filter - pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software-control-
led data protection feature has been implemented on the
AT28LV256. Software data protection (SDP) helps pre-
vent inadvertent writes from corrupting the data in the de-
vice. SDP can prevent inadvertent writes during power-up
and power-down as well as any other potential periods of
system instability.
duration of t , a read operation will effectively be a poll-
WC
ing operation.
PAGE WRITE: The page write operation of the
AT28LV256 allows 1 to 64-bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1
to 63 additional bytes. Each successive byte must be writ-
The AT28LV256 can only be written using the software
data protection feature. A series of three write commands
to specific addresses with specific data must be presented
to the device before writing in the byte or page mode. The
same three write commands must begin each write opera-
tion. All software write commands must obey the page
mode write timing specifications. The data in the 3-byte
command sequence is not written to the device; the ad-
dress in the command sequence can be utilized just like
any other location in the device.
ten within 150 µs (t
) of the previous byte. If the t
BLC
BLC
limit is exceeded the AT28LV256 will cease accepting
data and commence the internal programming operation.
All bytes during a page write operation must reside on the
same page as defined by the state of the A6 - A14 inputs.
For each WE high to low transition during the page write
operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
Any attempt to write to the device without the 3-byte se-
quence will start the internal write timers. No data will be
written to the device; however, for the duration of t
read operations will effectively be polling operations.
,
WC
DEVICE IDENTIFICATION: An extra 64-bytes of
DATA POLLING: The AT28LV256 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
2
E PROM memory are available to the user for device
identification. By raising A9 to 12V ± 0.5V and using ad-
dress locations 7FC0H to 7FFFH the additional bytes may
be written to or read from in the same manner as the regu-
lar memory array.
TOGGLE BIT: In addition to DATA Polling the AT28LV256
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
2-147
DC and AC Operating Range
AT28LV256-20
0°C - 70°C
AT28LV256-25
0°C - 70°C
Com.
Ind.
Operating
Temperature (Case)
-40°C - 85°C
3.3V ± 5%
-40°C - 85°C
3.3V ± 5%
V
Power Supply
CC
Operating Modes
Mode
CE
OE
WE
I/O
Read
V
V
V
V
D
D
IL
IL
IH
IL
IH
OUT
IN
(2)
Write
V
V
IH
IL
(1)
Standby/Write Inhibit
Write Inhibit
V
X
X
High Z
X
X
V
IH
Write Inhibit
X
X
V
X
IL
Output Disable
V
X
High Z
High Z
IH
(3)
Chip Erase
V
V
V
IL
IL
H
3. VH = 12.0V ± 0.5V.
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
V
I
I
Input Load Current
Output Leakage Current
V
V
= 0V to V + 1V
CC
LI
IN
= 0V to V
CC
10
LO
I/O
Com.
Ind.
20
I
SB
V
Standby Current CMOS
CE = V - 0.3V to V + 1V
CC CC
CC
50
I
V
Active Current
f = 5 MHz; I
= 0 mA
15
CC
CC
OUT
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.6
IL
2.0
2.0
V
IH
I
I
= 1.6 mA
0.3
V
OL
OH
OL
= -100 µA
V
OH
2-148
AT28LV256
AT28LV256
AC Read Characteristics
AT28LV256-20
AT28LV256-25
Min
Max
Min
Max
250
250
100
60
Symbol Parameter
Units
ns
t
t
t
t
Address to Output Delay
CE to Output Delay
200
200
80
ACC
(1)
ns
CE
OE
DF
(2)
OE to Output Delay
0
0
0
0
ns
(3, 4)
CE or OE to Output Float
55
ns
Output Hold from OE, CE or
Address, whichever occurred first
t
0
0
ns
OH
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Output Test Load
Input Test Waveforms and
Measurement Level
t , t < 20 ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
2-149
AC Write Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
AS OES
50
0
ns
AH
CS
CH
WP
DS
ns
0
ns
200
50
0
ns
ns
, t
Data, OE Hold Time
Time to Data Valid
ns
DH OEH
(1)
NR
DV
Note: 1. NR = No Restriction
AC Write Waveforms
WE Controlled
CE Controlled
2-150
AT28LV256
AT28LV256
Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
t
t
t
t
t
t
t
t
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
ms
ns
ns
ns
ns
ns
µs
ns
WC
0
50
50
0
AS
AH
DS
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
200
WP
BLC
WPH
150
100
Programming Algorithm
LOAD DATA AA
TO
ADDRESS 5555
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data protect state will be re-activated at the end of program
LOAD DATA 55
TO
ADDRESS 2AAA
cycle.
3. 1 to 64-bytes of data are loaded.
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED (2)
LOAD DATA XX
TO
ANY ADDRESS (3)
LOAD LAST BYTE
TO
LAST ADDRESS (3)
ENTER DATA
PROTECT STATE
Software Protected Write Cycle Waveforms (1, 2, 3)
2. A6 through A14 must specify the same page address during
Notes: 1. A0 - A14 must conform to the addressing sequence for
the first three bytes as shown above.
each high to low transition of WE (or CE) after the software
code has been entered.
3. OE must be high only when WE and CE are both low.
2-151
Data Polling Characteristics (1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
DH
0
ns
OEH
OE
(2)
ns
Write Recovery Time
0
ns
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
3. Any address location may be used but the
address should not vary.
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
2-152
AT28LV256
AT28LV256
2-153
Ordering Information (1)
t
I
(mA)
ACC
CC
Ordering Code
Package
Operation Range
Active Standby
(ns)
200
80
80
80
80
0.2
0.2
0.2
0.2
AT28LV256-20JC
AT28LV256-20PC
AT28LV256-20SC
AT28LV256-20TC
32J
Commercial
(0°C to 70°C)
28P6
28S
28T
AT28LV256-20JI
AT28LV256-20PI
AT28LV256-20SI
AT28LV256-20TI
32J
Industrial
(-40°C to 85°C)
28P6
28S
28T
250
AT28LV256-25JC
AT28LV256-25PC
AT28LV256-25SC
AT28LV256-25TC
32J
Commercial
(0°C to 70°C)
28P6
28S
28T
AT28LV256-25JI
AT28LV256-25PI
AT28LV256-25SI
AT28LV256-25TI
32J
Industrial
(-40°C to 85°C)
28P6
28S
28T
Note: 1. See Valid Part Number table below.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28LV256
Speed
Package and Temperature Combinations
JC, JI, PC, PI, SC, SI, TC, TI
20
25
AT28LV256
JC, JI, PC, PI, SC, SI, TC, TI
Package Type
32J
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
28P6
28S
28T
28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28 Lead, Plastic Thin Small Outline Package (TSOP)
2-154
AT28LV256
相关型号：
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