AT29C256-70 [ATMEL]
256K 32K x 8 5-volt Only CMOS Flash Memory; 256K 32K ×8 5伏只有CMOS闪存
| 型号： | AT29C256-70 |
| 厂家： | 
ATMEL |
| 描述： | 256K 32K x 8 5-volt Only CMOS Flash Memory |
| 文件： | 总17页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time – 70 ns
• 5-volt Only Reprogramming
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– Internal Address and Data Latches for 64 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Program Cycle Times
– Page (64 Byte) Program Time – 10 ms
– Chip Erase Time – 10 ms
• DATA Polling for End of Program Detection
256K (32K x 8)
5-volt Only
Flash Memory
• Low-power Dissipation
– 50 mA Active Current
– 300 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles
• Single 5V 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
AT29C256
Description
The AT29C256 is a five-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW. When the device is
deselected, the CMOS standby current is less than 300 µA. The device endurance is
such that any sector can typically be written to in excess of 10,000 times.
TSOP Top View
Pin Configurations
Type 1
Pin Name
A0 - A14
CE
Function
Addresses
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A8
OE
A13
A14
VCC
WE
A12
A7
WE
I/O0 - I/O7
NC
2
3
A6
4
A5
5
A4
6
A1
DC
Don’t Connect
A3
7
8
A2
PLCC and LCC Top View
A6
A5
A4
A3
A2
5
6
7
8
9
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
A1 10
A0 11
NC 12
I/O0 13
Note:
PLCC package pins 1 and 17 are
DON’T CONNECT.
Rev. 0046P–FLASH–10/04
To allow for simple in-system reprogrammability, the AT29C256 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C256 is performed on a page basis; 64 bytes of data are
loaded into the device and then simultaneously programmed. The contents of the entire
device may be erased by using a six-byte software code (although erasure before pro-
gramming is not needed).
During a reprogram cycle, the address locations and 64 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle has been detected a new
access for a read, program or chip erase can begin.
Block Diagram
Device Operation
READ: The AT29C256 is accessed like a static RAM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
BYTE LOAD: A byte load is performed by applying a low pulse on the WE or CE input
with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the
software codes for data protection and chip erasure.
2
AT29C256
0046P–FLASH–10/04
AT29C256
PROGRAM: The device is reprogrammed on a page basis. If a byte of data within a
page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded during the programming of its page will be indeterminate. Once the
bytes of a page are loaded into the device, they are simultaneously programmed during
the internal programming period. After the first data byte has been loaded into the
device, successive bytes are entered in the same manner. Each new byte to be pro-
grammed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to-
high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not
detected within 150 µs of the last low-to-high transition, the load period will end and the
internal programming period will start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify
the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has been initiated, and for the
duration of tWC, a read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION: A software controlled data protection feature is
available on the AT29C256. Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the page program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft-
ware feature will guard against inadvertent program cycles during power transitions.
Once set, software data protection will remain active unless the disable command
sequence is issued.
After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of tWC, a read operation will effectively be a polling operation.
After the software data protection’s three-byte command code is given, a byte load is
performed by applying a low pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of
data must be loaded into each sector by the same procedure as outlined in the program
section under device operation.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent
programs to the AT29C256 in the following ways: (a) VCC sense – if VCC is below 3.8V
(typical), the program function is inhibited; (b) VCC power on delay – once VCC has
reached the VCC sense level, the device will automatically time out 5 ms (typical) before
programming; (c) Program inhibit – holding any one of OE low, CE high or WE high
inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
3
0046P–FLASH–10/04
PRODUCT IDENTIFICATION: The product identification mode identifies the device
and manufacturer and may be accessed by a hardware operation. For details, see
Operating Modes or Product Identification.
DATA POLLING: The AT29C256 features DATA polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT29C256 provides another method for
determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
cycle.
OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a six-byte
software code. Please see Software Chip Erase application note for details.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
4
AT29C256
0046P–FLASH–10/04
AT29C256
DC and AC Operating Range
AT29C256-70
0°C - 70°C
-40°C - 85°C
5V 5%
AT29C256-90
0°C - 70°C
-40°C - 85°C
5V 10%
AT29C256-12
0°C - 70°C
-40°C - 85°C
5V 10%
AT29C256-15
0°C - 70°C
-40°C - 85°C
5V 10%
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Note:
Not recommended for New Designs.
Operating Modes
Mode
CE
VIL
VIL
VIL
VIH
X
OE
VIL
VIH
VIH
X(1)
X
WE
VIH
VIL
VIL
X
Ai
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
5V Chip Erase
Standby/Write Inhibit
Write Inhibit
High Z
VIH
X
Write Inhibit
X
VIL
VIH
Output Disable
High Voltage Chip Erase
Product Identification
X
X
High Z
High Z
(3)
VIL
VH
VIL
X
VIL
VIL
VIH
A1-A14 = VIL, A9 = VH, A0 = VIL
Manufacturer Code(4)
Hardware
A1-A14 = VIL, A9 = VH, A0 = VIH Device Code(4)
A0 = VIL
A0 = VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1F, Device Code: DC.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
ILI
Input Load Current
VIN = 0V to VCC
µA
µA
µA
mA
mA
V
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
VI/O = 0V to VCC
10
ISB1
ISB2
ICC
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
300
3
50
VIL
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
5
0046P–FLASH–10/04
AC Read Characteristics
AT29C256-70
AT29C256-90
AT29C256-12
AT29C256-15
Symbol
Parameter
Min
Max
70
Min
Max
90
Min
Max
120
120
50
Min
Max
150
150
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
70
90
ns
(2)
tOE
0
0
0
40
0
0
0
40
0
0
0
0
0
0
ns
(3)(4)
tDF
25
25
30
40
ns
Output Hold from OE, CE or Address,
whichever occurred first
ns
tOH
Note:
Not recommended for New Designs.
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT29C256
0046P–FLASH–10/04
AT29C256
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
0046P–FLASH–10/04
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
35
0
ns
ns
t
DH,tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
100
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
8
AT29C256
0046P–FLASH–10/04
AT29C256
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
tAS
0
tAH
50
35
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
90
ns
tBLC
tWPH
150
µs
100
ns
Program Cycle Waveforms(1)(2)(3)
Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being programmed will be indeterminate.
9
0046P–FLASH–10/04
Software Data Protection
Enable Algorithm(1)
Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA A0
TO
LOAD DATA 80
TO
ADDRESS 5555
WRITES ENABLED(2)
ADDRESS 5555
LOAD DATA
TO
PAGE (64 BYTES)(4)
LOAD DATA AA
TO
ENTER DATA
PROTECT STATE
ADDRESS 5555
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data Protect state will be re-activated at end of pro-
gram cycle.
LOAD DATA 55
TO
ADDRESS 2AAA
3. Data Protect state will be deactivated at end of pro-
gram period.
4. 64 bytes of data MUST BE loaded.
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA
TO
PAGE (64 BYTES)(4)
Software Protected Program Cycle Waveform(1)(2)(3)
Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE) after the software code has
been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being programmed will be indeterminate.
10
AT29C256
0046P–FLASH–10/04
AT29C256
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
0046P–FLASH–10/04
Software Product Identification Entry(1)
Software Product Identification Exit(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA F0
TO
ADDRESS 5555
ADDRESS 5555
PAUSE 10 mS
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A14 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is DC.
12
AT29C256
0046P–FLASH–10/04
AT29C256
NORMALIZED SUPPLY CURRENT
vs.TEMPERATURE
1.4
1.3
1.2
1.1
1.0
0.9
0.8
N
O
R
M
A
L
I
Z
E
D
I
C
C
-55
-25
5
35
65
95
125
TEMPERATURE (C)
NORMALIZED SUPPLY CURRENT
vs. ADDRESS FREQUENCY
1.1
1.0
0.9
0.8
0.7
N
O
R
M
A
L
I
Z
E
D
V
CC = 5V
T = 25C
I
C
C
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
1.0
N
O
R
M
A
L
I
Z
E
D
0.8
0.6
I
C
C
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
13
0046P–FLASH–10/04
Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
50
0.3
AT29C256-70JC
AT29C256-70TC
32J
28T
Commercial
(0° to 70°C)
AT29C256-70JI
AT29C256-70TI
32J
28T
Industrial
(-40° to 85°C)
90
50
50
50
0.3
0.3
0.3
AT29C256-90JC
AT29C256-90TC
32J
28T
Commercial
(0° to 70°C)
AT29C256-90JI
AT29C256-90TI
32J
28T
Industrial
(-40° to 85°C)
120
150
AT29C256-12JC
AT29C256-12TC
32J
28T
Commercial
(0° to 70°C)
AT29C256-12JI
AT29C256-12TI
32J
28T
Industrial
(-40° to 85°C)
AT29C256-15JC
AT29C256-15TC
32J
28T
Commercial
(0° to 70°C)
AT29C256-15JI
AT29C256-15TI
32J
28T
Industrial
(-40° to 85°C)
Note:
Not recommended for New Designs.
Package Type
32J
28T
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
28-lead, Plastic Thin Small Outline Package (TSOP)
14
AT29C256
0046P–FLASH–10/04
AT29C256
Packaging Information
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
15
0046P–FLASH–10/04
28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
28T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
C
R
16
AT29C256
0046P–FLASH–10/04
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
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