AT29C257-15JC [ATMEL]
256K 32K x 8 5-volt Only CMOS Flash Memory; 256K 32K ×8 5伏只有CMOS闪存
| 型号： | AT29C257-15JC |
| 厂家： | 
ATMEL |
| 描述： | 256K 32K x 8 5-volt Only CMOS Flash Memory |
| 文件： | 总12页 (文件大小：565K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT29C257
Features
Fast Read Access Time - 70 ns
5-Volt-Only Reprogramming
Page Program Operation
•
•
•
Single Cycle Reprogram (Erase and Program)
Internal Address and Data Latches for 64-Bytes
Internal Program Control and Timer
Hardware and Software Data Protection
Fast Program Cycle Times
•
•
•
Page (64-Byte) Program Time - 10 ms
Chip Erase Time - 10 ms
256K (32K x 8)
5-volt Only
CMOS Flash
Memory
DATA Polling for End of Program Detection
Low Power Dissipation
50 mA Active Current
300 µA CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V ± 10% Supply
•
•
•
•
CMOS and TTL Compatible Inputs and Outputs
Pin-Compatible with AT29C010A and AT29C512 for Easy System Upgrades
•
•
Description
The AT29C257 is a 5-volt-only in-system Flash programmable and erasable read only
memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits. Manu-
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers ac-
cess times to 70 ns with power dissipation of just 275 mW. When the device is dese-
lected, the CMOS standby current is less than 300 µA. The device endurance is such
that any sector can typically be written to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29C257 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C257 is performed on a page basis; 64-bytes of data are
loaded into the device and then simultaneously programmed. The contents of the
entire device may be erased by using a 6-byte software code (although erasure before
programming is not needed).
AT29C257
During a reprogram cycle, the address locations and 64-bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be de-
tected by DATA polling of I/O7. Once the end of a program cycle has been detected
a new access for a read, program or chip erase can begin.
Pin Configurations
PLCC Top View
Pin Name Function
A0 - A14
CE
Addresses
Chip Enable
Output Enable
Write Enable
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
NC
DC
No Connect
Don’t Connect
0012K
4-105
Block Diagram
Device Operation
SOFTWARE DATA PROTECTION: A software control-
led data protection feature is available on the AT29C257.
Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may
be performed. The software protection feature may be en-
abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en-
abled the same three program commands must begin
each program cycle in order for the programs to occur. All
software program commands must obey the page pro-
gram timing specifications. Once set, the software data
protection feature remains active unless its disable com-
mand is issued. Power transitions will not reset the soft-
ware data protection feature, however the software fea-
ture will guard against inadvertent program cycles during
power transitions.
READ: The AT29C257 is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
BYTE LOAD: A byte load is performed by applying a
low pulse on the WE or CE input with CE or WE low (re-
spectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE. Byte loads
are used to enter the 64-bytes of a page to be pro-
grammed or the software codes for data protection and
chip erasure.
PROGRAM: The device is reprogrammed on a page
basis. If a byte of data within a page is to be changed, data
for the entire page must be loaded into the device. Any
byte that is not loaded during the programming of its page
will be indeterminate. Once the bytes of a page are loaded
into the device, they are simultaneously programmed dur-
ing the internal programming period. After the first data
byte has been loaded into the device, successive bytes
are entered in the same manner. Each new byte to be pro-
grammed must have its high to low transition on WE (or
CE) within 150 µs of the low to high transition of WE (or
CE) of the preceding byte. If a high to low transition is not
detected within 150 µs of the last low to high transition, the
load period will end and the internal programming period
will start. A6 to A14 specify the page address. The page
address must be valid during each high to low transition of
WE (or CE). A0 to A5 specify the byte address within the
page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation
Once set, software data protection will remain active un-
less the disable command sequence is issued.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of t , a read operation will effectively be
WC
a polling operation.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. The 64-bytes of data
must be loaded into each sector by the same procedure as
outlined in the program section under device operation.
has been initiated, and for the duration of t , a read op-
WC
(continued)
eration will effectively be a polling operation.
4-106
AT29C257
AT29C257
Device Operation (Continued)
DATA POLLING: The AT29C257 features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C257 in
the following ways: (a) V sense— if V is below 3.8V
CC
CC
(typical), the program function is inhibited. (b) V power
CC
on delay— once V
has reached the V
sense level,
CC
CC
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit— holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter— pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
TOGGLE BIT: In addition to DATA polling the
AT29C257 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
PRODUCT IDENTIFICATION: The product identifica-
tion mode identifies the device and manufacturer and may
be accessed by a hardware or software operation. For de-
tails, see Operating Modes or Software Product Identifica-
tion.
OPTIONAL CHIP ERASE MODE: The entire device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
All Output Voltages
with Respect to Ground .............-0.6V to V + 0.6V
CC
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
4-107
DC and AC Operating Range
AT29C257-70
AT29C257-90
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT29C257-12
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT29C257-15
0°C - 70°C
-40°C - 85°C
5V ± 10%
Com.
Ind.
0°C - 70°C
-40°C - 85°C
5V ± 5%
Operating
Temperature (Case)
V
Power Supply
CC
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
V
V
V
V
V
Ai
Ai
Ai
X
D
D
IL
IL
IL
IH
IL
IH
IH
IH
OUT
IN
(2)
Program
V
V
V
V
IL
IL
5V Chip Erase
(1)
Standby/Write Inhibit
Write Inhibit
V
X
X
High Z
X
X
V
IH
Write Inhibit
X
X
V
X
IL
Output Disable
V
IH
X
High Z
High Z
(3)
High Voltage Chip Erase
Product Identification
V
IL
V
H
V
IL
X
A1 - A14 = VIL, A9 = VH,
A0 = VIL
A1 - A14 = VIL, A9 = VH,
A0 = VIH
(4)
Manufacturer Code
Hardware
V
IL
V
V
IH
IL
(4)
Device Code
(4)
A0 = VIL
A0 = VIH
Manufacturer Code
(5)
Software
(4)
Device Code
Notes: 1. X can be VIL or VIH.
4. Manufacturer Code: 1F, Device Code: DC
5. See details under Software Product Identification Entry/Exit.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
mA
mA
V
I
LI
Input Load Current
Output Leakage Current
V
V
= 0V to V
CC
IN
I
I
I
I
= 0V to V
CC
10
LO
I/O
V
V
V
Standby Current CMOS
Standby Current TTL
Active Current
CE = V - 0.3V to V
CC
300
3
SB1
SB2
CC
CC
CC
CC
CC
CE = 2.0V to V
CC
f= 5 MHz; I
= 0 mA
50
OUT
V
V
V
V
V
Input Low Voltage
0.8
IL
Input High Voltage
2.0
V
IH
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
I
I
I
= 2.1 mA
.45
V
OL
OH1
OH2
OL
OH
OH
= -400 µA
= -100 µA; V = 4.5V
2.4
4.2
V
V
CC
4-108
AT29C257
AT29C257
AC Read Characteristics
AT29C257-70 AT29C257-90 AT29C257-12 AT29C257-15
Min
Max
70
70
40
25
Min
Max
90
90
40
25
Min
Max
120
120
50
Min
Max
150
150
70
Symbol
Parameter
Units
ns
t
t
t
t
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
ACC
(1)
ns
CE
OE
DF
(2)
0
0
0
0
0
0
0
0
ns
(3, 4)
30
40
ns
Output Hold from OE, CE
or Address, whichever
occurred first
t
0
0
0
0
ns
OH
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
4. This parameter is characterized and is not 100% tested.
after an address change without impact on tACC
.
Output Test Load
Input Test Waveforms and Measurement Level
t , t < 5 ns
R
F
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
6
Units
pF
Conditions
C
C
4
8
V
V
= 0V
IN
IN
12
pF
= 0V
OUT
OUT
Note: 1. This parameter is characterized and is not 100% tested.
4-109
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
t
t
t
t
t
, t
Address, OE Set-up Time
Address Hold Time
AS OES
50
0
ns
AH
CS
CH
WP
DS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
35
0
ns
ns
, t
Data, OE Hold Time
Write Pulse Width High
ns
DH OEH
100
ns
WPH
AC Byte Load Waveforms
WE Controlled
CE Controlled
4-110
AT29C257
AT29C257
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
t
t
t
t
t
t
t
t
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
ms
ns
ns
ns
ns
ns
µs
ns
WC
0
AS
50
35
0
AH
DS
DH
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
90
WP
BLC
WPH
150
100
Program Cycle Waveforms (1, 2, 3)
Notes: 1. A6 through A14 must specify the page address
during each high to low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being
programmed will be indeterminate.
4-111
Software Data
Software Data
Protection Disable Algorithm (1)
Protection Enable Algorithm (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
LOAD DATA A0
TO
ADDRESS 5555
ADDRESS 5555
WRITES ENABLED
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA
TO
PAGE (64 BYTES)
(4)
ENTER DATA
(2)
PROTECT STATE
LOAD DATA 55
TO
ADDRESS 2AAA
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data Protect state will be activated at end of program cycle.
3. Data Protect state will be deactivated at end of program
period.
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
(3)
PROTECT STATE
4. 64-bytes of data must be loaded.
LOAD DATA
TO
(4)
PAGE (64 BYTES)
Software Protected Program Cycle Waveform (1, 2, 3)
Notes: 1. A6 through A14 must specify the page address
during each high to low transition of WE (or CE)
after the software code has been entered.
3. All bytes that are not loaded within the page being
programmed will be indeterminate.
2. OE must be high when WE and CE are both low.
4-112
AT29C257
AT29C257
Data Polling Characteristics (1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
DH
10
ns
OEH
OE
(2)
ns
Write Recovery Time
0
ns
WR
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
t
t
t
t
t
Data Hold Time
OE Hold Time
OE to Output Delay
OE High Pulse
DH
10
ns
OEH
OE
(2)
ns
150
0
ns
OEHP
WR
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms (1, 2, 3)
3. Any address location may be used but the address
should not vary.
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
4-113
Software Product
Software Product
Identification Exit (1)
Identification Entry (1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA F0
TO
LOAD DATA 90
TO
ADDRESS 5555
ADDRESS 5555
PAUSE 10 mS
PAUSE 10 mS
EXIT PRODUCT
IDENTIFICATION
ENTER PRODUCT
IDENTIFICATION
(4)
(2, 3, 5)
MODE
MODE
Notes for software product identification:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A14 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1F
Device Code: DC
4-114
AT29C257
AT29C257
4-115
Ordering Information
t
I
(mA)
ACC
CC
Ordering Code
AT29C257-70JC
AT29C257-70JI
AT29C257-90JC
AT29C257-90JI
AT29C257-12JC
AT29C257-12JI
AT29C257-15JC
AT29C257-15JI
Package
32J
Operation Range
(ns)
Active
Standby
70
50
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
Commercial
(0° to 70°C)
50
50
50
50
50
50
50
32J
Industrial
(-40° to 85°C)
90
32J
Commercial
(0° to 70°C)
32J
Industrial
(-40° to 85°C)
120
150
32J
Commercial
(0° to 70°C)
32J
Industrial
(-40° to 85°C)
32J
Commercial
(0° to 70°C)
32J
Industrial
(-40° to 85°C)
Package Type
32J
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
4-116
AT29C257
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