AT32UC3A0256-ALUR_技术文档

Features

• High Performance, Low Power AVR^®32 UC 32-Bit Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing 1.49 DMIPS / MHz

Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)

Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State)

– Memory Protection Unit

• Multi-hierarchy Bus System

AVR^®32

32-Bit

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 15 Peripheral DMA Channels Improves Speed for Peripheral Communication

• Internal High-Speed Flash

– 512K Bytes, 256K Bytes, 128K Bytes Versions

Microcontroller

– Single Cycle Access up to 33 MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)

• External Memory Interface on AT32UC3A0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

• Interrupt Controller

AT32UC3A0512

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

AT32UC3A1128

– Autovectored Low Latency Interrupt Service with Programmable Priority

• System Functions

– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator

– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing

Independant CPU Frequency from USB Frequency

– Watchdog Timer, Real-Time Clock Timer

Preliminary

Summary

• Universal Serial Bus (USB)

– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

• Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller

– Supports Media Independent Interface (MII) and Reduced MII (RMII)

• One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces

– Support for Hardware Handshaking, RS485 Interfaces and Modem Line

• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

• One Synchronous Serial Protocol Controller

– Supports I2S and Generic Frame-Based Protocols

• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible

• One 8-channel 10-bit Analog-To-Digital Converter

• 16-bit Stereo Audio Bitstream

– Sample Rate Up to 50 KHz

32058FS–AVR32–08/08

AT32UC3A

• On-Chip Debug System (JTAG interface)

– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace

• 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins)

• 5V Input Tolerant I/Os

• Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply

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AT32UC3A

1. Description

The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC

processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC

microprocessor core, designed for cost-sensitive embedded applications, with particular empha-

sis on low power consumption, high code density and high performance.

The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-

troller for supporting modern operating systems and real-time operating systems. Higher

computation capabilities are achievable using a rich set of DSP instructions.

The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access.

For applications requiring additional memory, an external memory interface is provided on

AT32UC3A0 derivatives.

The Peripheral Direct Memory Access controller (PDCA) enables data transfers between periph-

erals and memories without processor involvement. PDCA drastically reduces processing

overhead when transferring continuous and large data streams between modules within the

MCU.

The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector

monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external

oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.

The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be

independently programmed to perform frequency measurement, event counting, interval mea-

surement, pulse generation, delay timing and pulse width modulation.

The PWM modules provides seven independent channels with many configuration options

including polarity, edge alignment and waveform non overlap control. One PWM channel can

trigger ADC conversions for more accurate close loop control implementations.

The AT32UC3A also features many communication interfaces for communication intensive

applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like

flexible Synchronous Serial Controller, USB and Ethernet MAC are available.

The Synchronous Serial Controller provides easy access to serial communication protocols and

audio standards like I2S.

The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time

thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device

like a USB Flash disk or a USB printer to be directly connected to the processor.

The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module

provides on-chip solutions for network-connected devices.

AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive

real-time trace, full-speed read/write memory access in addition to basic runtime control.

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AT32UC3A

2. Configuration Summary

The table below lists all AT32UC3A memory and package configurations:

Ethernet

Ext. Bus Interface MAC

Device

Flash

SRAM

Package

AT32UC3A0512

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

AT32UC3A1128

512 Kbytes

256 Kbytes

128 Kbytes

512 Kbytes

256 Kbytes

128 Kbytes

64 Kbytes

32 Kbytes

64 Kbytes

32 Kbytes

yes

no

yes

144 lead LQFP

100 lead TQFP

no

3. Abbreviations

• GCLK: Power Manager Generic Clock

• GPIO: General Purpose Input/Output

• HSB: High Speed Bus

• MPU: Memory Protection Unit

• OCD: On Chip Debug

• PB: Peripheral Bus

• PDCA: Peripheral Direct Memory Access Controller (PDC) version A

• USBB: USB On-The-GO Controller version B

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AT32UC3A

4. Blockdiagram

Figure 4-1. Blockdiagram

TCK

TDO

TDI

LOCAL BUS

INTERFACE

FAST GPIO

JTAG

INTERFACE

TMS

UC CPU

NEXUS

CLASS 2+

OCD

MCKO

MEMORY PROTECTION UNIT

MDO[5..0]

MSEO[1..0]

EVTI_N

64 KB

SRAM

INSTR

DATA

EVTO_N

INTERFACE

VBUS

D+

D-

USB

INTERFACE

ID

VBOF

512 KB

FLASH

M

S

M

DMA

S

COL,

CRS,

RXD[3..0],

RX_CLK,

RX_DV,

RX_ER

M

HIGH SPEED

BUS MATRIX

DATA[15..0]

ADDR[23..0]

S

M

S

MDC,

TXD[3..0],

TX_CLK,

TX_EN,

TX_ER,

SPEED

NCS[3..0]

NRD

S

ETHERNET

MAC

NWAIT

NWE0

NWE1

NWE3

RAS

CONFIGURATION

REGISTERS BUS

HS

B

HSB-PB

BRIDGE B

HSB

HSB-PB

BRIDGE A

PB

PERIPHERAL

DMA

CONTROLLER

MDIO

CAS

SDA10

SDCK

SDCKE

SDCS0

SDWE

INTERRUPT

CONTROLLER

RXD

TXD

CLK

RTS, CTS

PA

PB

PC

PX

USART1

EXTERNAL

INTERRUPT

CONTROLLER

PA

PB

PC

PX

EXTINT[7..0]

DSR, DTR, DCD, RI

KPS[7..0]

NMI_N

RXD

TXD

CLK

USART0

USART2

USART3

REAL TIME

COUNTER

RTS, CTS

SCK

SERIAL

PERIPHERAL

INTERFACE 0/1

MISO, MOSI

NPCS0

WATCHDOG

TIMER

NPCS[3..1]

TX_CLOCK, TX_FRAME_SYNC

TX_DATA

SYNCHRONOUS

SERIAL

CONTROLLER

115 kHz

RCOSC

POWER

MANAGER

RX_CLOCK, RX_FRAME_SYNC

RX_DATA

32 KHz

OSC

XIN32

XOUT32

CLOCK

SCL

SDA

GENERATOR

TWO-WIRE

INTERFACE

XIN0

OSC0

OSC1

XOUT0

CLOCK

CONTROLLER

XIN1

XOUT1

PULSE WIDTH

MODULATION

CONTROLLER

SLEEP

CONTROLLER

PWM[6..0]

AD[7..0]

PLL0

PLL1

RESET

CONTROLLER

ANALOG TO

DIGITAL

GCLK[3..0]

RESET_N

ADVREF

CONVERTER

A[2..0]

B[2..0]

CLK[2..0]

TIMER/COUNTER

AUDIO

BITSTREAM

DAC

DATA[1..0]

DATAN[1..0]

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32058FS–AVR32–08/08

AT32UC3A

4.1

Processor and architecture

4.1.1

AVR32 UC CPU

• 32-bit load/store AVR32A RISC architecture.

– 15 general-purpose 32-bit registers.

– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.

– Fully orthogonal instruction set.

– Privileged and unprivileged modes enabling efficient and secure Operating Systems.

– Innovative instruction set together with variable instruction length ensuring industry leading

code density.

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.

• 3 stage pipeline allows one instruction per clock cycle for most instructions.

– Byte, half-word, word and double word memory access.

– Multiple interrupt priority levels.

• MPU allows for operating systems with memory protection.

4.1.2

4.1.3

4.1.4

Debug and Test system

• IEEE1149.1 compliant JTAG and boundary scan

• Direct memory access and programming capabilities through JTAG interface

• Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+

– Low-cost NanoTrace supported.

• Auxiliary port for high-speed trace information

• Hardware support for 6 Program and 2 data breakpoints

• Unlimited number of software breakpoints supported

• Advanced Program, Data, Ownership, and Watchpoint trace supported

Peripheral DMA Controller

• Transfers from/to peripheral to/from any memory space without intervention of the processor.

• Next Pointer Support, forbids strong real-time constraints on buffer management.

• Fifteen channels

– Two for each USART

– Two for each Serial Synchronous Controller

– Two for each Serial Peripheral Interface

– One for each ADC

– Two for each TWI Interface

Bus system

• High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled

– Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet

Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus

B, EBI.

– Round-Robin Arbitration (three modes supported: no default master, last accessed default

master, fixed default master)

– Burst Breaking with Slot Cycle Limit

– One Address Decoder Provided per Master

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32058FS–AVR32–08/08

AT32UC3A

• Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus

Figure 4-1 gives an overview of the bus system. All modules connected to the same bus use the

same clock, but the clock to each module can be individually shut off by the Power Manager.

The figure identifies the number of master and slave interfaces of each module connected to the

High Speed Bus, and which DMA controller is connected to which peripheral.

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AT32UC3A

5. Signals Description

The following table gives details on the signal name classified by peripheral

The signals are multiplexed with GPIO pins as described in ”Peripheral Multiplexing on I/O lines”

on page 30.

Table 5-1.

Signal Description List

Active

Level

Signal Name

Function

Type

Comments

Power

Input

VDDPLL

VDDCORE

VDDIO

Power supply for PLL

Core Power Supply

1.65V to 1.95 V

3.0V to 3.6V

Power

Input

Power

Input

I/O Power Supply

Power

Input

VDDANA

VDDIN

Analog Power Supply

Voltage Regulator Input Supply

Voltage Regulator Output

3.0V to 3.6V

Power

Input

3.0V to 3.6V

Power

Output

VDDOUT

1.65V to 1.95 V

GNDANA

GND

Analog Ground

Ground

Clocks, Oscillators, and PLL’s

XIN0, XIN1, XIN32

Crystal 0, 1, 32 Input

Crystal 0, 1, 32 Output

Analog

XOUT0, XOUT1,

XOUT32

Analog

JTAG

Input

TCK

TDI

Test Clock

Test Data In

Input

TDO

TMS

Test Data Out

Test Mode Select

Output

Input

Auxiliary Port - AUX

Output

MCKO

Trace Data Output Clock

Trace Data Output

MDO0 - MDO5

Output

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32058FS–AVR32–08/08

AT32UC3A

Table 5-1.

Signal Description List

Active

Level

Signal Name

Function

Type

Comments

MSEO0 - MSEO1

EVTI_N

Trace Frame Control

Event In

Output

Low

EVTO_N

Event Out

Power Manager - PM

GCLK0 - GCLK3

RESET_N

Generic Clock Pins

Reset Pin

Output

Input

Low

Real Time Counter - RTC

Output

Watchdog Timer - WDT

RTC_CLOCK

WDTEXT

RTC clock

External Watchdog Pin

Output

External Interrupt Controller - EIC

EXTINT0 - EXTINT7

KPS0 - KPS7

NMI_N

External Interrupt Pins

Keypad Scan Pins

Input

Output

Non-Maskable Interrupt Pin

Input

Ethernet MAC - MACB

Low

COL

Collision Detect

Input

Output

I/O

CRS

Carrier Sense and Data Valid

Management Data Clock

Management Data Input/Output

Receive Data

MDC

MDIO

RXD0 - RXD3

RX_CLK

RX_DV

RX_ER

SPEED

TXD0 - TXD3

TX_CLK

TX_EN

TX_ER

Input

Receive Clock

Receive Data Valid

Receive Coding Error

Speed

Transmit Data

Output

Transmit Clock or Reference Clock

Transmit Enable

Transmit Coding Error

9

32058FS–AVR32–08/08

AT32UC3A

Table 5-1.

Signal Description List

Active

Level

Signal Name

Function

Type

Comments

External Bus Interface - HEBI

ADDR0 - ADDR23

CAS

Address Bus

Output

I/O

Column Signal

Data Bus

Low

DATA0 - DATA15

NCS0 - NCS3

NRD

Chip Select

Output

Input

Low

Read Signal

NWAIT

External Wait Signal

Write Enable 0

Write Enable 1

Write Enable 3

Row Signal

NWE0

Output

NWE1

NWE3

RAS

SDA10

SDRAM Address 10 Line

SDRAM Clock

SDCK

SDCKE

SDCS0

SDRAM Clock Enable

SDRAM Chip Select

SDRAM Write Enable

Low

SDWE

General Purpose Input/Output 2 - GPIOA, GPIOB, GPIOC

P0 - P31

P0 - P5

Parallel I/O Controller GPIOA

I/O

Parallel I/O Controller GPIOB

Parallel I/O Controller GPIOC

Parallel I/O Controller GPIOX

P0 - P31

Serial Peripheral Interface - SPI0, SPI1

MISO

Master In Slave Out

Master Out Slave In

I/O

MOSI

NPCS0 - NPCS3

SCK

SPI Peripheral Chip Select

Clock

I/O

Low

Output

Synchronous Serial Controller - SSC

RX_CLOCK

SSC Receive Clock

I/O

10

32058FS–AVR32–08/08

AT32UC3A

Table 5-1.

Signal Description List

Active

Level

Signal Name

Function

Type

Input

I/O

Comments

RX_DATA

SSC Receive Data

RX_FRAME_SYNC

TX_CLOCK

SSC Receive Frame Sync

SSC Transmit Clock

I/O

TX_DATA

SSC Transmit Data

Output

I/O

TX_FRAME_SYNC

SSC Transmit Frame Sync

Timer/Counter - TIMER

A0

Channel 0 Line A

I/O

A1

Channel 1 Line A

A2

Channel 2 Line A

I/O

B0

Channel 0 Line B

I/O

B1

Channel 1 Line B

I/O

B2

Channel 2 Line B

I/O

CLK0

CLK1

CLK2

Channel 0 External Clock Input

Channel 1 External Clock Input

Channel 2 External Clock Input

Input

Two-wire Interface - TWI

SCL

SDA

Serial Clock

Serial Data

I/O

Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3

CLK

CTS

DCD

DSR

DTR

RI

Clock

I/O

Clear To Send

Data Carrier Detect

Data Set Ready

Data Terminal Ready

Ring Indicator

Request To Send

Receive Data

Input

Only USART1

RTS

RXD

TXD

Output

Input

Transmit Data

Output

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AT32UC3A

Table 5-1.

Signal Description List

Active

Level

Signal Name

Function

Type

Comments

Analog to Digital Converter - ADC

Analog

input

AD0 - AD7

ADVREF

Analog input pins

Analog

input

Analog positive reference voltage input

2.6 to 3.6V

Pulse Width Modulator - PWM

PWM0 - PWM6

PWM Output Pins

Output

Universal Serial Bus Device - USB

DDM

DDP

USB Device Port Data -

USB Device Port Data +

Analog

VBUS

USB VBUS Monitor and OTG Negociation

ID Pin of the USB Bus

USB VBUS On/off: bus power control port

Input

USBID

Input

USB_VBOF

output

Audio Bitstream DAC (ABDAC)

DATA0-DATA1

D/A Data out

D/A Data inverted out

Outpu

DATAN0-DATAN1

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AT32UC3A

6. Package and Pinout

The device pins are multiplexed with peripheral functions as described in ”Peripheral Multiplexing on I/O lines” on page 30.

Figure 6-1. TQFP100 Pinout

75

51

76

50

26

100

1

25

Table 6-1.

TQFP100 Package Pinout

1

2

PB20

PB21

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

PA05

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

PA21

PA22

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

PB08

PB09

PB10

VDDIO

GND

PA06

PA07

PA08

PA09

PA10

N/C

3

PB22

PA23

4

VDDIO

GND

PA24

5

PA25

6

PB23

PA26

PB11

PB12

PA29

PA30

PC02

PC03

PB13

PB14

TMS

7

PB24

PA27

8

PB25

PA11

PA28

9

PB26

VDDCORE

GND

VDDANA

ADVREF

GNDANA

VDDPLL

PC00

10

11

12

13

14

15

16

17

18

19

20

21

22

PB27

VDDOUT

VDDIN

GND

PA12

PA13

VDDCORE

PA14

PB28

PC01

PB29

PA15

PB00

TCK

PB30

PA16

PB01

TDO

PB31

PA17

VDDIO

GND

TDI

RESET_N

PA00

PA18

PC04

PC05

PB15

PB16

VDDCORE

PA19

PA01

PA20

PB02

GND

VBUS

VDDIO

PB03

VDDCORE

PB04

13

32058FS–AVR32–08/08

AT32UC3A

Table 6-1.

TQFP100 Package Pinout

23

24

25

PA02

PA03

PA04

48

49

50

DM

DP

73

74

75

PB05

PB06

PB07

98

99

PB17

PB18

PB19

GND

100

Figure 6-2. LQFP144 Pinout

108

73

109

144

72

37

1

36

Table 6-2.

VQFP144 Package Pinout

1

2

PX00

PX01

PB20

PX02

PB21

PB22

VDDIO

GND

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

GND

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

PA21

PA22

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

GND

PX30

PB08

PX31

PB09

PX32

PB10

VDDIO

GND

PX33

PB11

PX34

PB12

PA29

PA30

PC02

PC03

PB13

PB14

TMS

PX10

PA05

PX11

PA06

PX12

PA07

PX13

PA08

PX14

PA09

PA10

N/C

3

PA23

4

PA24

5

PA25

6

PA26

7

PA27

8

PA28

9

PB23

PX03

PB24

PX04

PB25

PB26

PB27

VDDOUT

VDDIN

GND

VDDANA

ADVREF

GNDANA

VDDPLL

PC00

10

11

12

13

14

15

16

17

18

19

20

21

PA11

PC01

VDDCORE

GND

PX20

PB00

PA12

PX21

PA13

PB01

PB28

PB29

PB30

VDDCORE

PA14

PX22

VDDIO

PA15

TCK

14

32058FS–AVR32–08/08

AT32UC3A

Table 6-2.

VQFP144 Package Pinout

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

PB31

RESET_N

PX05

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

PA16

PX15

PA17

PX16

PA18

PX17

PA19

PX18

PA20

PX19

VBUS

VDDIO

DM

94

95

GND

PX23

PB02

PX24

PB03

PX25

PB04

PX26

PB05

PX27

PB06

PX28

PB07

PX29

VDDIO

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

TDO

TDI

96

PC04

PC05

PB15

PX35

PB16

PX36

VDDCORE

PB17

PX37

PB18

PX38

PB19

PX39

PA00

97

PX06

98

PA01

99

GND

100

101

102

103

104

105

106

107

108

VDDCORE

PA02

PX07

PA03

PX08

PA04

PX09

DP

VDDIO

GND

15

32058FS–AVR32–08/08

AT32UC3A

7. Power Considerations

7.1

Power Supplies

The AT32UC3A has several types of power supply pins:

• VDDIO: Powers I/O lines. Voltage is 3.3V nominal.

• VDDANA: Powers the ADC Voltage is 3.3V nominal.

• VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal.

• VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.

• VDDPLL: Powers the PLL. Voltage is 1.8V nominal.

The ground pins GND are common to VDDCORE, VDDIO, VDDPLL. The ground pin for

VDDANA is GNDANA.

Refer to ”Power Consumption” on page 42 for power consumption on the various supply pins.

Dual Power Supply

Single Power Supply

3.3V

VDDANA

VDDIO

3.3V

VDDANA

VDDIO

ADVREF

VDDIN

ADVREF

VDDIN

1.8V

Regulator

VDDOUT

1.8V

VDDCORE

VDDPLL

VDDCORE

VDDPLL

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32058FS–AVR32–08/08

AT32UC3A

7.2

Voltage Regulator

7.2.1

Single Power Supply

The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes

its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be

externally connected to the 1.8V domains.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability

and reduce source voltage drop. Two input decoupling capacitors must be placed close to the

chip.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscil-

lations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and

GND as close to the chip as possible

3.3V

1.8V

VDDIN

C

IN1

IN2

1.8V

Regulator

VDDOUT

C

OUT1

OUT2

Refer to Section 12.3 on page 41 for decoupling capacitors values and regulator characteristics

7.2.2

Dual Power Supply

In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent

from leakage current.

VDDIN

VDDOUT

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AT32UC3A

7.3

Analog-to-Digital Converter (A.D.C) reference.

The ADC reference (ADVREF) must be provided from an external source. Two decoupling

capacitors must be used to insure proper decoupling.

3.3V

ADVREF

C

VREF2

VREF1

Refer to Section 12.4 on page 41 for decoupling capacitors values and electrical characteristics.

In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra

consumption.

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8. I/O Line Considerations

8.1

JTAG pins

TMS, TDI and TCK have pull-up resistors. TDO is an output, driven at up to VDDIO, and has no

pull-up resistor.

8.2

RESET_N pin

The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As

the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case

no reset from the system needs to be applied to the product.

8.3

8.4

TWI pins

When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and

inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the

pins have the same characteristics as PIO pins.

GPIO pins

All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is

performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines

default as inputs with pull-up resistors disabled, except when indicated otherwise in the column

“Reset State” of the GPIO Controller multiplexing tables.

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9. Memories

9.1

Embedded Memories

• Internal High-Speed Flash

– 512 KBytes (AT32UC3A0512, AT32UC3A1512)

– 256 KBytes (AT32UC3A0256, AT32UC3A1256)

– 128 KBytes (AT32UC3A1128, AT32UC3A2128)

- 0 Wait State Access at up to 33 MHz in Worst Case Conditions

- 1 Wait State Access at up to 66 MHz in Worst Case Conditions

- Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding

penalty of 1 wait state access

- Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation

to only 15% compared to 0 wait state operation

- 100 000 Write Cycles, 15-year Data Retention Capability

- 4 ms Page Programming Time, 8 ms Chip Erase Time

- Sector Lock Capabilities, Bootloader Protection, Security Bit

- 32 Fuses, Erased During Chip Erase

- User Page For Data To Be Preserved During Chip Erase

• Internal High-Speed SRAM, Single-cycle access at full speed

– 64 KBytes (AT32UC3A0512, AT32UC3A0256, AT32UC3A1512, AT32UC3A1256)

– 32KBytes (AT32UC3A1128)

9.2

Physical Memory Map

The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they

are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented

translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space

is mapped as follows:

Table 9-1.

AT32UC3A Physical Memory Map

Size

Device

Start Address

AT32UC3A0512

64 Kbyte

AT32UC3A1512

AT32UC3A0256

64 Kbyte

AT32UC3A1256

AT32UC3A0128

32 Kbyte

AT32UC3A1128

Embedded SRAM 0x0000_0000

64 Kbyte

32 Kbyte

Embedded Flash

EBI SRAM CS0

EBI SRAM CS2

EBI SRAM CS3

0x8000_0000

0xC000_0000

0xC800_0000

512 Kbyte

16 Mbyte

512 Kbyte

256 Kbyte

16 Mbyte

256 Kbyte

128 Kbyte

16 Mbyte

128 Kbyte

-

0xCC00_0000 16 Mbyte

EBI SRAM CS1

/SDRAM CS0

0xD000_0000

0xE000_0000

128 Mbyte

64 Kbyte

-

128 Mbyte

64 Kbyte

-

128 Mbyte

64 Kbyte

-

USB

Configuration

64 Kbyte

HSB-PB Bridge A

HSB-PB Bridge B

0xFFFE_0000

0xFFFF_0000

64 Kbyte

64 kByte

64 Kbyte

64 kByte

64 Kbyte

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Table 9-2.

Flash Memory Parameters

General Purpose

Fuse bits

Flash Size

Number of pages

Page size

Part Number

AT32UC3A0512

(FLASH_PW)

512 Kbytes

256 Kbytes

128 Kbytes

(FLASH_P)

(FLASH_W)

(FLASH_F)

1024

512

64

128 words

32 fuses

AT32UC3A1512

AT32UC3A0256

AT32UC3A1256

AT32UC3A1128

AT32UC3A0128

64

9.3

Bus Matrix Connections

Accesses to unused areas returns an error result to the master requesting such an access.

The bus matrix has the several masters and slaves. Each master has its own bus and its own

decoder, thus allowing a different memory mapping per master. The master number in the table

below can be used to index the HMATRIX control registers. For example, MCFG0 is associated

with the CPU Data master interface.

Table 9-3.

Master 0

Master 1

Master 2

Master 3

Master 4

Master 5

High Speed Bus masters

CPU Data

CPU Instruction

CPU SAB

PDCA

MACB DMA

USBB DMA

Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number

in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is

associated with the Internal SRAM Slave Interface.

Table 9-4.

Slave 0

Slave 1

Slave 2

Slave 3

Slave 4

Slave 5

High Speed Bus slaves

Internal Flash

HSB-PB Bridge 0

HSB-PB Bridge 1

Internal SRAM

USBB DPRAM

EBI

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32058FS–AVR32–08/08

AT32UC3A

Figure 9-1. HMatrix Master / Slave Connections

HMATRIX SLAVES

0

1

2

3

4

5

CPU Data

0

1

2

3

4

5

CPU

Instruction

CPU SAB

PDCA

MACB

USBB DMA

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AT32UC3A

10. Peripherals

10.1 Peripheral address map

Table 10-1. Peripheral Address Mapping

Address

Peripheral Name

Bus

0xE0000000

USBB

USBB Slave Interface - USBB

HSB

PBB

0xFFFE0000

0xFFFE1000

0xFFFE1400

0xFFFE1800

0xFFFE1C00

0xFFFE2000

0xFFFF0000

0xFFFF0800

0xFFFF0C00

0xFFFF0D00

0xFFFF0D30

0xFFFF0D80

0xFFFF1000

0xFFFF1400

0xFFFF1800

USBB

HMATRIX

FLASHC

MACB

SMC

USBB Configuration Interface - USBB

HMATRIX Configuration Interface - HMATRIX

Flash Controller - FLASHC

MACB Configuration Interface - MACB

Static Memory Controller Configuration Interface -

SMC

PBB

PBA

SDRAM Controller Configuration Interface -

SDRAMC

PDCA

INTC

Peripheral DMA Interface - PDCA

Interrupt Controller Interface - INTC

Power Manager - PM

PM

RTC

Real Time Clock - RTC

WDT

WatchDog Timer - WDT

EIC

External Interrupt Controller - EIC

General Purpose IO Controller - GPIO

GPIO

Universal Synchronous Asynchronous Receiver

Transmitter - USART0

USART0

USART1

Universal Synchronous Asynchronous Receiver

Transmitter - USART1

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Table 10-1. Peripheral Address Mapping (Continued)

Address

Peripheral Name

Bus

0xFFFF1C00

Universal Synchronous Asynchronous Receiver

Transmitter - USART2

USART2

PBA

0xFFFF2000

Universal Synchronous Asynchronous Receiver

Transmitter - USART3

USART3

0xFFFF2400

SPI0

Serial Peripheral Interface - SPI0

Serial Peripheral Interface - SPI1

Two Wire Interface - TWI

0xFFFF2800

SPI1

0xFFFF2C00

TWI

0xFFFF3000

PWM

Pulse Width Modulation Controller - PWM

Synchronous Serial Controller - SSC

Timer/Counter - TC

0xFFFF3400

SSC

0xFFFF3800

TC

0xFFFF3C00

ADC

Analog To Digital Converter - ADC

10.2 CPU Local Bus Mapping

Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to

being mapped on the Peripheral Bus. These registers can therefore be reached both by

accesses on the Peripheral Bus, and by accesses on the local bus.

Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since

the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at

CPU speed, one write or read operation can be performed per clock cycle to the local bus-

mapped GPIO registers.

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AT32UC3A

The following GPIO registers are mapped on the local bus:

Table 10-2. Local bus mapped GPIO registers

Local Bus

Address

Port

Register

Mode

WRITE

SET

Access

0

Output Driver Enable Register (ODER)

0x4000_0040

0x4000_0044

0x4000_0048

0x4000_004C

0x4000_0050

0x4000_0054

0x4000_0058

0x4000_005C

0x4000_0060

0x4000_0140

0x4000_0144

0x4000_0148

0x4000_014C

0x4000_0150

0x4000_0154

0x4000_0158

0x4000_015C

0x4000_0160

0x4000_0240

0x4000_0244

0x4000_0248

0x4000_024C

0x4000_0250

0x4000_0254

0x4000_0258

0x4000_025C

0x4000_0260

Write-only

Read-only

Write-only

Read-only

Write-only

Read-only

CLEAR

TOGGLE

WRITE

SET

Output Value Register (OVR)

CLEAR

TOGGLE

-

Pin Value Register (PVR)

1

Output Driver Enable Register (ODER)

WRITE

SET

CLEAR

TOGGLE

WRITE

SET

Output Value Register (OVR)

CLEAR

TOGGLE

-

Pin Value Register (PVR)

2

Output Driver Enable Register (ODER)

WRITE

SET

CLEAR

TOGGLE

WRITE

SET

Output Value Register (OVR)

Pin Value Register (PVR)

CLEAR

TOGGLE

-

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AT32UC3A

Table 10-2. Local bus mapped GPIO registers

Local Bus

Address

Port

Register

Mode

WRITE

SET

Access

3

Output Driver Enable Register (ODER)

0x4000_0340

0x4000_0344

0x4000_0348

0x4000_034C

0x4000_0350

0x4000_0354

0x4000_0358

0x4000_035C

0x4000_0360

Write-only

Read-only

CLEAR

TOGGLE

WRITE

SET

Output Value Register (OVR)

Pin Value Register (PVR)

CLEAR

TOGGLE

-

10.3 Interrupt Request Signal Map

The various modules may output Interrupt request signals. These signals are routed to the Inter-

rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64

groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt

signals in the same group share the same autovector address and priority level. Refer to the

documentation for the individual submodules for a description of the semantics of the different

interrupt requests.

The interrupt request signals are connected to the INTC as follows.

Table 10-3. Interrupt Request Signal Map

Group

Line

Module

Signal

AVR32 UC CPU with optional MPU and

optional OCD

SYSBLOCK

COMPARE

0

1

External Interrupt Controller

Real Time Counter

EIC 0

EIC 1

EIC 2

EIC 3

EIC 4

EIC 5

EIC 6

EIC 7

RTC

2

3

4

1

5

6

7

8

9

Power Manager

PM

10

Frequency Meter

FREQM

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AT32UC3A

Table 10-3. Interrupt Request Signal Map

0

1

General Purpose Input/Output

GPIO 0

GPIO 1

General Purpose Input/Output

Peripheral DMA Controller

Flash Controller

2

GPIO 2

3

GPIO 3

4

GPIO 4

5

GPIO 5

6

GPIO 6

2

7

GPIO 7

8

GPIO 8

9

GPIO 9

10

11

12

13

0

GPIO 10

GPIO 11

GPIO 12

GPIO 13

PDCA 0

PDCA 1

PDCA 2

PDCA 3

PDCA 4

PDCA 5

PDCA 6

PDCA 7

PDCA 8

PDCA 9

PDCA 10

PDCA 11

PDCA 12

PDCA 13

PDCA 14

FLASHC

1

2

3

4

5

6

3

7

8

9

10

11

12

13

14

0

4

5

Universal Synchronous/Asynchronous

Receiver/Transmitter

0

USART0

USART1

USART2

USART3

Universal Synchronous/Asynchronous

Receiver/Transmitter

6

7

8

Universal Synchronous/Asynchronous

Receiver/Transmitter

Universal Synchronous/Asynchronous

Receiver/Transmitter

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AT32UC3A

Table 10-3. Interrupt Request Signal Map

9

0

1

2

0

Serial Peripheral Interface

Two-wire Interface

SPI0

SPI1

10

11

12

13

TWI

Pulse Width Modulation Controller

Synchronous Serial Controller

Timer/Counter

PWM

SSC

TC0

14

Timer/Counter

TC1

Timer/Counter

TC2

15

16

17

18

19

Analog to Digital Converter

Ethernet MAC

ADC

MACB

USBB

SDRAMC

DAC

USB 2.0 OTG Interface

SDRAM Controller

Audio Bitstream DAC

10.4 Clock Connections

10.4.1

Timer/Counters

Each Timer/Counter channel can independently select an internal or external clock source for its

counter:

Table 10-4. Timer/Counter clock connections

Source

Name

Connection

Internal

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

32 KHz Oscillator

PBA clock / 2

PBA clock / 8

PBA clock / 32

PBA clock / 128

See Section 10.7

External

XC1

XC2

10.4.2

USARTs

Each USART can be connected to an internally divided clock:

Table 10-5. USART clock connections

USART

Source

Name

Connection

0

1

2

3

Internal

CLK_DIV

PBA clock / 8

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32058FS–AVR32–08/08

AT32UC3A

10.4.3

SPIs

Each SPI can be connected to an internally divided clock:

Table 10-6. SPI clock connections

SPI

0

Source

Name

Connection

Internal

CLK_DIV

PBA clock or

PBA clock / 32

1

10.5 Nexus OCD AUX port connections

If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-

spectively of the PIO configuration. Two different OCD trace pin mappings are possible,

depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Tech-

nical Reference Manual.

Table 10-7. Nexus OCD AUX port connections

AXS=0

PB19

PB16

PB14

PB13

PB12

PB11

PB10

PB20

PB21

PB04

PB17

AXS=1

PA08

PA27

PA26

PA25

PA24

PA23

PA22

PB20

PA21

PA07

PA28

EVTI_N

MDO[5]

MDO[4]

MDO[3]

MDO[2]

MDO[1]

MDO[0]

EVTO_N

MCKO

MSEO[1]

MSEO[0]

10.6 PDC handshake signals

The PDC and the peripheral modules communicate through a set of handshake signals. The fol-

lowing table defines the valid settings for the Peripheral Identifier (PID) in the PDC Peripheral

Select Register (PSR).

Table 10-8. PDC Handshake Signals

PID Value

Peripheral module & direction

ADC

0

1

2

3

SSC - RX

USART0 - RX

USART1 - RX

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AT32UC3A

Table 10-8. PDC Handshake Signals

PID Value

Peripheral module & direction

USART2 - RX

USART3 - RX

TWI - RX

4

5

6

7

SPI0 - RX

8

SPI1 - RX

9

SSC - TX

10

11

12

13

14

15

16

17

USART0 - TX

USART1 - TX

USART2 - TX

USART3 - TX

TWI - TX

SPI0 - TX

SPI1 - TX

ABDAC

10.7 Peripheral Multiplexing on I/O lines

Each GPIO line can be assigned to one of 3 peripheral functions; A, B or C. The following table

define how the I/O lines on the peripherals A, B and C are multiplexed by the GPIO.

Table 10-9. GPIO Controller Function Multiplexing

TQFP100

19

VQFP144

25

GPIO Pin

GPIO 0

GPIO 1

GPIO 2

GPIO 3

GPIO 4

GPIO 5

GPIO 6

GPIO 7

GPIO 8

GPIO 9

GPIO 10

GPIO 11

GPIO 12

GPIO 13

Function A

Function B

TC - CLK0

Function C

PA00

PA01

PA02

PA03

PA04

PA05

PA06

PA07

PA08

PA09

PA10

PA11

PA12

PA13

USART0 - RXD

USART0 - TXD

USART0 - CLK

USART0 - RTS

USART0 - CTS

USART1 - RXD

USART1 - TXD

USART1 - CLK

USART1 - RTS

USART1 - CTS

SPI0 - NPCS[0]

SPI0 - MISO

20

27

TC - CLK1

23

30

TC - CLK2

24

32

EIM - EXTINT[4]

EIM - EXTINT[5]

PWM - PWM[4]

PWM - PWM[5]

PM - GCLK[0]

SPI0 - NPCS[1]

SPI0 - NPCS[2]

EIM - EXTINT[6]

USB - USB_ID

USB - USB_VBOF

DAC - DATA[0]

25

34

DAC - DATAN[0]

26

39

27

41

28

43

SPI0 - NPCS[3]

EIM - EXTINT[7]

MACB - WOL

29

45

30

47

31

48

33

50

36

53

SPI0 - MOSI

37

54

SPI0 - SCK

SSC -

TX_FRAME_SYNC

39

40

56

57

PA14

PA15

GPIO 14

GPIO 15

SPI1 - NPCS[0]

SPI1 - SCK

EBI - NCS[0]

SSC - TX_CLOCK

EBI - ADDR[20]

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AT32UC3A

Table 10-9. GPIO Controller Function Multiplexing

41

42

43

58

60

62

PA16

PA17

PA18

GPIO 16

GPIO 17

GPIO 18

SSC - TX_DATA

SSC - RX_DATA

SSC - RX_CLOCK

SPI1 - MOSI

SPI1 - MISO

EBI - ADDR[21]

EBI - ADDR[22]

MACB - WOL

SPI1 - NPCS[1]

SSC -

RX_FRAME_SYNC

44

64

PA19

GPIO 19

SPI1 - NPCS[2]

45

51

52

53

54

55

56

57

58

83

84

65

66

70

71

72

73

74

75

76

77

78

81

82

87

88

95

96

98

99

100

1

66

73

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PB00

PB01

PB02

PB03

PB04

PB05

PB06

PB07

PB08

PB09

PB10

PB11

PB12

PB13

PB14

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

GPIO 20

GPIO 21

GPIO 22

GPIO 23

GPIO 24

GPIO 25

GPIO 26

GPIO 27

GPIO 28

GPIO 29

GPIO 30

GPIO 32

GPIO 33

GPIO 34

GPIO 35

GPIO 36

GPIO 37

GPIO 38

GPIO 39

GPIO 40

GPIO 41

GPIO 42

GPIO 43

GPIO 44

GPIO 45

GPIO 46

GPIO 47

GPIO 48

GPIO 49

GPIO 50

GPIO 51

GPIO 52

GPIO 53

GPIO 54

GPIO 55

EIM - EXTINT[8]

ADC - AD[0]

SPI1 - NPCS[3]

EIM - EXTINT[0]

EIM - EXTINT[1]

EIM - EXTINT[2]

EIM - EXTINT[3]

EIM - SCAN[0]

EIM - SCAN[1]

EIM - SCAN[2]

EIM - SCAN[3]

USART2 - RTS

USART2 - CTS

USART2 - RTS

USART2 - CTS

DAC - DATA[0]

DAC - DATAN[0]

USART3 - CLK

DAC - DATA[1]

DAC - DATAN[1]

USB - USB_ID

USB - USB_VBOF

DAC - DATA[1]

DAC - DATAN[1]

EBI - NCS[0]

74

ADC - AD[1]

75

ADC - AD[2]

76

ADC - AD[3]

77

ADC - AD[4]

78

ADC - AD[5]

EBI - ADDR[20]

EBI - ADDR[21]

EBI - ADDR[22]

79

ADC - AD[6]

80

ADC - AD[7]

122

123

88

TWI - SDA

TWI - SCL

MACB - TX_CLK

MACB - TX_EN

MACB - TXD[0]

MACB - TXD[1]

MACB - CRS

MACB - RXD[0]

MACB - RXD[1]

MACB - RX_ER

MACB - MDC

MACB - MDIO

MACB - TXD[2]

MACB - TXD[3]

MACB - TX_ER

MACB - RXD[2]

MACB - RXD[3]

MACB - RX_DV

MACB - COL

MACB - RX_CLK

MACB - SPEED

PWM - PWM[0]

PWM - PWM[1]

PWM - PWM[2]

PWM - PWM[3]

TC - A0

USART3 - RTS

USART3 - CTS

90

96

98

100

102

104

106

111

113

115

119

121

126

127

134

136

139

141

143

3

EBI - NCS[3]

USART3 - RXD

USART3 - TXD

TC - CLK0

EBI - SDCK

EBI - SDCKE

EBI - RAS

TC - CLK1

EBI - CAS

TC - CLK2

EBI - SDWE

USB - USB_ID

USB - USB_VBOF

ADC - TRIGGER

PM - GCLK[0]

EBI - SDA10

EBI - ADDR[23]

PWM - PWM[6]

EIM - SCAN[4]

EIM - SCAN[5]

EIM - SCAN[6]

EIM - SCAN[7]

PM - GCLK[1]

2

5

PM - GCLK[2]

3

6

PM - GCLK[3]

6

9

USART1 - DCD

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32058FS–AVR32–08/08

AT32UC3A

Table 10-9. GPIO Controller Function Multiplexing

7

11

13

14

15

19

20

21

22

85

86

124

125

132

133

1

PB24

PB25

PB26

PB27

PB28

PB29

PB30

PB31

PC00

PC01

PC02

PC03

PC04

PC05

PX00

PX01

PX02

PX03

PX04

PX05

PX06

PX07

PX08

PX09

PX10

PX11

PX12

PX13

PX14

PX15

PX16

PX17

PX18

PX19

PX20

PX21

PX22

PX23

PX24

GPIO 56

GPIO 57

GPIO 58

GPIO 59

GPIO 60

GPIO 61

GPIO 62

GPIO 63

GPIO 64

GPIO 65

GPIO 66

GPIO 67

GPIO 68

GPIO 69

GPIO 100

GPIO 99

GPIO 98

GPIO 97

GPIO 96

GPIO 95

GPIO 94

GPIO 93

GPIO 92

GPIO 91

GPIO 90

GPIO 109

GPIO 108

GPIO 107

GPIO 106

GPIO 89

GPIO 88

GPIO 87

GPIO 86

GPIO 85

GPIO 84

GPIO 83

GPIO 82

GPIO 81

GPIO 80

TC - B0

TC - A1

USART1 - DSR

USART1 - DTR

USART1 - RI

8

9

TC - B1

10

14

15

16

17

63

64

85

86

93

94

TC - A2

PWM - PWM[4]

PWM - PWM[5]

PM - GCLK[1]

PM - GCLK[2]

PM - GCLK[3]

TC - B2

USART2 - RXD

USART2 - TXD

USART2 - CLK

EBI - NCS[2]

EBI - SDCS

EBI - NWAIT

EBI - DATA[10]

EBI - DATA[9]

EBI - DATA[8]

EBI - DATA[7]

EBI - DATA[6]

EBI - DATA[5]

EBI - DATA[4]

EBI - DATA[3]

EBI - DATA[2]

EBI - DATA[1]

EBI - DATA[0]

EBI - NWE1

USART0 - RXD

USART0 - TXD

USART0 - CTS

USART0 - RTS

USART1 - RXD

USART1 - TXD

USART1 - CTS

USART1 - RTS

USART3 - RXD

USART3 - TXD

USART2 - RXD

USART2 - TXD

USART2 - CTS

USART2 - RTS

2

4

10

12

24

26

31

33

35

38

40

42

44

46

59

61

63

65

67

87

89

91

95

97

EBI - NWE0

EBI - NRD

EBI - NCS[1]

TC - A0

TC - B0

EBI - ADDR[19]

EBI - ADDR[18]

EBI - ADDR[17]

EBI - ADDR[16]

EBI - ADDR[15]

EBI - ADDR[14]

EBI - ADDR[13]

EBI - ADDR[12]

EBI - ADDR[11]

EBI - ADDR[10]

USART3 - RTS

USART3 - CTS

TC - A1

TC - B1

TC - A2

EIM - SCAN[0]

EIM - SCAN[1]

EIM - SCAN[2]

EIM - SCAN[3]

EIM - SCAN[4]

EIM - SCAN[5]

TC - B2

TC - CLK0

TC - CLK1

TC - CLK2

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Table 10-9. GPIO Controller Function Multiplexing

99

PX25

PX26

PX27

PX28

PX29

PX30

PX31

PX32

PX33

PX34

PX35

PX36

PX37

PX38

PX39

GPIO 79

GPIO 78

GPIO 77

GPIO 76

GPIO 75

GPIO 74

GPIO 73

GPIO 72

GPIO 71

GPIO 70

GPIO 105

GPIO 104

GPIO 103

GPIO 102

GPIO 101

EBI - ADDR[9]

EBI - ADDR[8]

EBI - ADDR[7]

EBI - ADDR[6]

EBI - ADDR[5]

EBI - ADDR[4]

EBI - ADDR[3]

EBI - ADDR[2]

EBI - ADDR[1]

EBI - ADDR[0]

EBI - DATA[15]

EBI - DATA[14]

EBI - DATA[13]

EBI - DATA[12]

EBI - DATA[11]

EIM - SCAN[6]

EIM - SCAN[7]

SPI0 - MISO

101

103

105

107

110

112

114

118

120

135

137

140

142

144

SPI0 - MOSI

SPI0 - SCK

SPI0 - NPCS[0]

SPI0 - NPCS[1]

SPI0 - NPCS[2]

SPI0 - NPCS[3]

SPI1 - MISO

SPI1 - MOSI

SPI1 - SCK

SPI1 - NPCS[0]

SPI1 - NPCS[1]

SPI1 - NPCS[2]

10.8 Oscillator Pinout

The oscillators are not mapped to the normal A,B or C functions and their muxings are controlled

by registers in the Power Manager (PM). Please refer to the power manager chapter for more

information about this.

Table 10-10. Oscillator pinout

TQFP100 pin

VQFP144 pin

Pad

Oscillator pin

xin0

85

93

63

86

94

64

124

132

85

PC02

PC04

PC00

PC03

PC05

PC01

xin1

xin32

125

133

86

xout0

xout1

xout32

10.9 USART Configuration

Table 10-11. USART Supported Mode

Manchester

Encoding

SPI

RS485

ISO7816

IrDA

Modem

USART0

USART1

USART2

USART3

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

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32058FS–AVR32–08/08

AT32UC3A

10.10 GPIO

The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is

not available for this device.

10.11 Peripheral overview

10.11.1 External Bus Interface

• Optimized for Application Memory Space support

• Integrates Two External Memory Controllers:

– Static Memory Controller

– SDRAM Controller

• Optimized External Bus:

– 16-bit Data Bus

– 24-bit Address Bus, Up to 16-Mbytes Addressable

– Optimized pin multiplexing to reduce latencies on External Memories

• 4 SRAM Chip Selects, 1SDRAM Chip Select:

– Static Memory Controller on NCS0

– SDRAM Controller or Static Memory Controller on NCS1

– Static Memory Controller on NCS2

– Static Memory Controller on NCS3

10.11.2 Static Memory Controller

• 4 Chip Selects Available

• 64-Mbyte Address Space per Chip Select

• 8-, 16-bit Data Bus

• Word, Halfword, Byte Transfers

• Byte Write or Byte Select Lines

• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

• Programmable Data Float Time per Chip Select

• Compliant with LCD Module

• External Wait Request

• Automatic Switch to Slow Clock Mode

• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

10.11.3 SDRAM Controller

• Numerous Configurations Supported

– 2K, 4K, 8K Row Address Memory Parts

– SDRAM with Two or Four Internal Banks

– SDRAM with 16-bit Data Path

• Programming Facilities

– Word, Half-word, Byte Access

– Automatic Page Break When Memory Boundary Has Been Reached

– Multibank Ping-pong Access

– Timing Parameters Specified by Software

– Automatic Refresh Operation, Refresh Rate is Programmable

• Energy-saving Capabilities

– Self-refresh, Power-down and Deep Power Modes Supported

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AT32UC3A

– Supports Mobile SDRAM Devices

• Error Detection

– Refresh Error Interrupt

• SDRAM Power-up Initialization by Software

• CAS Latency of 1, 2, 3 Supported

• Auto Precharge Command Not Used

10.11.4 USB Controller

• USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s

• 7 Pipes/Endpoints

• 960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints

• Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)

• Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels

• On-Chip Transceivers Including Pull-Ups

10.11.5 Serial Peripheral Interface

• Supports communication with serial external devices

– Four chip selects with external decoder support allow communication with up to 15

peripherals

– Serial memories, such as DataFlash and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays between consecutive transfers and between clock and data

per chip select

– Programmable delay between consecutive transfers

– Selectable mode fault detection

• Very fast transfers supported

– Transfers with baud rates up to Peripheral Bus A (PBA) max frequency

– The chip select line may be left active to speed up transfers on the same device

10.11.6 Two-wire Interface

• High speed up to 400kbit/s

• Compatibility with standard two-wire serial memory

• One, two or three bytes for slave address

• Sequential read/write operations

10.11.7 USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB- or LSB-first

– Optional break generation and detection

– By 8 or by-16 over-sampling receiver frequency

– Hardware handshaking RTS-CTS

– Receiver time-out and transmitter timeguard

– Optional Multi-drop Mode with address generation and detection

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– Optional Manchester Encoding

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• IrDA modulation and demodulation

– Communication at up to 115.2 Kbps

• Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

• SPI Mode

– Master or Slave

– Serial Clock Programmable Phase and Polarity

– SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency PBA/4

• Supports Connection of Two Peripheral DMA Controller Channels (PDC)

– Offers Buffer Transfer without Processor Intervention

10.11.8 Serial Synchronous Controller

• Provides serial synchronous communication links used in audio and telecom applications (with

CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)

• Contains an independent receiver and transmitter and a common clock divider

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of different

event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

10.11.9 Timer Counter

• Three 16-bit Timer Counter Channels

• Wide range of functions including:

– Frequency Measurement

– Event Counting

– Interval Measurement

– Pulse Generation

– Delay Timing

– Pulse Width Modulation

– Up/down Capabilities

• Each channel is user-configurable and contains:

– Three external clock inputs

– Five internal clock inputs

– Two multi-purpose input/output signals

• Two global registers that act on all three TC Channels

10.11.10 Pulse Width Modulation Controller

• 7 channels, one 20-bit counter per channel

• Common clock generator, providing Thirteen Different Clocks

– A Modulo n counter providing eleven clocks

– Two independent Linear Dividers working on modulo n counter outputs

• Independent channel programming

– Independent Enable Disable Commands

– Independent Clock

– Independent Period and Duty Cycle, with Double Bufferization

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

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10.11.11 Ethernet 10/100 MAC

• Compatibility with IEEE Standard 802.3

• 10 and 100 Mbits per second data throughput capability

• Full- and half-duplex operations

• MII or RMII interface to the physical layer

• Register Interface to address, data, status and control registers

• DMA Interface, operating as a master on the Memory Controller

• Interrupt generation to signal receive and transmit completion

• 28-byte transmit and 28-byte receive FIFOs

• Automatic pad and CRC generation on transmitted frames

• Address checking logic to recognize four 48-bit addresses

• Support promiscuous mode where all valid frames are copied to memory

• Support physical layer management through MDIO interface control of alarm and update

time/calendar data

10.11.12 Audio Bitstream DAC

• Digital Stereo DAC

• Oversampled D/A conversion architecture

– Oversampling ratio fixed 128x

– FIR equalization filter

– Digital interpolation filter: Comb4

– 3rd Order Sigma-Delta D/A converters

• Digital bitstream outputs

• Parallel interface

• Connected to Peripheral DMA Controller for background transfer without CPU intervention

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AT32UC3A

11. Boot Sequence

This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is

controlled by the Power Manager. For specific details, refer to Section 13. ”Power Manager

(PM)” on page 55.

11.1 Starting of clocks

After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the

power has stabilized throughout the device. Once the power has stabilized, the device will use

the internal RC Oscillator as clock source.

On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have

a divided frequency, all parts of the system recieves a clock with the same frequency as the

internal RC Oscillator.

11.2 Fetching of initial instructions

After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset

address, which is 0x8000_0000. This address points to the first address in the internal Flash.

The code read from the internal Flash is free to configure the system to use for example the

PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the

clocks to unused peripherals.

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12. Electrical Characteristics

12.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature......................................-40⋅C to +85⋅C

Storage Temperature.......................................................... ....-

60°C to +150°C

Voltage on Input Pin

with respect to Ground-O.3V to 5.5V

Maximum Operating Voltage (VDDCORE, VDDPLL)..... 1.95V

Maximum Operating Voltage (VDDIO).............................. 3.6V

Total DC Output Current on all I/O Pin

for TQFP100 packag ................................................... 370 mA

for LQGP144 package................................................. 470 mA

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32058FS–AVR32–08/08

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12.2 DC Characteristics

The following characteristics are applicable to the operating temperature range: T_A= -40°C to 85°C, unless otherwise spec-

ified and are certified for a junction temperature up to T_J= 100°C.

Symbol

Parameter

Condition

Min.

Typ.

Max

Units

V_VDDCOR

DC Supply Core

1.65

1.95

V

E

V_VDDPLL

V_VDDIO

V_REF

DC Supply PLL

1.65

3.0

1.95

3.6

V

DC Supply Peripheral I/Os

Analog reference voltage

Input Low-level Voltage

2.6

3.6

V_IL

-0.3

+0.8

All GPIOS except for PC00, PC01, PC02,

PC03, PC04, PC05.

2.0

5.5V

V

V_IH

Input High-level Voltage

PC00, PC01, PC02, PC03, PC04, PC05.

I_OL=-4mA

3.6V

0.4

V

V_OL

V_OH

Output Low-level Voltage

Output High-level Voltage

Input Leakage Current

V_VDDIO

0.4

-

I_OL=4mA

V

I_LEAK

C_IN

Input Capacitance

R_PULLUPPull-up Resistance

I_O

Pullup resistors disabled

TQFP100 Package

LQFP144 Package

1

µA

pF

7

pF

10K

Ohm

mA

Output Current

4

On V_VDDCORE= 1.8V,

T_A=25°C

TBD

µA

CPU is in static mode

I_SC

Static Current

All inputs driven;

T_A=85°C

TBD

10

TBD

RESET_N=1,

Static Current of internal

regulator

Low Power mode (stop,

T_A=25°C

I_SCR

deep stop or static

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32058FS–AVR32–08/08

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12.3 Regulator characteristics

12.3.1

Electrical characteristics

Symbol Parameter

Condition

Min. Typ. Max. Units

V_VDDIN

Supply voltage (input)

2.7

3.3

3.6

1.89

100

90

V

V_VDDOUTSupply voltage (output)

1.81 1.85

Maximum DC output current with V_{VDDIN = 3.3V}

mA

I_OUT

Maximum DC output current with V_{VDDIN = 2.7V}

12.3.2

Decoupling requirements

Symbol Parameter

Condition

Typ. Techno. Units

C_IN1

Input Regulator Capacitor 1

1

NPO

X7R

NPO

X7R

nF

uF

pF

uF

C_IN2

Input Regulator Capacitor 2

Output Regulator Capacitor 1

Output Regulator Capacitor 2

4.7

470

2.2

C_OUT1

C_OUT2

12.4 Analog characteristics

12.4.1

Electrical characteristics

Symbol Parameter

Condition

Min. Typ. Max. Units

V_ADVREF

Analog voltage reference (input)

2.6

3.6

V

12.4.2

Decoupling requirements

Symbol

C_VREF1

C_VREF2

Parameter

Condition

Typ.

10

Techno.

Units

nF

Voltage reference Capacitor 1

Voltage reference Capacitor 2

-

1

uF

12.4.3

BOD

Table 12-1. BODLEVEL Values

BODLEVEL Value

000000b

Typ.

1.58

1.62

1.67

1.77

1.92

Units.

V

010111b

011111b

100111b

111111b

The values in Table 12-1 describes the values of the BODLEVEL in the flash FGPFR register.

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12.5 Power Consumption

The values in Table 12-2 and Table 12-3 on page 43 are measured values of power consump-

tion with operating conditions as follows:

•V_DDIO= 3.3V

•V_DDCORE= V_DDPLL= 1.8V

•T^A= 25°C, TA = 85°C

•I/Os are inactive

Figure 12-1. Measurement setup

VDDANA

VDDIO

VDDIN

Amp0

Internal

Voltage

Regulator

VDDOUT

VDDCORE

Amp1

VDDPLL

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AT32UC3A

These figures represent the power consumption measured on the power supplies.

Table 12-2. Power Consumption for Different Modes⁽¹⁾

Consumption

Typ.

Mode

Conditions

Unit

mA

CPU running from flash.

CPU clocked from PLL0 at f MHz

f = 12 MHz

f = 24 MHz

f = 36MHz

f = 50 MHz

9

16

Voltage regulator is on.

XIN0 : external clock. ⁽¹⁾

XIN1 stopped. XIN32 stopped

PLL0 running

23

Active

31.5

All peripheral clocks activated.

GPIOs on internal pull-up.

JTAG unconnected with ext pull-up.

f = 60 MHz

on Amp0

37

25

mA

uA

Typ : Ta = 25 °C

CPU is in static mode

GPIOs on internal pull-up.

All peripheral clocks de-activated.

DM and DP pins connected to ground.

XIN0,Xin1 and XIN2 are stopped

Static

on Amp1

14

uA

1. Core frequency is generated from XIN0 using the PLL so that 140 MHz < fpll0 < 160 MHz and

10 MHz < fxin0 < 12MHz

Table 12-3. Power Consumption by Peripheral in Active Mode

Peripheral

GPIO

SMC

Consumption

Unit

37

10

4

SDRAMC

ADC

18

31

25

14

45

30

36

7

EBI

INTC

TWI

MACB

PDCA

PWM

RTC

µA/MHz

SPI

13

10

35

45

SSC

TC

USART

USB

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AT32UC3A

12.6 Clock Characteristics

These parameters are given in the following conditions:

• V_DDCORE= 1.8V

• Ambient Temperature = 25°C

12.6.1

CPU/HSB Clock Characteristics

Table 12-4. Core Clock Waveform Parameters

Symbol

1/(t_CPCPU

t_CPCPU

Parameter

Conditions

Min

Max

Units

MHz

ns

)

CPU Clock Frequency

CPU Clock Period

66

15,15

12.6.2

PBA Clock Characteristics

Table 12-5. PBA Clock Waveform Parameters

Symbol

1/(t_CPPBA

t_CPPBA

Parameter

Min

Max

Units

MHz

ns

)

PBA Clock Frequency

PBA Clock Period

66

15,15

12.6.3

PBB Clock Characteristics

Table 12-6. PBB Clock Waveform Parameters

Symbol

1/(t_CPPBB

t_CPPBB

Parameter

Min

Max

Units

MHz

ns

)

PBB Clock Frequency

PBB Clock Period

66

15,15

12.6.4

XIN Clock Characteristics

Table 12-7. XIN Clock Electrical Characteristics

Symbol

Parameter

Conditions

External clock

Crystal

Min

Max

Units

50

20

MHz

1/(t_CPXIN

)

XIN Clock Frequency

3

t_CHXIN

t_CLXIN

C_IN

XIN Clock High Half-period

XIN Clock Low Half-period

XIN Input Capacitance

0.4 x t_CPXIN

0.6 x t_CPXIN

TBD

pF

12.7 Crystal Oscillator Characteristis

The following characteristics are applicable to the operating temperature range: T_A= -40°C to 85°C and worst case of

power supply, unless otherwise specified.

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12.7.1

32 KHz Oscillator Characteristics

Table 12-8. 32 KHz Oscillator Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

32 768

60

Unit

Hz

%

1/(t_CP32KHz

)

Crystal Oscillator Frequency

Duty Cycle

40

6

50

C_L

t_ST

Equivalent Load Capacitance

12.5

pF

C_L= 6pF⁽¹⁾

C_L= 12.5pF⁽¹⁾

600

1200

Startup Time

ms

Active mode

1.8

0.1

µA

I_OSC

Current Consumption

Standby mode

Note:

1. C_Lis the equivalent load capacitance.

12.7.2

Main Oscillators Characteristics

Table 12-9. Main Oscillator Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1/(t_CPMAIN

)

Crystal Oscillator Frequency

0.45

16

MHz

Internal Load Capacitance

(C_L1= C_L2)

C_L1, C_L2

C_L

12

pF

Equivalent Load Capacitance

Duty Cycle

TBD

50

pF

%

40

60

t_ST

Startup Time

TBD

ms

µA

Active mode @TBD MHz

Standby mode @TBD V

I_OSC

Current Consumption

Notes: 1. C_Sis the shunt capacitance

12.7.3 PLL Characteristics

Table 12-10. Phase Lock Loop Characteristics

Symbol

F_OUT

Parameter

Conditions

Min

80

Typ

Max

240

Unit

MHz

mA

Output Frequency

Input Frequency

F_IN

TBD

active mode

I_PLL

Current Consumption

standby mode

µA

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32058FS–AVR32–08/08

AT32UC3A

12.8 ADC Characteristics

Table 12-11. Channel Conversion Time and ADC Clock

Parameter

Conditions

Min

Typ

Max

5

Units

MHz

µs

ADC Clock Frequency

Startup Time

10-bit resolution mode

8-bit resolution mode

Return from Idle Mode

8

20

Track and Hold Acquisition Time

Conversion Time

600

ns

ADC Clock = 5 MHz

ADC Clock = 8 MHz

ADC Clock = 5 MHz

ADC Clock = 8 MHz

2

µs

Conversion Time

1.25

384⁽¹⁾

533⁽²⁾

µs

Throughput Rate

kSPS

Throughput Rate

Notes: 1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for

conversion.

2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for

conversion.

Table 12-12. External Voltage Reference Input

Parameter

Conditions

Min

Typ

Max

VDDANA

250

Units

V

ADVREF Input Voltage Range

ADVREF Average Current

Current Consumption on VDDANA

2.6

On 13 samples with ADC Clock = 5 MHz

200

µA

TBD

mA

Table 12-13. Analog Inputs

Parameter

Min

Typ

Max

Units

Input Voltage Range

Input Leakage Current

Input Capacitance

0

V_ADVREF

TBD

17

µA

pF

Table 12-14. Transfer Characteristics

Parameter

Conditions

Min

Typ

Max

Units

Bit

Resolution

10

Absolute Accuracy

Integral Non-linearity

Differential Non-linearity

Offset Error

f=5MHz

0.8

0.5

LSB

0.35

0.3

-0.5

Gain Error

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32058FS–AVR32–08/08

AT32UC3A

12.9 EBI Timings

These timings are given for worst case process, T = 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance.

Table 12-15. SMC Clock Signal.

Symbol

Parameter

Max⁽¹⁾

Units

1/(t_CPSMC

)

SMC Controller Clock Frequency

1/(t_cpcpu

)

MHz

Note:

1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.

Table 12-16. SMC Read Signals with Hold Settings

Symbol

Parameter

Min

Units

NRD Controlled (READ_MODE = 1)

SMC₁

SMC₂

SMC₃

SMC₄

SMC₅

SMC₆

SMC₇

SMC₈

SMC₉

Data Setup before NRD High

Data Hold after NRD High

12

0

NRD High to NBS0/A0 Change⁽¹⁾

NRD High to NBS1 Change⁽¹⁾

NRD High to NBS2/A1 Change⁽¹⁾

NRD High to NBS3 Change⁽¹⁾

NRD High to A2 - A25 Change⁽¹⁾

NRD High to NCS Inactive⁽¹⁾

NRD Pulse Width

nrd hold length * t_CPSMC- 1.3

ns

(nrd hold length - ncs rd hold length) * t_CPSMC- 2.3

nrd pulse length * t_CPSMC- 1.4

NRD Controlled (READ_MODE = 0)

SMC₁₀

SMC₁₁

SMC₁₂

SMC₁₃

SMC₁₄

SMC₁₅

SMC₁₆

SMC₁₇

SMC₁₈

11.5

Data Setup before NCS High

Data Hold after NCS High

0

NCS High to NBS0/A0 Change⁽¹⁾

NCS High to NBS2/A1 Change⁽¹⁾

NCS High to NBS3 Change⁽¹⁾

NCS High to A2 - A25 Change⁽¹⁾

NCS High to NRD Inactive⁽¹⁾

NCS Pulse Width

ncs rd hold length * t_CPSMC- 2.3

ncs rd hold length * t_CPSMC- 4

ncs rd hold length - nrd hold length)* t_CPSMC- 1.3

ncs rd pulse length * t_CPSMC- 3.6

ns

Note:

1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.

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32058FS–AVR32–08/08

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Table 12-17. SMC Read Signals with no Hold Settings

Symbol

Parameter

Min

Units

NRD Controlled (READ_MODE = 1)

NRD Controlled (READ_MODE = 0)

SMC₁₉

SMC₂₀

Data Setup before NRD High

Data Hold after NRD High

13.7

1

ns

SMC₂₁

SMC₂₂

13.3

0

Data Setup before NCS High

Data Hold after NCS High

ns

Table 12-18. SMC Write Signals with Hold Settings

Symbol

Parameter

Min

Units

NRD Controlled (READ_MODE = 1)

SMC₂₃

SMC₂₄

SMC₂₅

SMC₂₆

SMC₂₉

SMC₃₀

SMC₃₁

SMC₃₂

SMC₃₃

Data Out Valid before NWE High

Data Out Valid after NWE High⁽¹⁾

NWE High to NBS0/A0 Change⁽¹⁾

NWE High to NBS1 Change⁽¹⁾

NWE High to NBS2/A1 Change⁽¹⁾

NWE High to NBS3 Change⁽¹⁾

NWE High to A2 - A25 Change⁽¹⁾

NWE High to NCS Inactive⁽¹⁾

NWE Pulse Width

(nwe pulse length - 1) * t_CPSMC- 0.9

nwe hold length * t_CPSMC- 6

nwe hold length * t_CPSMC- 1.9

nwe hold length * t_CPSMC- 1.7

ns

(nwe hold length - ncs wr hold length)* t_CPSMC- 2.9

nwe pulse length * t_CPSMC- 0.9

NRD Controlled (READ_MODE = 0)

SMC₃₄

SMC₃₅

SMC₃₆

Data Out Valid before NCS High

Data Out Valid after NCS High⁽¹⁾

NCS High to NWE Inactive⁽¹⁾

(ncs wr pulse length - 1)* t_CPSMC- 4.6

ncs wr hold length * t_CPSMC- 5.8

ns

(ncs wr hold length - nwe hold length)* t_CPSMC- 0.6

Note:

1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “nwe hold

length"

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Table 12-19. SMC Write Signals with No Hold Settings (NWE Controlled only).

Symbol

SMC₃₇

SMC₃₈

SMC₃₉

SMC₄₀

SMC₄₁

SMC₄₂

SMC₄₃

SMC₄₄

SMC₄₅

Parameter

Min

Units

NWE Rising to A2-A25 Valid

NWE Rising to NBS0/A0 Valid

NWE Rising to NBS1 Change

NWE Rising to A1/NBS2 Change

NWE Rising to NBS3 Change

NWE Rising to NCS Rising

Data Out Valid before NWE Rising

Data Out Valid after NWE Rising

NWE Pulse Width

5.4

5

ns

5

5.1

(nwe pulse length - 1) * t_CPSMC- 1.2

5

nwe pulse length * t_CPSMC- 0.9

Figure 12-2. SMC Signals for NCS Controlled Accesses.

SMC16

A2-A25

SMC12

SMC13

SMC14

SMC15

SMC12

SMC13

SMC14

SMC15

SMC12

SMC13

SMC14

SMC15

A0/A1/NBS[3:0]

NRD

SMC17

SMC18

NCS

SMC22

SMC10

SMC11

SMC21

SMC34

SMC35

D0 - D15

SMC36

NWE

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Figure 12-3. SMC Signals for NRD and NRW Controlled Accesses.

SMC37

SMC7

SMC31

A2-A25

SMC3

SMC4

SMC5

SMC6

SMC38

SMC39

SMC40

SMC41

SMC3

SMC4

SMC5

SMC6

SMC25

SMC26

SMC29

SMC30

A0/A1/NBS[3:0]

SMC42

SMC8

SMC32

NCS

NRD

SMC8

SMC9

SMC24

SMC19

SMC20

SMC23

SMC43

SMC44

SMC2

SMC1

D0 - D15

SMC45

SMC33

NWE

12.9.1

SDRAM Signals

These timings are given for 10 pF load on SDCK and 40 pF on other signals.

Table 12-20. SDRAM Clock Signal.

Symbol

Parameter

Max⁽¹⁾

1/(t_cpcpu

Units

1/(t_CPSDCK

)

SDRAM Controller Clock Frequency

)

MHz

Note:

1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the

HSB.

Table 12-21. SDRAM Clock Signal.

Symbol

Parameter

Min

7.4

3.2

7

Units

SDRAMC₁

SDRAMC₂

SDRAMC₃

SDRAMC₄

SDRAMC₅

SDRAMC₆

SDRAMC₇

SDRAMC₈

SDRAMC₉

SDRAMC₁₀

SDCKE High before SDCK Rising Edge

SDCKE Low after SDCK Rising Edge

SDCKE Low before SDCK Rising Edge

SDCKE High after SDCK Rising Edge

SDCS Low before SDCK Rising Edge

SDCS High after SDCK Rising Edge

RAS Low before SDCK Rising Edge

RAS High after SDCK Rising Edge

SDA10 Change before SDCK Rising Edge

SDA10 Change after SDCK Rising Edge

ns

2.9

7.5

1.6

7.2

2.3

7.6

1.9

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Table 12-21. SDRAM Clock Signal.

Symbol

Parameter

Min

6.2

2.2

6.3

2.4

7.4

1.9

6.4

2.2

9

Units

SDRAMC₁₁

SDRAMC₁₂

SDRAMC₁₃

SDRAMC₁₄

SDRAMC₁₅

SDRAMC₁₆

SDRAMC₁₇

SDRAMC₁₈

SDRAMC₁₉

SDRAMC₂₀

SDRAMC₂₃

SDRAMC₂₄

SDRAMC₂₅

SDRAMC₂₆

Address Change before SDCK Rising Edge

Address Change after SDCK Rising Edge

Bank Change before SDCK Rising Edge

Bank Change after SDCK Rising Edge

CAS Low before SDCK Rising Edge

CAS High after SDCK Rising Edge

DQM Change before SDCK Rising Edge

DQM Change after SDCK Rising Edge

D0-D15 in Setup before SDCK Rising Edge

D0-D15 in Hold after SDCK Rising Edge

SDWE Low before SDCK Rising Edge

SDWE High after SDCK Rising Edge

D0-D15 Out Valid before SDCK Rising Edge

D0-D15 Out Valid after SDCK Rising Edge

ns

0

7.6

1.8

7.1

1.5

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Figure 12-4. SDRAMC Signals relative to SDCK.

SDCK

SDRAMC

4

1

2

3

SDCKE

SDCS

RAS

SDRAMC

5

SDRAMC

6

5

6

5

6

7

8

SDRAMC

15

SDRAMC

16

15

16

CAS

SDRAMC

23

SDRAMC

24

SDWE

SDA10

SDRAMC SDRAMC

9

SDRAMC SDRAMC

9

10

12

14

10

12

14

18

10

12

14

18

SDRAMC

11

13

17

11

13

17

A0 - A9,

A11 - A13

13

BA0/BA1

DQM0 -

DQM3

SDRAMC

19

SDRAMC

20

D0 - D15

Read

SDRAMC

25

26

D0 - D15

to Write

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AT32UC3A

12.10 JTAG Timings

12.10.1 JTAG Interface Signals

Table 12-22. JTAG Interface Timing specification

Symbol

JTAG₀

JTAG₁

JTAG₂

JTAG₃

JTAG₄

JTAG₅

JTAG₆

JTAG₇

JTAG₈

JTAG₉

JTAG₁₀

Parameter

Conditions

Min

6

Max

Units

ns

(1)

TCK Low Half-period

TCK High Half-period

TCK Period

(1)

3

ns

9

ns

TDI, TMS Setup before TCK High

TDI, TMS Hold after TCK High

TDO Hold Time

1

ns

0

ns

4

ns

TCK Low to TDO Valid

Device Inputs Setup Time

Device Inputs Hold Time

Device Outputs Hold Time

TCK to Device Outputs Valid

6

ns

Note:

1. V_VDDIOfrom 3.0V to 3.6V, maximum external capacitor = 40pF

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Figure 12-5. JTAG Interface Signals

JTAG₂

TCK

JTAG

JTAG₁

0

TMS/TDI

JTAG₃

JTAG₄

TDO

JTAG₅

JTAG₆

Device

Inputs

JTAG₈

JTAG₇

Device

Outputs

JTAG₉

JTAG₁₀

12.11 SPI Characteristics

Figure 12-6. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)

SPCK

SPI₁

SPI₀

MISO

MOSI

SPI₂

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Figure 12-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)

SPCK

SPI₄

SPI₃

MISO

MOSI

SPI₅

Figure 12-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)

SPCK

SPI₆

MISO

SPI₇

SPI₈

MOSI

Figure 12-9. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)

SPCK

SPI₉

MISO

SPI₁₀

SPI₁₁

MOSI

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AT32UC3A

Table 12-23. SPI Timings

Symbol

SPI₀

SPI₁

SPI₂

SPI₃

SPI₄

SPI₅

SPI₆

SPI₇

SPI₈

SPI₉

SPI₁₀

SPI₁₁

Parameter

Conditions

Min

Max

Units

ns

MISO Setup time before SPCK rises (master)

MISO Hold time after SPCK rises (master)

SPCK rising to MOSI Delay (master)

MISO Setup time before SPCK falls (master)

MISO Hold time after SPCK falls (master)

SPCK falling to MOSI Delay (master)

SPCK falling to MISO Delay (slave)

MOSI Setup time before SPCK rises (slave)

MOSI Hold time after SPCK rises (slave)

SPCK rising to MISO Delay (slave)

MOSI Setup time before SPCK falls (slave)

MOSI Hold time after SPCK falls (slave)

3.3V domain⁽¹⁾

3.3V domain ⁽¹⁾

22 + (t_CPMCK)/2⁽²⁾

0

ns

7

ns

22 + (t_CPMCK)/2⁽²⁾

0

ns

7

ns

26.5

ns

0

ns

1.5

ns

27

ns

0

1

ns

Notes: 1. 3.3V domain: V_VDDIOfrom 3.0V to 3.6V, maximum external capacitor = 40 pF.

2. t_CPMCK: Master Clock period in ns.

12.12 MACB Characteristics

Table 12-24. Ethernet MAC Signals

Symbol

EMAC₁

EMAC₂

EMAC₃

Parameter

Conditions

Load: 20pF⁽²⁾

Min (ns)

Max (ns)

Setup for EMDIO from EMDC rising

Hold for EMDIO from EMDC rising

EMDIO toggling from EMDC falling

Notes: 1. f: MCK frequency (MHz)

2. V_VDDIOfrom 3.0V to 3.6V, maximum external capacitor = 20 pF

Table 12-25. Ethernet MAC MII Specific Signals

Symbol

EMAC₄

EMAC₅

EMAC₆

EMAC₇

EMAC₈

EMAC₉

EMAC₁₀

EMAC₁₁

Parameter

Conditions

Load: 20pF ⁽¹⁾

Min (ns)

Max (ns)

Setup for ECOL from ETXCK rising

Hold for ECOL from ETXCK rising

Setup for ECRS from ETXCK rising

Hold for ECRS from ETXCK rising

ETXER toggling from ETXCK rising

ETXEN toggling from ETXCK rising

ETX toggling from ETXCK rising

Setup for ERX from ERXCK

3

0

3

0

15

1

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AT32UC3A

Table 12-25. Ethernet MAC MII Specific Signals

Symbol

EMAC₁₂

EMAC₁₃

EMAC₁₄

EMAC₁₅

EMAC₁₆

Parameter

Conditions

Load: 20pF ⁽¹⁾

Min (ns)

Max (ns)

Hold for ERX from ERXCK

Setup for ERXER from ERXCK

Hold for ERXER from ERXCK

Setup for ERXDV from ERXCK

Hold for ERXDV from ERXCK

1.5

1

0.5

1.5

1

Note:

1. V_VDDIOfrom 3.0V to 3.6V, maximum external capacitor = 20 pF

Figure 12-10. Ethernet MAC MII Mode

EMDC

EMAC₃

EMAC₁

EMAC₂

EMDIO

ECOL

EMAC₄

EMAC₆

EMAC₅

EMAC₇

ECRS

ETXCK

EMAC₈

ETXER

ETXEN

ETX[3:0]

EMAC₉

EMAC₁₀

ERXCK

ERX[3:0]

ERXER

ERXDV

EMAC₁₁

EMAC₁₃

EMAC₁₅

EMAC₁₂

EMAC₁₄

EMAC₁₆

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Table 12-26. Ethernet MAC RMII Specific Signals

Symbol

EMAC₂₁

EMAC₂₂

EMAC₂₃

EMAC₂₄

EMAC₂₅

EMAC₂₆

EMAC₂₇

EMAC₂₈

Parameter

Min (ns)

Max (ns)

14.5

ETXEN toggling from EREFCK rising

ETX toggling from EREFCK rising

Setup for ERX from EREFCK

Hold for ERX from EREFCK

Setup for ERXER from EREFCK

Hold for ERXER from EREFCK

Setup for ECRSDV from EREFCK

Hold for ECRSDV from EREFCK

7

14.7

1.5

0

1.5

0

1.5

0

Figure 12-11. Ethernet MAC RMII Mode

EREFCK

EMAC₂₁

ETXEN

EMAC₂₂

ETX[1:0]

EMAC₂₃

EMAC₂₅

EMAC₂₇

EMAC₂₄

EMAC₂₆

EMAC₂₈

ERX[1:0]

ERXER

ECRSDV

12.13 Flash Characteristics

The following table gives the device maximum operating frequency depending on the field FWS

of the Flash FSR register. This field defines the number of wait states required to access the

Flash Memory.

Table 12-27. Flash Wait States

FWS

Read Operations

1 cycle

Maximum Operating Frequency (MHz)

0

1

33

66

2 cycles

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13. Mechanical Characteristics

13.1 Thermal Considerations

13.1.1

Thermal Data

Table 13-1 summarizes the thermal resistance data depending on the package.

Table 13-1. Thermal Resistance Data

Symbol

θ_JA

Parameter

Condition

Package

TQFP100

LQFP144

Typ

TBD

Unit

Junction-to-ambient thermal resistance Still Air

Junction-to-case thermal resistance

⋅C/W

θ_JC

θ_JA

Junction-to-ambient thermal resistance Still Air

Junction-to-case thermal resistance

⋅C/W

θ_JC

13.1.2

Junction Temperature

The average chip-junction temperature, T_J, in °C can be obtained from the following:

1. = T + (P × θ

T

)

JA

J

A

D

2. T_J= T_A+ (P_D× (θ_HEATSINK+ θ_JC))

where:

• θ_JA= package thermal resistance, Junction-to-ambient (°C/W), provided in Table 13-1 on page

59.

• θ_JC= package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in

Table 13-1 on page 59.

• θ_{HEAT SINK}= cooling device thermal resistance (°C/W), provided in the device datasheet.

• P_D= device power consumption (W) estimated from data provided in the section ”Power

Consumption” on page 42.

• T_A= ambient temperature (°C).

From the first equation, the user can derive the estimated lifetime of the chip and decide if a

cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second

equation should be used to compute the resulting average chip-junction temperature T_Jin °C.

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13.2 Package Drawings

Figure 13-1. TQFP-100 package drawing

Table 13-2. Device and Package Maximum Weight

TBD

mg

Table 13-3. Package Characteristics

Moisture Sensitivity Level

TBD

Table 13-4. Package Reference

JEDEC Drawing Reference

JESD97 Classification

MS-026

E3

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Figure 13-2. LQFP-144 package drawing

Table 13-5. Device and Package Maximum Weight

TBD

mg

Table 13-6. Package Characteristics

Moisture Sensitivity Level

TBD

Table 13-7. Package Reference

JEDEC Drawing Reference

JESD97 Classification

MS-026

E3

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13.3 Soldering Profile

Table 13-8 gives the recommended soldering profile from J-STD-20.

Table 13-8. Soldering Profile

Profile Feature

Green Package

TBD

Average Ramp-up Rate (217°C to Peak)

Preheat Temperature 175°C ±25°C

Temperature Maintained Above 217°C

Time within 5⋅C of Actual Peak Temperature

Peak Temperature Range

TBD

Ramp-down Rate

TBD

Time 25⋅C to Peak Temperature

TBD

Note:

It is recommended to apply a soldering temperature higher than 250°C.

A maximum of three reflow passes is allowed per component.

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14. Ordering Information

Table 14-1. Ordering Information

Temperature Operating

Range

Device

Ordering Code

Package

Conditioning

Tray

AT32UC3A0512

AT32UC3A0512-ALUT

AT32UC3A0512-ALUR

AT32UC3A0512-ALTR

AT32UC3A0512-ALTT

AT32UC3A0512-ALTES

144 lead LQFP

Industrial (-40⋅C to 85⋅C)

Automotive (-40⋅C to 85⋅C)

Reel

Tray

Automotive (-40⋅C to 85⋅C)

samples

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

AT32UC3A1128

AT32UC3A0256-ALUT

AT32UC3A0256-ALUR

AT32UC3A0128-ALUT

AT32UC3A0128-ALUR

AT32UC3A1512-AUT

AT32UC3A1512-AUR

AT32UC3A1256-AUT

AT32UC3A1256-AUR

AT32UC3A1128-AUT

AT32UC3A1128-AUR

144 lead LQFP

100 lead TQFP

Tray

Reel

Tray

Reel

Tray

Reel

Tray

Reel

Tray

Reel

Industrial (-40⋅C to 85⋅C)

14.1 Automotive Quality Grade

The AT32UC3A have been developed and manufactured according to the most stringent

requirements of the international standard ISO-TS-16949. This data sheet will contain limit val-

ues extracted from the results of extensive characterization (Temperature and Voltage). The

quality and reliability of the AT32UC3A is verified during regular product qualification as per

AEC-Q100 grade 3.

As indicated in the ordering information paragraph, the product is available in only one tempera-

ture grade T: -40°C / + 85°C.

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15. Errata

All industrial parts labelled with -UES (engineering samples) are revision E parts.

15.1 Rev. J

15.1.1

PWM

1. PWM channel interrupt enabling triggers an interrupt

When enabling a PWM channel that is configured with center aligned period (CALG=1), an

interrupt is signalled.

Fix/Workaround

When using center aligned mode, enable the channel and read the status before channel

interrupt is enabled.

2. PWM counter restarts at 0x0001

The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first

PWM period has one more clock cycle.

Fix/Workaround

- The first period is 0x0000, 0x0001, ..., period

- Consecutive periods are 0x0001, 0x0002, ..., period

3. PWM update period to a 0 value does not work

It is impossible to update a period equal to 0 by the using the PWM update register

(PWM_CUPD).

Fix/Workaround

Do not update the PWM_CUPD register with a value equal to 0.

15.1.2

15.1.3

ADC

1. Sleep Mode activation needs additional A to D conversion

If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode

before after the next AD conversion.

Fix/Workaround

Activate the sleep mode in the mode register and then perform an AD conversion.

SPI

1. SPI Slave / PDCA transfer: no TX UNDERRUN flag

There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to

be informed of a character lost in transmission.

Fix/Workaround

For PDCA transfer: none.

2. SPI FDIV option does not work

Selecting clock signal using FDIV = 1 does not work as specified.

Fix/Workaround

Do not set FDIV = 1.

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3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and

NCPHA=0

When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't

equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.

Fix/workaround

When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if

CPOL=1 and CPHA=0.

4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first

transfer

In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or

during the first transfer.

Fix/Workaround

1. Set slave mode, set required CPOL/CPHA.

2. Enable SPI.

3. Set the polarity CPOL of the line in the opposite value of the required one.

4. Set the polarity CPOL to the required one.

5. Read the RXHOLDING register.

Transfers can now befin and RXREADY will now behave as expected.

5. SPI Disable does not work in Slave mode

Fix/workaround

Read the last received data then perform a Software reset.

15.1.4

Power Manager

1. If the BOD level is higher than VDDCORE, the part is constantly under reset

If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will

be in constant reset.

Fix/Workaround

Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than

VDDCORE max and disable the BOD.

15.1.5

15.1.6

PDCA

TWI

1. Wrong PDCA behavior when using two PDCA channels with the same PID.

Fix/Workaround

The same PID should not be assigned to more than one channel.

1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.

Fix/Workaround

After a Software Reset, the register TWI RHR must be read.

15.1.7

SDRAMC

1. Code execution from external SDRAM does not work

Code execution from SDRAM does not work.

Fix/Workaround

Do not run code from SDRAM.

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15.1.8

Processor and Architecture

1. LDM instruction with PC in the register list and without ++ increments Rp

For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie

the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the

increment of the pointer is done in parallel with the testing of R12.

Fix/Workaround

None.

2. RETE instruction does not clear SREG[L] from interrupts.

The RETE instruction clears SREG[L] as expected from exceptions.

Fix/Workaround

When using the STCOND instruction, clear SREG[L] in the stacked value of SR before

returning from interrupts with RETE.

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15.2 Rev. I

15.2.1

PWM

1. PWM channel interrupt enabling triggers an interrupt

When enabling a PWM channel that is configured with center aligned period (CALG=1), an

interrupt is signalled.

Fix/Workaround

When using center aligned mode, enable the channel and read the status before channel

interrupt is enabled.

2. PWM counter restarts at 0x0001

The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first

PWM period has one more clock cycle.

Fix/Workaround

- The first period is 0x0000, 0x0001, ..., period

- Consecutive periods are 0x0001, 0x0002, ..., period

3. PWM update period to a 0 value does not work

It is impossible to update a period equal to 0 by the using the PWM update register

(PWM_CUPD).

Fix/Workaround

Do not update the PWM_CUPD register with a value equal to 0.

15.2.2

ADC

1. Sleep Mode activation needs additional A to D conversion

If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode

before after the next AD conversion.

Fix/Workaround

Activate the sleep mode in the mode register and then perform an AD conversion.

15.2.3

SPI

1. SPI Slave / PDCA transfer: no TX UNDERRUN flag

There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to

be informed of a character lost in transmission.

Fix/Workaround

For PDCA transfer: none.

2. SPI FDIV option does not work

Selecting clock signal using FDIV = 1 does not work as specified.

Fix/Workaround

Do not set FDIV = 1.

3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and

NCPHA=0

When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't

equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.

Fix/workaround

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When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if

CPOL=1 and CPHA=0.

4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first

transfer

In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or

during the first transfer.

Fix/Workaround

1. Set slave mode, set required CPOL/CPHA.

2. Enable SPI.

3. Set the polarity CPOL of the line in the opposite value of the required one.

4. Set the polarity CPOL to the required one.

5. Read the RXHOLDING register.

Transfers can now befin and RXREADY will now behave as expected.

5. SPI Disable does not work in Slave mode

Fix/workaround

Read the last received data then perform a Software reset.

15.2.4

Power Manager

1. If the BOD level is higher than VDDCORE, the part is constantly under reset

If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will

be in constant reset.

Fix/Workaround

Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than

VDDCORE max and disable the BOD.

15.2.5

Flashc

1. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP,

EP, EA, WUP, EUP commands may happen

- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a

given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the

other half of the flash may fail. This may lead to an exception or to other errors derived from

this corrupted read access.

- After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may

fail. This may lead to an exception or to other errors derived from this corrupted read access.

- After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading

(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to

an exception or to other errors derived from this corrupted read access.

Fix/Workaround

Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or

through the EBI. After these commands, read twice one flash page initialized to 00h in each

half part of the flash.

15.2.6

PDCA

1. Wrong PDCA behavior when using two PDCA channels with the same PID.

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Workaround/fix

The same PID should not be assigned to more than one channel.

15.2.7

GPIO

1. Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant

Only 11 GPIOs remain 5V tolerant (VIHmax=5V): PB01, PB02, PB03, PB10, PB19, PB20,

PB21, PB22, PB23, PB27, PB28.

Workaround/fix

None.

15.2.8

15.2.9

TWI

1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.

Fix/Workaround

After a Software Reset, the register TWI RHR must be read.

SDRAMC

1. Code execution from external SDRAM does not work

Code execution from SDRAM does not work.

Fix/Workaround

Do not run code from SDRAM.

15.2.10 Processor and Architecture

1. LDM instruction with PC in the register list and without ++ increments Rp

For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie

the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the

increment of the pointer is done in parallel with the testing of R12.

Fix/Workaround

None.

2. RETE instruction does not clear SREG[L] from interrupts.

The RETE instruction clears SREG[L] as expected from exceptions.

Fix/Workaround

When using the STCOND instruction, clear SREG[L] in the stacked value of SR before

returning from interrupts with RETE.

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15.3 Rev. H

15.3.1

PWM

1. PWM channel interrupt enabling triggers an interrupt

When enabling a PWM channel that is configured with center aligned period (CALG=1), an

interrupt is signalled.

Fix/Workaround

When using center aligned mode, enable the channel and read the status before channel

interrupt is enabled.

2. PWM counter restarts at 0x0001

The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first

PWM period has one more clock cycle.

Fix/Workaround

- The first period is 0x0000, 0x0001, ..., period

- Consecutive periods are 0x0001, 0x0002, ..., period

3. PWM update period to a 0 value does not work

It is impossible to update a period equal to 0 by the using the PWM update register

(PWM_CUPD).

Fix/Workaround

Do not update the PWM_CUPD register with a value equal to 0.

15.3.2

ADC

1. Sleep Mode activation needs additional A to D conversion

If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode

before after the next AD conversion.

Fix/Workaround

Activate the sleep mode in the mode register and then perform an AD conversion.

15.3.3

SPI

1. SPI Slave / PDCA transfer: no TX UNDERRUN flag

There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to

be informed of a character lost in transmission.

Fix/Workaround

For PDCA transfer: none.

2. SPI FDIV option does not work

Selecting clock signal using FDIV = 1 does not work as specified.

Fix/Workaround

Do not set FDIV = 1

3. SPI disable does not work in SLAVE mode.

Fix/Workaround

Read the last received data, then perform a Software Reset.

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4. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and

NCPHA=0

When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't

equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.

Fix/workaround

When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if

CPOL=1 and CPHA=0.

5. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first

transfer

In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or

during the first transfer.

Fix/Workaround

1. Set slave mode, set required CPOL/CPHA.

2. Enable SPI.

3. Set the polarity CPOL of the line in the opposite value of the required one.

4. Set the polarity CPOL to the required one.

5. Read the RXHOLDING register.

Transfers can now befin and RXREADY will now behave as expected.

6. SPI Disable does not work in Slave mode

Fix/workaround

Read the last received data then perform a Software reset.

15.3.4

Power Manager

1. Wrong reset causes when BOD is activated

Setting the BOD enable fuse will cause the Reset Cause Register to list BOD reset as the

reset source even though the part was reset by another source.

Fix/Workaround

Do not set the BOD enable fuse, but activate the BOD as soon as your program starts.

2. If the BOD level is higher than VDDCORE, the part is constantly under reset

If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will

be in constant reset.

Fix/Workaround

Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than

VDDCORE max and disable the BOD.

15.3.5

FLASHC

1. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP,

EP, EA, WUP, EUP commands may happen

- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a

given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the

other half of the flash may fail. This may lead to an exception or to other errors derived from

this corrupted read access.

- After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may

fail. This may lead to an exception or to other errors derived from this corrupted read access.

- After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading

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(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to

an exception or to other errors derived from this corrupted read access.

Fix/Workaround

Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or

through the EBI. After these commands, read twice one flash page initialized to 00h in each

half part of the flash.

15.3.6

15.3.7

15.3.8

PDCA

TWI

1. Wrong PDCA behavior when using two PDCA channels with the same PID.

Workaround/fix

The same PID should not be assigned to more than one channel.

1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.

Fix/Workaround

After a Software Reset, the register TWI RHR must be read.

SDRAMC

1. Code execution from external SDRAM does not work

Code execution from SDRAM does not work.

Fix/Workaround

Do not run code from SDRAM.

15.3.9

Processor and Architecture

1. LDM instruction with PC in the register list and without ++ increments Rp

For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie

the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the

increment of the pointer is done in parallel with the testing of R12.

Fix/Workaround

None.

2. RETE instruction does not clear SREG[L] from interrupts.

The RETE instruction clears SREG[L] as expected from exceptions.

Fix/Workaround

When using the STCOND instruction, clear SREG[L] in the stacked value of SR before

returning from interrupts with RETE.

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15.4 Rev. E

15.4.1

SPI

1. SPI FDIV option does not work

Selecting clock signal using FDIV = 1 does not work as specified.

Fix/Workaround

Do not set FDIV = 1.

2. SPI Slave / PDCA transfer: no TX UNDERRUN flag

There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to

be informed of a character lost in transmission.

Fix/Workaround

For PDCA transfer: none.

3. SPI Bad serial clock generation on 2nd chip select when SCBR=1, CPOL=1 and

CNCPHA=0

When multiple CS are in use, if one of the baudrate equals to 1 and one of the others

doesn’t equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on

SCK.

Fix/Workaround

When multiple CS are in use, if one of the baudrate equals to 1, the other must also equal 1

if CPOL=1 and CPHA=0.

4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first

transfer

In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or

during the first transfer.

Fix/Workaround

1. Set slave mode, set required CPOL/CPHA.

2. Enable SPI.

3. Set the polarity CPOL of the line in the opposite value of the required one.

4. Set the polarity CPOL to the required one.

5. Read the RXHOLDING register.

Transfers can now befin and RXREADY will now behave as expected.

5. SPI CSNAAT bit 2 in register CSR0...CSR3 is not available.

Fix/Workaround

Do not use this bit.

6. SPI disable does not work in SLAVE mode.

Fix/Workaround

Read the last received data, then perform a Software Reset.

7. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and

NCPHA=0

When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't

equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.

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Fix/workaround

When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if

CPOL=1 and CPHA=0.

15.4.2

PWM

1. PWM counter restarts at 0x0001

The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first

PWM period has one more clock cycle.

Fix/Workaround

- The first period is 0x0000, 0x0001, ..., period

- Consecutive periods are 0x0001, 0x0002, ..., period

2. PWM channel interrupt enabling triggers an interrupt

When enabling a PWM channel that is configured with center aligned period (CALG=1), an

interrupt is signalled.

Fix/Workaround

When using center aligned mode, enable the channel and read the status before channel

interrupt is enabled.

3. PWM update period to a 0 value does not work

It is impossible to update a period equal to 0 by the using the PWM update register

(PWM_CUPD).

Fix/Workaround

Do not update the PWM_CUPD register with a value equal to 0.

4. PWM channel status may be wrong if disabled before a period has elapsed

Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit

for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if

the channel was disabled before the period elapsed. It will then read '0' as expected.

Fix/Workaround

Reading the PWM channel status of a disabled channel is only correct after a PWM period

has elapsed.

15.4.3

SSC

1. SSC does not trigger RF when data is low

The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or

RCMR respectively.

Fix/Workaround

Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the PIO.

2. SSC Data is not sent unless clock is set as output

The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or

RCMR respectively.

Fix/Workaround

Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the PIO.

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15.4.4

USB

1. USB No end of host reset signaled upon disconnection

In host mode, in case of an unexpected device disconnection whereas a usb reset is being

sent by the usb controller, the UHCON.RESET bit may not been cleared by the hardware at

the end of the reset.

Fix/Workaround

A software workaround consists in testing (by polling or interrupt) the disconnection

(UHINT.DDISCI == 1) while waiting for the end of reset (UHCON.RESET == 0) to avoid

being stuck.

2. USBFSM and UHADDR1/2/3 registers are not available.

Do not use USBFSM register.

Fix/Workaround

Do not use USBFSM register and use HCON[6:0] field instead for all the pipes.

15.4.5

Processor and Architecture

1. Incorrect Processor ID

The processor ID reads 0x01 and not 0x02 as it should.

Fix/Workaround

None.

2. Bus error should be masked in Debug mode

If a bus error occurs during debug mode, the processor will not respond to debug com-

mands through the DINST register.

Fix/Workaround

A reset of the device will make the CPU respond to debug commands again.

3. Read Modify Write (RMW) instructions on data outside the internal RAM does not

work.

Read Modify Write (RMW) instructions on data outside the internal RAM does not work.

Fix/Workaround

Do not perform RMW instructions on data outside the internal RAM.

4. CRC calculation of a locked device will calculate CRC for 512 kB of flash memory,

even though the part has less flash.

Fix/Workaround

The flash address space is wrapping, so it is possible to use the CRC value by calculating

CRC of the flash content concatenated with itself N times. Where N is 512 kB/flash size.

5. Need two NOPs instruction after instructions masking interrupts

The instructions following in the pipeline the instruction masking the interrupt through SR

may behave abnormally.

Fix/Workaround

Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR.

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6. CPU Cycle Counter does not reset the COUNT system register on COMPARE match.

The device revision E does not reset the COUNT system register on COMPARE match. In

this revision, the COUNT register is clocked by the CPU clock, so when the CPU clock

stops, so does incrementing of COUNT.

Fix/Workaround

None.

7. Memory Protection Unit (MPU) is non functional.

Fix/Workaround

Do not use the MPU.

8. The following alternate GPIO function C are not available in revE

MACB-WOL on GPIO9 (PA09), MACB-WOL on GPIO18 (PA18), USB-USB_ID on GPIO21

(PA21), USB-USB_VBOF on GPIO22 (PA22), and all function B and C on GPIO70 to

GPIO101 (PX00 to PX39).

Fix/Workaround

Do not use these alternate B and C functions on the listed GPIO pins.

9.

Clock connection table on Rev E

Here is the table of Rev E

Figure 15-1. Timer/Counter clock connections on RevE

Source

Name

Connection

Internal

TIMER_CLOCK1

TIMER_CLOCK2

TIMER_CLOCK3

TIMER_CLOCK4

TIMER_CLOCK5

XC0

32 KHz Oscillator

PBA Clock / 4

PBA Clock / 8

PBA Clock / 16

PBA Clock / 32

External

XC1

XC2

10. Local Bus fast GPIO not available in RevE.

Fix/Workaround

Do not use on this silicon revision.

11. Spurious interrupt may corrupt core SR mode to exception

If the rules listed in the chapter `Masking interrupt requests in peripheral modules' of the

AVR32UC Technical Reference Manual are not followed, a spurious interrupt may occur. An

interrupt context will be pushed onto the stack while the core SR mode will indicate an

exception. A RETE instruction would then corrupt the stack..

Fix/Workaround

Follow the rules of the AVR32UC Technical Reference Manual. To increase software

robustness, if an exception mode is detected at the beginning of an interrupt handler,

change the stack interrupt context to an exception context and issue a RETE instruction.

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12. CPU cannot operate on a divided slow clock (internal RC oscillator)

Fix/Workaround

Do not run the CPU on a divided slow clock.

15.4.6

SDRAMC

1. Code execution from external SDRAM does not work

Code execution from SDRAM does not work.

Fix/Workaround

Do not run code from SDRAM.

2. SDRAM SDCKE rise at the same time as SDCK while exiting self-refresh mode

SDCKE rise at the same time as SDCK while exiting self-refresh mode.

Fix/Workaround

None.

15.4.7

USART

1. USART Manchester Encoder Not Working

Manchester encoding/decoding is not working.

Fix/Workaround

Do not use manchester encoding.

2. USART RXBREAK problem when no timeguard

In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0

and the break character is located just after the stop bit.

Fix/Workaround

If the NBSTOP is 1, timeguard should be different from 0.

3. USART Handshaking: 2 characters sent / CTS rises when TX

If CTS switches from 0 to 1 during the TX of a character, if the Holding register is not empty,

the TXHOLDING is also transmitted.

Fix/Workaround

None.

4. USART PDC and TIMEGUARD not supported in MANCHESTER

Manchester encoding/decoding is not working.

Fix/Workaround

Do not use manchester encoding.

5. USART SPI mode is non functional on this revision.

Fix/Workaround

Do not use the USART SPI mode.

6. DCD is active High instead of Low.

In modem mode the DCD signal is assumed to be active high by the USART, butshould

have been active low.

Fix/Workaround

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Add an external inverter to the DCD line.

15.4.8

Power Manager

1. Voltage regulator input and output is connected to VDDIO and VDDCORE inside the

device

The voltage regulator input and output is connected to VDDIO and VDDCORE respectively

inside the device.

Fix/Workaround

Do not supply VDDCORE externally, as this supply will work in paralell with the regulator.

2. Wrong reset causes when BOD is activated

Setting the BOD enable fuse will cause the Reset Cause Register to list BOD reset as the

reset source even though the part was reset by another source.

Fix/Workaround

Do not set the BOD enable fuse, but activate the BOD as soon as your program starts.

3. PLL0/1 Lock control does not work

Lock Control does not work for PLL0 and PLL1.

Fix/Workaround

In PLL0/1 Control register, the bit 7 should be set in order to prevent unexpected behaviour.

4. Peripheral Bus A maximum frequency is 33MHz instead of 66MHz.

Fix/Workaround

Do not set PBA frequency higher than 33 MHz.

5. PCx pins go low in stop mode

In sleep mode stop all PCx pins will be controlled by GPIO module instead of oscillators.

This can cause drive contention on the XINx in worst case.

Fix/Workaround

Before entering stop mode set all PCx pins to input and GPIO controlled.

6. On some rare parts, the maximum HSB and CPU speed is 50MHz instead of 66MHz.

Fix/Workaround

Do not set the HSB/CPU speed higher than 50MHz when the firmware generate exceptions.

7. If the BOD level is higher than VDDCORE, the part is constantly under reset

If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will

be in constant reset.

Fix/Workaround

Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than

VDDCORE max and disable the BOD.

8. System Timer mask (Bit 16) of the PM CPUMASK register is not available.

Fix/Workaround

Do not use this bit.

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15.4.9

HMatrix

1. HMatrix fixed priority arbitration does not work

Fixed priority arbitration does not work.

Fix/Workaround

Use Round-Robin arbitration instead.

15.4.10 ADC

1. ADC possible miss on DRDY when disabling a channel

The ADC does not work properly when more than one channel is enabled.

Fix/Workaround

Do not use the ADC with more than one channel enabled at a time.

2. ADC OVRE flag sometimes not reset on Status Register read

The OVRE flag does not clear properly if read simultaneously to an end of conversion.

Fix/Workaround

None.

3. Sleep Mode activation needs additional A to D conversion

If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode

before after the next AD conversion.

Fix/Workaround

Activate the sleep mode in the mode register and then perform an AD conversion.

15.4.11 ABDAC

15.4.12 FLASHC

1. Audio Bitstream DAC is not functional.

Fix/Workaround

Do not use the ABDAC on revE.

1. The address of Flash General Purpose Fuse Register Low (FGPFRLO) is 0xFFFE140C

on revE instead of 0xFFFE1410.

Fix/Workaround

None.

2. The command Quick Page Read User Page(QPRUP) is not functional.

Fix/Workaround

None.

3. PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0]

on revision E instead of WriteData[7:0], ByteAddress[2:0].

Fix/Workaround

None.

4. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP,

EP, EA, WUP, EUP commands may happen

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- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a

given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the

other half of the flash may fail. This may lead to an exception or to other errors derived from

this corrupted read access.

- After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may

fail. This may lead to an exception or to other errors derived from this corrupted read access.

- After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading

(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to

an exception or to other errors derived from this corrupted read access.

Fix/Workaround

Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or

through the EBI. After these commands, read twice one flash page initialized to 00h in each

half part of the flash.

15.4.13 RTC

1. Writes to control (CTRL), top (TOP) and value (VAL) in the RTC are discarded if the

RTC peripheral bus clock (PBA) is divided by a factor of four or more relative to the

HSB clock.

Fix/Workaround

Do not write to the RTC registers using the peripheral bus clock (PBA) divided by a factor of

four or more relative to the HSB clock.

2. The RTC CLKEN bit (bit number 16) of CTRL register is not available.

Fix/Workaround

Do not use the CLKEN bit of the RTC on Rev E.

15.4.14 OCD

1. Stalled memory access instruction writeback fails if followed by a HW breakpoint.

Consider the following assembly code sequence:

A

B

If a hardware breakpoint is placed on instruction B, and instruction A is a memory access

instruction, register file updates from instruction A can be discarded.

Fix/Workaround

Do not place hardware breakpoints, use software breakpoints instead.

Alternatively, place a hardware breakpoint on the instruction before the memory

access instruction and then single step over the memory access instruction.

15.4.15 PDCA

15.4.16 TWI

1. Wrong PDCA behavior when using two PDCA channels with the same PID.

Workaround/fix

The same PID should not be assigned to more than one channel.

1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.

Fix/Workaround

After a Software Reset, the register TWI RHR must be read.

15.4.17 Processor and Architecture

1. LDM instruction with PC in the register list and without ++ increments Rp

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For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie

the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the

increment of the pointer is done in parallel with the testing of R12.

Fix/Workaround

None.

2. RETE instruction does not clear SREG[L] from interrupts.

The RETE instruction clears SREG[L] as expected from exceptions.

Fix/Workaround

When using the STCOND instruction, clear SREG[L] in the stacked value of SR before

returning from interrupts with RETE.

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16. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

16.1 Rev. F – 08/08

1.

2.

Add revision J to ”Errata” on page 64.

Update DMIPS number in ”Features” on page 1.

16.2 Rev. E – 04/08

16.3 Rev. D – 04/08

1.

Open Drain Mode removed from ”General-Purpose Input/Output Controller (GPIO)”

on page 151.

1.

2.

Updated ”Signal Description List” on page 8. Removed RXDN and TXDN from

USART section.

Updated ”Errata” on page 64. Rev G replaced by rev H.

16.4 Rev. C – 10/07

1.

2.

Updated ”Signal Description List” on page 8. Removed RXDN and TXDN from

USART section.

Updated ”Errata” on page 64. Rev G replaced by rev H.

16.5 Rev. B – 10/07

1.

2.

3.

4.

Updated ”Features” on page 1.

Update ”Blockdiagram” on page 4 with local bus.

Updated ”Peripherals” on page 34 with local bus.

Add SPI feature in ”Universial Synchronous/Asynchronous Receiver/Transmitter

(USART)” on page 315.

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5.

6.

7.

Updated ”USB On-The-Go Interface (USBB)” on page 517.

Updated ”JTAG and Boundary Scan” on page 750 with programming procedure .

Add description for silicon Rev G.

16.6 Rev. A – 03/07

1.

Initial revision.

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Table of Contents

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4

Description ............................................................................................... 3

Configuration Summary .......................................................................... 4

Abbreviations ........................................................................................... 4

Blockdiagram ........................................................................................... 5

4.1Processor and architecture .......................................................................................6

5

6

7

Signals Description ................................................................................. 8

Package and Pinout ............................................................................... 13

Power Considerations ........................................................................... 16

7.1Power Supplies .......................................................................................................16

7.2Voltage Regulator ....................................................................................................17

7.3Analog-to-Digital Converter (A.D.C) reference. .......................................................18

8

9

I/O Line Considerations ......................................................................... 19

8.1JTAG pins ................................................................................................................19

8.2RESET_N pin ..........................................................................................................19

8.3TWI pins ..................................................................................................................19

8.4GPIO pins ................................................................................................................19

Memories ................................................................................................ 20

9.1Embedded Memories ..............................................................................................20

9.2Physical Memory Map .............................................................................................20

9.3Bus Matrix Connections ..........................................................................................21

10 Peripherals ............................................................................................. 23

10.1Peripheral address map ........................................................................................23

10.2CPU Local Bus Mapping .......................................................................................24

10.3Interrupt Request Signal Map ................................................................................26

10.4Clock Connections ................................................................................................28

10.5Nexus OCD AUX port connections .......................................................................29

10.6PDC handshake signals ........................................................................................29

10.7Peripheral Multiplexing on I/O lines .......................................................................30

10.8Oscillator Pinout ....................................................................................................33

10.9USART Configuration ............................................................................................33

10.10GPIO ...................................................................................................................34

I

32058FS–AVR32–08/08

10.11Peripheral overview .............................................................................................34

11 Boot Sequence ....................................................................................... 38

11.1Starting of clocks ...................................................................................................38

11.2Fetching of initial instructions ................................................................................38

12 Electrical Characteristics ...................................................................... 39

12.1Absolute Maximum Ratings* .................................................................................39

12.2DC Characteristics ................................................................................................40

12.3Regulator characteristics .......................................................................................41

12.4Analog characteristics ...........................................................................................41

12.5Power Consumption ..............................................................................................42

12.6Clock Characteristics .............................................................................................44

12.7Crystal Oscillator Characteristis ............................................................................44

12.8ADC Characteristics ..............................................................................................46

12.9EBI Timings ...........................................................................................................47

12.10JTAG Timings ......................................................................................................53

12.11SPI Characteristics ..............................................................................................54

12.12MACB Characteristics .........................................................................................56

12.13Flash Characteristics ...........................................................................................58

13 Mechanical Characteristics ................................................................... 59

13.1Thermal Considerations ........................................................................................59

13.2Package Drawings ................................................................................................60

13.3Soldering Profile ....................................................................................................62

14 Ordering Information ............................................................................. 63

14.1Automotive Quality Grade .....................................................................................63

15 Errata ....................................................................................................... 64

15.1Rev. J ....................................................................................................................64

15.2Rev. I .....................................................................................................................67

15.3Rev. H ...................................................................................................................70

15.4Rev. E ....................................................................................................................73

16 Datasheet Revision History .................................................................. 82

16.1Rev. F – 08/08 .......................................................................................................82

16.2Rev. E – 04/08 .......................................................................................................82

16.3Rev. D – 04/08 ......................................................................................................82

16.4Rev. C – 10/07 ......................................................................................................82

16.5Rev. B – 10/07 .......................................................................................................82

16.6Rev. A – 03/07 .......................................................................................................83

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32058FS–AVR32–08/08


型号：	AT32UC3A0256-ALUR
厂家：	ATMEL
描述：	AVR32 32-Bit Microcontroller AVR32 32位微控制器微控制器
文件：	总86页 (文件大小：1327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT32UC3A0256-ALUR [ATMEL]

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