AT40K05AL-1DQL [ATMEL]
Field Programmable Gate Array, 256 CLBs, 5000 Gates, CMOS, PQFP208, 28 X 28 MM, PLASTIC, MS-129FA-1, QFP-208;
| 型号： | AT40K05AL-1DQL |
| 厂家： | 
ATMEL |
| 描述： | Field Programmable Gate Array, 256 CLBs, 5000 Gates, CMOS, PQFP208, 28 X 28 MM, PLASTIC, MS-129FA-1, QFP-208 ATM 异步传输模式 栅 可编程逻辑 |
| 文件： | 总55页 (文件大小：1098K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Ultra High Performance
– System Speeds to 100 MHz
– Array Multipliers > 50 MHz
– 10 ns Flexible SRAM
– Internal Tri-state Capability in Each Cell
• FreeRAM™
– Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM
– 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells
• 128 - 384 PCI Compliant I/Os
– Programmable Output Drive
5K - 50K Gates
Coprocessor
FPGA with
– Fast, Flexible Array Access Facilitates Pin Locking
– Pin-compatible with XC4000, XC5200 FPGAs
• 8 Global Clocks
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
FreeRAM™
• Cache Logic® Dynamic Full/Partial Re-configurability In-System
– Unlimited Re-programmability via Serial or Parallel Modes
– Enables Adaptive Designs
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
– Enables Fast Vector Multiplier Updates
– QuickChange™ Tools for Fast, Easy Design Changes
• Pin-compatible Package Options
– Plastic Leaded Chip Carriers (PLCC)
– Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP)
• Industry-standard Design Tools
– Seamless Integration (Libraries, Interface, Full Back-annotation) with
Everest, Exemplar™, Mentor®, OrCAD®, Synopsys®, Verilog®, Viewlogic®,
Synplicity®
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-chip Partitioning
– Fast, Efficient Synthesis
– Over 75 Automatic Component Generators Create 1000s
of Reusable, Fully Deterministic Logic and RAM Functions
• Easy Migration to Atmel Gate Arrays for High Volume Production
• Supply Voltage 3.3V
• 5V I/O Tolerant
• Green (Pb/Halide-free/RoHS Compliant) Package Options Available
2818F–FPGA–07/06
Table 1. AT40KAL Family(1)
Device
AT40K05AL
AT40K10AL
10K - 20K
24 x 24
576
AT40K20AL
20K - 30K
32 x 32
1,024
AT40K40AL
40K - 50K
48 x 48
2,304
Usable Gates
Rows x Columns
Cells
5K - 10K
16 x 16
256
Registers
496(1)
2,048
128
954(1)
1,520(1)
3,048(1)
RAM Bits
4,608
8,192
18,432
I/O (Maximum)
192
256
384
Note:
1. Packages with FCK will have 8 less registers.
Description
The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with distributed
10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global
clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), auto-
matic component generators, and range in size from 5,000 to 50,000 usable gates. I/O
counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC
to 352-ball Square BGA, and support 3.3V designs.
The AT40KAL is designed to quickly implement high-performance, large gate count
designs through the use of synthesis and schematic-based tools used on a PC or Sun
platform. Atmel’s design tools provide seamless integration with industry standard tools
such as Synplicity, ModelSim, Exemplar and Viewlogic. See the “IDS Datasheet” avail-
able on the Atmel web site (http://www.atmel.com/atmel/acrobat/doc1421.pdf) for a list
of other supported tools.
The AT40KAL can be used as a coprocessor for high-speed (DSP/processor-based)
designs by implementing a variety of computation intensive, arithmetic functions. These
include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), con-
volvers, interpolators and discrete-cosine transforms (DCT) that are required for video
compression and decompression, encryption, convolution and other multimedia
applications.
Fast, Flexible and
Efficient SRAM
The AT40KAL FPGA offers a patented distributed 10 ns SRAM capability where the
RAM can be used without losing logic resources. Multiple independent, synchronous or
asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be
created using Atmel’s macro generator tool.
Fast, Efficient Array and The AT40KAL’s patented 8-sided core cell with direct horizontal, vertical and diagonal
cell-to-cell connections implements ultra fast array multipliers without using any busing
Vector Multipliers
resources. The AT40KAL’s Cache Logic capability enables a large number of design
coefficients and variables to be implemented in a very small amount of silicon, enabling
vast improvement in system speed at much lower cost than conventional FPGAs.
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AT40KAL Series FPGA
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AT40KAL Series FPGA
Cache Logic Design
The AT40KAL, AT6000 and FPSLIC families are capable of implementing Cache Logic
(dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building
adaptive logic and systems. As new logic functions are required, they can be loaded into
the logic cache without losing the data already there or disrupting the operation of the
rest of the chip; replacing or complementing the active logic. The AT40KAL can act as a
reconfigurable coprocessor.
Automatic Component
Generators
The AT40KAL FPGA family is capable of implementing user-defined, automatically gen-
erated, macros in multiple designs; speed and functionality are unaffected by the macro
orientation or density of the target device. This enables the fastest, most predictable and
efficient FPGA design approach and minimizes design risk by reusing already proven
functions. The Automatic Component Generators work seamlessly with industry stan-
dard schematic and synthesis tools to create the fastest, most efficient designs
available.
The patented AT40KAL series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable I/O.
Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to
3,048 registers. Pin locations are consistent throughout the AT40KAL series for easy
design migration in the same package footprint. The AT40KAL series FPGAs utilize a
reliable 0.35µ triple-metal, CMOS process and are 100% factory-tested. Atmel’s PC-
and workstation-based integrated development system (IDS) is used to create
AT40KAL series designs. Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance,
functional density and design flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean functions of (the same) three
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient communication over medium and
long distances.
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The Symmetrical
Array
At the heart of the Atmel architecture is a symmetrical array of identical cells,
see Figure 1. The array is continuous from one edge to the other, except for bus
repeaters spaced every four cells, see Figure 2 on page 5. At the intersection of each
repeater row and column there is a 32 x 4 RAM block accessible by adjacent buses.
The RAM can be configured as either a single-ported or dual-ported RAM(1), with either
synchronous or asynchronous operation.
Note:
1. The right-most column can only be used as single-port RAM.
Figure 1. Symmetrical Array Surrounded by I/O (AT40K20AL)(1)
= FreeRAM
= Repeater Row
= I/O Pad
= Repeater Column
= AT40K Cell
Note:
1. AT40KAL has registered I/Os. Group enable on every sector for tri-states on obufe’s.
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AT40KAL Series FPGA
Figure 2. Floor Plan (Representative Portion)(1)
RV
= Vertical Repeater
= Horizontal Repeater
RH
= Core Cell
RAM
RAM
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RAM
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RAM
RAM
RAM
RAM
Note:
1. Repeaters regenerate signals and can connect any bus to any other bus (all path-
ways are legal) on the same plane. Each repeater has connections to two adjacent
local-bus segments and two express-bus segments. This is done automatically using
the integrated development system (IDS) tool.
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The Busing Network
Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus
resources: a local-bus resource (the middle bus) and two express-bus (both sides)
resources. Bus resources are connected via repeaters. Each repeater has connections
to two adjacent local-bus segments and two express-bus segments. Each local-bus
segment spans four cells and connects to consecutive repeaters. Each express-bus
segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regener-
ate signals and can connect any bus to any other bus (all pathways are legal) on the
same plane. Although not shown, a local bus can bypass a repeater via a programma-
ble pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are
implemented through pass gates in the cell-bus interface. Express/Express turns are
implemented through separate pass gates distributed throughout the array.
Some of the bus resources on the AT40KAL are used as a dual-function resources.
Table 2 shows which buses are used in a dual-function mode and which bus plane is
used. The AT40KAL software tools are designed to accommodate dual-function buses
in an efficient manner.
Table 2. Dual-function Buses
Function
Type
Plane(s) Direction
Comments
Cell Output Enable
Local
5
Horizontal
and Vertical
RAM Output Enable Express
2
Vertical
Vertical
Vertical
Bus full length at array edge
Bus in first column to left of
RAM block
RAM Write Enable
RAM Address
Express
Express
1
Bus full length at array edge
Bus in first column to left of
RAM block
1 - 5
Buses full length at array edge
Buses in second column to left
of RAM block
RAM Data In
Local
Local
1
2
Horizontal
Horizontal
Data In connects to local
bus plane 1
RAM Data Out
Data out connects to local
bus plane 2
Clocking
Express
Express
4
5
Vertical
Vertical
Bus half length at array edge
Bus half length at array edge
Set/Reset
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Figure 3. Busing Plane (One of Five)
= AT40KAL Core Cell
= Local/Local or Express/Express Turn Point
= Row Repeater
= Column Repeater
Express
Bus
Express
Bus
Local
Bus
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2818F–FPGA–07/06
Cell Connections
Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.
Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per
busing plane) and five vertical local buses (1 per busing plane).
Figure 4. Cell Connections
CELL
CELL
CELL
CELL
CELL
CELL
CELL
⎧
⎨
Plane 5⎩
⎫
⎪
⎬
⎪
⎭
⎧
⎨
Plane 4⎩
Horizontal
Busing Plane
⎧
⎨
Plane 3⎩
⎧
⎨
Plane 2⎩
⎧
⎨
Plane 1⎩
WXYZL
CELL
W
X
Y
Z
CELL
L
Vertical
Busing Plane
Diagonal
Direct Connect
CELL
Orthogonal
Direct Connect
(a) Cell-to-cell Connections
(b) Cell-to-bus Connections
The Cell
Figure 5 depicts the AT40KAL cell. Configuration bits for separate muxes and pass
gates are independent. All permutations of programmable muxes and pass gates are
legal. Vn (V1 - V5) is connected to the vertical local bus in plane n. Hn (H1 - H5) is con-
nected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by
turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let sig-
nals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming
into the logic cell on one local bus plane can be switched onto another plane by opening
two of the pass gates. This allows bus signals to switch planes to achieve greater route
ability. Up to five simultaneous local/local turns are possible.
The AT40KAL FPGA core cell is a highly configurable logic block based around two 3-
input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This
means that any core cell can implement two functions of 3 inputs or one function of 4
inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-stated
and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every
cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an impor-
tant feature in the implementation of efficient array multipliers.
With this functionality in each core cell, the core cell can be configured in several
“modes”. The core cell flexibility makes the AT40KAL architecture well suited to most
digital design application areas, see Figure 6.
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AT40KAL Series FPGA
Figure 5. The Cell
"1"
N
E
S
Y
W
"1" NW NE SE SW
"1"
X
W
Z
X
W
Y
FB
8X1 LUT
OUT
8X1 LUT
OUT
"1"
"0" "1"
V1
H1
V2
H2
V3
H3
V4
H4
V5
H5
Pass gates
1
0
Z
L
"1" OE OE
H
V
D
Q
CLOCK
RESET/SET
Y
X
NW NE SE SW
N
E
S
W
X
Y
= Diagonal Direct Connect or Bus
= Orthogonal Direct Connect or Bus
W = Bus Connection
= Bus Connection
FB = Internal Feedback
Z
9
2818F–FPGA–07/06
Figure 6. Some Single Cell Modes
Synthesis Mode. This mode is particularly important for
the use of VHDL/Verilog design. VHDL/Verilog Synthesis
tools generally will produce as their output large amounts
of random logic functions. Having a 4-input LUT structure
gives efficient random logic optimization without the
delays associated with larger LUT structures. The output
of any cell may be registered, tri-stated and/or fed back
into a core cell.
A
B
Q (Registered)
and/or
Q
D Q
C
D
SUM
or
Arithmetic Mode is frequently used in many designs.
As can be seen in the figure, the AT40KAL core cell can
implement a 1-bit full adder (2-input adder with both Carry
In and Carry Out) in one core cell. Note that the sum
output in this diagram is registered. This output could then
be tri-stated and/or fed back into the cell.
A
B
C
D Q
SUM (Registered)
and/or
CARRY
DSP/Multiplier Mode. This mode is used to efficiently
implement array multipliers. An array multiplier is an array
of bitwise multipliers, each implemented as a full adder
with an upstream AND gate. Using this AND gate and the
diagonal interconnects between cells, the array multiplier
structure fits very well into the AT40KAL architecture.
PRODUCT (Registered)
or
PRODUCT
D Q
A
B
C
D
and/or
CARRY
Counter Mode. Counters are fundamental to almost all
digital designs. They are the basis of state machines,
timing chains and clock dividers. A counter is essentially
an increment by one function (i.e., an adder), with the
input being an output (or a decode of an output) from the
previous stage. A 1-bit counter can be implemented in one
core cell. Again, the output can be registered, tri-stated
and/or fed back.
D Q
Q
CARRY IN
and/or
CARRY
Tri-state/Mux Mode. This mode is used in many
telecommunications applications, where data needs to be
routed through more than one possible path. The output of
the core cell is very often tri-statable for many inputs to
many outputs data switching.
A
B
C
Q
EN
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AT40KAL Series FPGA
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AT40KAL Series FPGA
RAM
32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit
Input Data Bus connects to four horizontal local buses distributed over four sector rows
(plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed
over four sector rows (plane 2). A 5-bit Input Address Bus connects to five vertical
express buses in the same column. A 5-bit Output Address Bus connects to five vertical
express buses in the same column. Ain (input address) and Aout (output address)
alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,
Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the
left and Aout is tied off, thus it can only be configured as a single port. For single-ported
RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN
connect to the vertical express buses in the same column.
Figure 7. RAM Connections (One Ram Block)
CLK
CLK
CLK
CLK
Din
Dout
Aout
32 x 4 RAM
Ain
WEN
OEN
CLK
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Reading and writing of the 10 ns 32 x 4 dual-port FreeRAM are independent of each
other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are
transparent; when Load is logic 1, data flows through; when Load is logic 0, data is
latched. These latches are used to synchronize Write Address, Write Enable Not, and
Din signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a trans-
parent latch. The front-end latch and the memory latch together form an edge-triggered
flip flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is
logic 0, data flows through the bit. When a nibble is not (Write) addressed or LOAD is
logic 0 or WE is logic 1, data is latched in the nibble. The two CLOCK muxes are con-
trolled together; they both select CLOCK (for a synchronous RAM) or they both select
“1” (for an asynchronous RAM). CLOCK is obtained from the clock for the sector-column
immediately to the left and immediately above the RAM block. Writing any value to the
RAM clear byte during configuration clears the RAM (see the “AT40K/40KAL Configura-
tion Series” application note at www.atmel.com).
Figure 8. RAM Logic
CLOCK
“1”
“1”
0
1
1
0
Load
5
5
Read Address
Write Address
Ain
Aout
WEN
Din
Load
Latch
32 x 4
Dual-port
RAM
“1”
OE
Load
Latch
Write Enable NOT
Load
Latch
4
4
Din
Dout
Dout
Clear
RAM-Clear Byte
Figure 9 on page 13 shows an example of a RAM macro constructed using the
AT40KAL’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous
RAM. Note the very small amount of external logic required to complete the address
decoding for the macro. Most of the logic cells (core cells) in the sectors occupied by the
RAM will be unused: they can be used for other logic in the design. This logic can be
automatically generated using the macro generators.
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AT40KAL Series FPGA
Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous)
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Clocking Scheme
There are eight Global Clock buses (GCK1 - GCK8) on the AT40KAL FPGA. Each of
the eight dedicated Global Clock buses is connected to one of the dual-use Global
Clock pins. Any clocks used in the design should use global clocks where possible: this
can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations.
In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4), two per
edge column of the array for PCI specification. For AT40KAL FPGAs, even the derived
clocks can be routed through the Global network. Access points are provided in the cor-
ners of the array to route the derived clocks into the global clock network. The IDS
software tools handle derived clocks to global clock connections automatically if used.
Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Col-
umn Clock mux is at the top of every column of an array and the Sector Clock mux is at
every four cells. The Column Clock mux is selected from one of the eight Global Clock
buses. The clock provided to each sector column of four cells is inverted, non-inverted
or tied off to “0”, using the Sector Clock mux to minimize the power consumption in a
sector that has no clocks. The clock can either come from the Column Clock or from the
Plane 4 express bus, see Figure 10 on page 15. The extreme-left Column Clock mux
has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The
extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to
provide fast clocking to right-side I/Os.
The register in each cell is triggered on a rising clock edge by default. Before configura-
tion on power-up, constant “0” is provided to each register’s clock pins. After
configuration on power-up, the registers either set or reset, depending on the user’s
choice.
The clocking scheme is designed to allow efficient use of multiple clocks with low clock
skew, both within a column and across the core cell array.
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AT40KAL Series FPGA
Figure 10. Clocking (for One Column of Cells)
}
⎫
⎬
⎭
FCK (2 per Edge Column of the Array)
GCK1 - GCK8
Column Clock Mux
“1”
Sector Clock Mux
Global Clock Line
(Buried)
Express Bus
(Plane 4; Half Length at Edge)
“1”
“1”
“1”
Repeater
Sector Clock Mux
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Set/Reset Scheme
The AT40KAL family reset scheme is essentially the same as the clock scheme except
that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by
any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The auto-
matic placement tool will choose the reset net with the most connections to use the
global resources. You can change this by using an RSBUF component in your design to
indicate the global reset. Additional resets will use the express bus network.
The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux,
there is Sector Set/Reset mux at every four cells. Each sector column of four cells is
set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux,
see Figure 11 on page 17. The set/reset provided to each sector column of four cells is
either inverted or non-inverted using the Sector Reset mux.
The function of the Set/Reset input of a register is determined by a configuration bit in
each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or
Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a
high) is provided by each register (i.e., all registers are set at power-up).
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AT40KAL Series FPGA
Figure 11. Set/Reset (for One Column of Cells)
Each Cell has a Programmable Set or Reset
Sector Set/Reset Mux
Repeater
“1”
“1”
“1”
Global Set/Reset Line (Buried)
Express Bus
(Plane 5; Half Length at Edge)
“1”
Any User I/O can Drive Global Set/Reset Lone
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I/O Structure
The AT40KAL has registered I/Os and group enable every sector for tri-states on obuf’s.
PAD
The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os
have pads: the ones without pads are called Unbonded I/Os. The number of unbonded
I/Os varies with the device size and package. These unbonded I/Os are used to perform
a variety of bus turns at the edge of the array.
PULL-UP/PULL-DOWN
Each pad has a programmable pull-up and pull-down attached to it. This supplies a
weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate
the signal level of the pad pin.
The input stage of each I/O cell has a number of parameters that can be programmed
either as properties in schematic entry or in the I/O Pad Attributes editor in IDS.
CMOS
The threshold level is a CMOS-compatible level.
SCHMITT
A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenera-
tive comparator circuit that adds 1V hysteresis to the input. This effectively improves the
rise and fall times (leading and trailing edges) of the incoming signal and can be useful
for filtering out noise.
DELAYS
DRIVE
The input buffer can be programmed to include four different intrinsic delays as specified
in the AC timing characteristics. This feature is useful for meeting data hold require-
ments for the input signal.
The output drive capabilities of each I/O are programmable. They can be set to FAST,
MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability
(20 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive
(14 mA at 5V) buffer, while SLOW yields a standard (6 mA at 5V) buffer.
TRI-STATE
The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open
drain (0 or Z) by programming an I/O’s Source Selection mux. Of course, the output can
be normal (0 or 1), as well.
SOURCE SELECTION MUX
The Source Selection mux selects the source for the output signal of an I/O.
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AT40KAL Series FPGA
Primary, Secondary and The AT40KAL has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O.
Every edge cell except corner cells on the AT40KAL has access to one Primary I/O and
two Secondary I/Os.
Corner I/Os
Primary I/O
Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and
from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It
also connects into the repeaters on the row immediately above and below the adjacent
core cell. In addition, each Primary I/O also connects into the busing network of the
three nearest edge cells. This is an extremely powerful feature, as it provides logic cells
toward the center of the array with fast access to I/Os via local and express buses. It can
be seen from the diagram that a given Primary I/O can be accessed from any logic cell
on three separate rows or columns of the FPGA. See Figure 12 on page 20.
Secondary I/O
Every logic cell at the edge of the FPGA array has two direct diagonal connections to a
Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O
connects on the diagonal inputs to the cell above and the cell below. It also connects to
the repeater of the cell above and below. In addition, each Secondary I/O also connects
into the busing network of the two nearest edge cells. This is an extremely powerful fea-
ture, as it provides logic cells toward the center of the array with fast access to I/Os via
local and express buses. It can be seen from the diagram that a given Secondary I/O
can be accessed from any logic cell on two rows or columns of the FPGA. See
Figure 13 on page 20.
Corner I/O
Logic cells at the corner of the FPGA array have direct-connect access to five separate
I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary
I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KAL FPGA
with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be
accessed both from the corner logic cell and the horizontal and vertical busing networks
running along the edges of the array. This means that many different edge logic cells
can access the Corner I/Os. See Figure 14 on page 21.
19
2818F–FPGA–07/06
Figure 12. West Primary I/O (Mirrored for East I/O)
CELL
"0"
"1"
PULL-UP
PAD
"0"
"1"
OCLK
CELL
PULL-DOWN
CELL
Figure 13. West Secondary I/O (Mirrored for East I/O)
"0"
"1"
CELL
PULL-UP
"0"
"1"
PAD
PULL-DOWN
CELL
20
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners)
PAD
PAD
VCC
GND
VCC
GND
TTL/CMOS
DRIVE
TTL/CMOS
SCHMITT
DELAY
DRIVE
TRI-STATE
SCHMITT
DELAY
TRI-STATE
ICLK
ICLK
OCLK
RST
OCLK
RST
RST
RST
RST
"0"
"1"
PULL-UP
PAD
"0"
"1"
CELL
CELL
PULL-DOWN
CELL
21
2818F–FPGA–07/06
Absolute Maximum Ratings – 3.3V Commercial/Industrial*
*NOTICE:
Stresses beyond those listed under Absolute
Operating Temperature.................................. -55°C to +125°C
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.................................-0.5V to VCC +7V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............250°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
DC and AC Operating Range – 3.3V Operation
Commercial
Industrial
-40°C - 85°C
3.3V 0.3V
Operating Temperature (Case)
VCC Power Supply
0°C - 70°C
3.3V 0.3V
High (VIHC
)
70% - 100% VCC
0 - 30% VCC
70% - 100% VCC
0 - 30% VCC
Input Voltage Level (CMOS)
Low (VILC
)
22
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
DC Characteristics – 3.3V Operation Commercial/Industrial
Symbol
Parameter
Conditions
Minimum
0.7 VCC
-0.3
Typical
Maximum
5.5V
Units
VIH
High-level Input Voltage
Low-level Input Voltage
CMOS
V
V
V
VIL
CMOS
30% VCC
I
OH = 4 mA
2.1
VCC = VCC minimum
I
OH = 12 mA
2.1
2.1
V
V
V
V
V
VOH
High-level Output Voltage
Low-level Output Voltage
VCC = 3.0V
I
OH = 16 mA
VCC = 3.0V
I
OL = -4 mA
0.4
0.4
0.4
VCC = 3.0V
I
OL = -12 mA
VOL
VCC = 3.0V
I
OL = -16 mA
VCC = 3.0V
V
IN = VCC Maximum
With pull-down, VIN = VCC
IN = VSS
10.0
µA
µA
µA
µA
µA
IIH
High-level Input Current
Low-level Input Current
75.0
-10.0
-300.0
150.0
300.0
V
IIL
With pull-up, VIN = VSS
-150.0
-75.0
10.0
Without pull-down,
VIN = VCC Maximum
High-level Tri-state Output
Leakage Current
IOZH
With pull-down,
75.0
150.0
300.0
µA
VIN = VCC Maximum
Without pull-up, VIN = VSS
With pull-up, VIN = VSS
-10.0
mA
Low-level Tri-state Output
Leakage Current
IOZL
CON = -500 µA
TO -125 µA
-150.0
0.6
CON = -500 µA
TO -125 µA
µA
ICC
Standby Current
Consumption
Standby, unprogrammed
1.0
mA
CIN
Input Capacitance
All pins
10.0
pF
Note:
1. Parameter based on characterization and simulation; it is not tested in production.
23
2818F–FPGA–07/06
Power-On Power
Supply Requirements
Atmel FPGAs require a minimum rated power supply current capacity to insure proper
initialization, and the power supply ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up time.
Table 3. Power-On Power Supply Requirements(1)
Device
Description
Maximum Current(2)(3)
AT40K05AL
AT40K10AL
Maximum Current Supply
50 mA
AT40K20AL
AT40K40AL
Maximum Current Supply
100 mA
Notes: 1. This specification applies to Commercial and Industrial grade products only.
2. Devices are guaranteed to initialize properly at 50% of the minimum current listed
above. A larger capacity power supply may result in a larger initialization current.
3. Ramp-up time is measured from 0 V DC to 3.6 V DC. Peak current required lasts less
than 2 ms, and occurs near the internal power on reset threshold voltage.
24
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.00V, temperature = 70°C
Minimum times based on best case: VCC = 3.60V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
Cell Function
Core
Parameter
Path
-1
Units
Notes
2-input Gate
3-input Gate
3-input Gate
4-input Gate
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
DFF
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
x/y -> x/y
x/y/z -> x/y
x/y/w -> x/y
x/y/w/z -> x/y
y -> y
1.8
2.1
2.2
2.2
1.4
1.7
1.8
1.5
2.2
2.3
2.3
1.7
1.8
2.2
2.2
1.8
1.5
1.4
1.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
t
PD (Maximum)
tPD (Maximum)
tPD (Maximum)
x -> y
t
PD (Maximum)
y -> x
tPD (Maximum)
tPD (Maximum)
x -> x
w -> y
t
PD (Maximum)
w -> x
tPD (Maximum)
tPD (Maximum)
z -> y
z -> x
t
PD (Maximum)
q -> x/y
R -> x/y
S -> x/y
q -> w
DFF
tPD (Maximum)
tPD (Maximum)
DFF
DFF
tPD (Maximum)
Incremental -> L
Local Output Enable
Local Output Enable
tPD (Maximum)
tPZX (Maximum)
x/y -> L
oe -> L
oe -> L
1 unit load
1 unit load
tPXZ (Maximum)
25
2818F–FPGA–07/06
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of
VDD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD.
Cell Function
Repeaters
Repeater
Repeater
Repeater
Repeater
Repeater
Repeater
Parameter
Path
-1
Units
Notes
t
PD (Maximum)
L -> E
E -> E
L -> L
1.3
1.3
1.3
1.3
0.8
0.8
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
tPD (Maximum)
tPD (Maximum)
t
PD (Maximum)
E -> L
E -> IO
L -> IO
tPD (Maximum)
tPD (Maximum)
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of
DD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD
V
.
Cell Function
Parameter
Path
-1
Units
Notes
IO
Input
tPD (Maximum)
pad -> x/y
pad -> x/y
pad -> x/y
pad -> x/y
x/y/E/L -> pad
x/y/E/L -> pad
x/y/E/L -> pad
oe -> pad
1.2
3.6
7.3
10.8
5.9
4.8
3.9
6.2
1.3
4.8
1.9
3.7
1.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No extra delay
1 extra delay
2 extra delays
3 extra delays
50 pf load
Input
tPD (Maximum)
Input
tPD (Maximum)
tPD (Maximum)
Input
Output, Slow
Output, Medium
Output, Fast
Output, Slow
Output, Slow
Output, Medium
Output, Medium
Output, Fast
Output, Fast
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
50 pf load
50 pf load
t
PZX (Maximum)
50 pf load
tPXZ (Maximum)
tPZX (Maximum)
oe -> pad
50 pf load
oe -> pad
50 pf load
t
PXZ (Maximum)
oe -> pad
50 pf load
tPZX (Maximum)
tPXZ (Maximum)
oe -> pad
50 pf load
oe -> pad
50 pf load
26
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
.
.
Cell Function
Global Clocks and Set/Reset
tPD
Parameter
Path
Device
-1
Units
Notes
GCLK Input Buffer
FCLK Input Buffer
Clock Column Driver
Clock Sector Driver
GSRN Input Buffer
Global Clock to Output
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
1.1
1.2
1.2
1.4
ns
ns
ns
ns
Rising edge clock
(Maximum)
tPD
(Maximum)
pad -> clock
pad -> clock
pad -> clock
pad -> clock
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
0.7
0.8
0.8
0.8
ns
ns
ns
ns
Rising edge clock
Rising edge clock
Rising edge clock
tPD
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
0.8
0.9
1.0
1.1
ns
ns
ns
ns
(Maximum)
tPD
(Maximum)
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
0.5
0.5
0.5
0.5
ns
ns
ns
ns
tPD
(Maximum)
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
3.0
3.7
4.3
5.6
ns
ns
ns
ns
From any pad to Global
Set/Reset network
tPD
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
8.3
8.4
8.6
8.8
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
(Maximum)
Fast Clock to Output
tPD
(Maximum)
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
7.9
8.0
8.1
8.3
ns
ns
ns
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
27
2818F–FPGA–07/06
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Cell Function
Async RAM
Write
Parameter
Path
-1
Units
Notes
t
WECYC (Minimum)
tWEL (Minimum)
WEH (Minimum)
cycle time
12.0
5.0
5.0
5.3
0.0
5.0
0.0
8.7
6.3
2.9
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
we
Pulse width low
Pulse width high
Write
t
we
Write
tAWS (Minimum)
tAWH (Minimum)
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
rd addr -> dout
oe -> dout
Write
Write
tDS (Minimum)
Write
tDH (Minimum)
tDD (Maximum)
Write/Read
Read
rd addr = wr addr
t
AD (Maximum)
Read
tOZX (Maximum)
tOXZ (Maximum)
Read
oe -> dout
Sync RAM
Write
tCYC (Minimum)
tCLKL (Minimum)
cycle time
12.0
5.0
5.0
3.2
0.0
5.0
0.0
3.9
0.0
5.8
6.3
2.9
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
clk
Pulse width low
Pulse width high
Write
t
CLKH (Minimum)
clk
Write
tWCS (Minimum)
tWCH (Minimum)
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
Write
Write
tACS (Minimum)
Write
tACH (Minimum)
tDCS (Minimum)
Write
Write
t
DCH (Minimum)
tCD (Maximum)
AD (Maximum)
Write/Read
Read
rd addr = wr addr
t
rd addr -> dout
oe -> dout
Read
tOZX (Maximum)
tOXZ (Maximum)
Read
oe -> dout
Notes: 1. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant.
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
28
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
FreeRAM Asynchronous Timing Characteristics
Single-port Write/Read
t
WEL
WE
t
AWS
t
AWH
0
1
2
3
ADDR
OE
t
OH
t
t
DS
t
t
AD
t
OXZ
OZX
DH
DATA
Dual-port Write with
Read
t
WECYC
t
t
WEH
WEL
WE
t
AWS
t
t
AWH
0
1
2
WR ADDR
WR DATA
DH
PREV.
NEW
t
DD
RD ADDR = WR ADDR 1
t
WD
OLD
PREV.
NEW
RD DATA
Dual-port Read
0
1
RD ADDR
OE
t
t
AD
t
OXZ
OZX
DATA
29
2818F–FPGA–07/06
FreeRAM Synchronous Timing Characteristics
Single-port Write/Read
t
CLKH
CLK
WE
t
t
WCS
WCH
t
t
ACH
ACS
0
1
2
3
ADDR
OE
t
t
OZX
t
AD
OXZ
t
t
DCS
DCH
DATA
Dual-port Write with
Read
t
CYC
t
t
CLKH
CLKL
CLK
t
t
WCH
WCS
WE
WR ADDR
WR DATA
t
t
ACS
ACH
0
1
2
t
t
DCS
DCH
RD ADDR = WR ADDR 1
RD DATA
t
CD
Dual-port Read
0
1
RD ADDR
OE
t
t
AD
t
OXZ
OZX
DATA
30
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
Left Side (Top to Bottom)
240
84
128 I/O
192 I/O
256 I/O
384 I/O
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
GND
GND
GND
GND
12
13
1
1
2
1
I/O1,
GCK1
(A16)
I/O1,
GCK1
(A16)
I/O1,
GCK1
(A16)
I/O1,
GCK1
(A16)
2
2
4
2
3
I/O2
(A17)
I/O2
(A17)
I/O2
(A17)
I/O2
(A17)
14
3
3
5
I/O3
I/O4
I/O3
I/O4
I/O3
I/O4
I/O3
I/O4
4
5
6
7
4
5
I/O5
(A18)
I/O5
(A18)
I/O5
(A18)
I/O5
(A18)
15
16
4
5
6
7
8
9
6
7
I/O6
(A19)
I/O6
(A19)
I/O6
(A19)
I/O6
(A19)
GND
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
VCC
I/O7
I/O8
VCC
GND
GND
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
GND
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
GND
I/O7
I/O8
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
10
11
12
13
8
9
I/O9
10
11
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
GND
12
13
GND
GND
8
14
14
Note:
1. On-chip tri-state
31
2818F–FPGA–07/06
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
256 I/O
AT40K40AL
384 I/O
Left Side (Top to Bottom)
240
PQFP
84
PLCC
100 TQFP 144 LQFP 208 PQFP
I/O9,
FCK1
I/O13,
FCK1
I/O17,
FCK1
I/O25,
FCK1
9
15
16
17
15
16
17
I/O10
I/O14
I/O18
I/O26
10
11
I/O11
(A20)
I/O15
(A20)
I/O19
(A20)
I/O27
(A20)
17
18
6
7
I/O12
(A21)
I/O16
(A21)
I/O20
(A21)
I/O28
(A21)
12
18
18
VCC
I/O17
I/O18
VCC
I/O21
I/O22
VCC
I/O29
I/O30
GND
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
GND
VCC
19
20
21
I/O23
I/O24
GND
22
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
GND
I/O43
I/O44
I/O45
I/O46
I/O25
I/O26
I/O27
I/O28
I/O19
I/O20
19
20
23
24
I/O13
I/O14
I/O21
I/O22
I/O29
I/O30
13
14
21
22
25
26
8
I/O15
(A22)
I/O23
(A22)
I/O31
(A22)
I/O47
(A22)
19
20
9
15
16
23
24
27
28
I/O16
(A23)
I/O24
(A23)
I/O32
(A23)
I/O48
(A23)
10
GND
VCC
GND
VCC
GND
VCC
GND
VCC
21
22
11
12
17
18
25
26
29
30
Note:
1. On-chip tri-state
32
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
Left Side (Top to Bottom)
240
84
128 I/O
I/O17
192 I/O
I/O25
256 I/O
I/O33
384 I/O
I/O49
I/O50
I/O51
I/O52
I/O53
I/O54
GND
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
VCC
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
23
24
13
14
19
20
27
28
31
I/O18
I/O26
I/O34
32
I/O19
I/O20
I/O27
I/O28
I/O35
I/O36
15
21
22
29
30
33
34
I/O29
I/O30
I/O37
I/O38
I/O39
I/O40
31
32
35
36
GND
I/O41
I/O42
GND
I/O61
I/O62
I/O63
I/O64
I/O65
I/O66
GND
I/O67
I/O68
VCC
37
I/O31
I/O32
VCC
I/O43
I/O44
VCC
38
39
40
41
42
43
I/O21
I/O22
I/O23
I/O33
I/O34
I/O35
I/O45
I/O46
I/O47
I/O69
I/O70
I/O71
25
26
16
17
23
24
25
33
34
35
I/O24,
FCK2
I/O36,
FCK2
I/O48,
FCK2
I/O72,
FCK2
26
27
36
37
44
45
GND
GND
GND
I/O49
I/O50
I/O51
GND
I/O73
I/O74
I/O75
I/O37
46
Note:
1. On-chip tri-state
33
2818F–FPGA–07/06
AT40K05AL
128 I/O
AT40K10AL
AT40K20AL
AT40K40AL
Left Side (Top to Bottom)
240
PQFP
84
PLCC
192 I/O
256 I/O
384 I/O
I/O76
I/O77
I/O78
GND
I/O79
I/O80
I/O81
I/O82
I/O83
I/O84
GND
VCC
100 TQFP 144 LQFP 208 PQFP
I/O38
I/O52
47
I/O39
I/O40
I/O41
I/O42
I/O53
I/O54
I/O55
I/O56
GND
VCC
38
39
40
41
48
49
50
51
I/O25
I/O26
I/O57
I/O58
I/O85
I/O86
I/O87
I/O88
I/O89
I/O90
GND
I/O91
I/O92
I/O93
I/O94
I/O27
I/O28
I/O43
I/O44
I/O59
I/O60
27
18
19
28
29
42
43
52
53
I/O29
I/O30
I/O45
I/O46
I/O61
I/O62
30
31
44
45
54
55
I/O31
(OTS)(1)
I/O47
(OTS)(1)
I/O63
(OTS)(1)
I/O95
(OTS)(1)
28
29
20
21
32
33
46
47
56
57
I/O32,
GCK2
I/O48,
GCK2
I/O64,
GCK2
I/O96,
GCK2
M1
GND
M0
M1
GND
M0
M1
GND
M0
M1
GND
M0
30
31
32
22
23
24
34
35
36
48
49
50
58
59
60
Note:
1. On-chip tri-state
34
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
Bottom Side (Left to Right)
240
84
128 I/O
VCC
M2
192 I/O
VCC
M2
256 I/O
VCC
M2
384 I/O
VCC
M2
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
33
34
25
26
37
38
55
56
61
62
I/O33,
GCK3
I/O49,
GCK3
I/O65,
GCK3
I/O97,
GCK3
35
36
27
28
39
40
57
58
63
64
I/O34
(HDC)
I/O50
(HDC)
I/O66
(HDC)
I/O98
(HDC)
I/O35
I/O36
I/O37
I/O51
I/O52
I/O53
I/O67
I/O68
I/O69
I/O99
I/O100
I/O101
41
42
43
59
60
61
65
66
67
29
30
I/O38
(LDC)
I/O54
(LDC)
I/O70
(LDC)
I/O102
(LDC)
37
44
62
68
GND
I/O103
I/O104
I/O105
I/O106
I/O107
I/O108
VCC
I/O71
I/O72
VCC
GND
I/O73
I/O74
I/O75
I/O76
GND
I/O39
I/O40
I/O55
I/O56
I/O57
I/O58
I/O109
I/O110
I/O111
I/O112
I/O113
I/O114
GND
63
64
65
66
69
70
71
72
I/O77
I/O78
I/O79
I/O80
I/O115
I/O116
I/O117
I/O118
I/O119
I/O120
GND
I/O59
I/O60
73
74
GND
I/O41
GND
GND
I/O81
45
46
67
68
75
76
I/O61
I/O121
35
2818F–FPGA–07/06
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
Bottom Side (Left to Right)
84
240
128 I/O
I/O42
I/O43
I/O44
192 I/O
I/O62
I/O63
I/O64
VCC
256 I/O
I/O82
I/O83
I/O84
VCC
384 I/O
I/O122
I/O123
I/O124
VCC
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
47
48
49
69
70
71
77
78
79
80
81
82
38
39
31
32
I/O65
I/O66
I/O85
I/O86
I/O125
I/O126
GND
72
73
I/O127
I/O128
I/O129
I/O130
I/O131
I/O132
GND
I/O87
I/O88
GND
83
VCC
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O133
I/O134
I/O135
I/O136
I/O137
I/O138
GND
I/O67
I/O68
I/O69
I/O70
84
85
86
87
I/O45
I/O46
33
34
50
51
74
75
I/O139
I/O140
I/O141
I/O142
I/O47
(D15)
I/O71
(D15)
I/O95
(D15)
I/O143
(D15)
40
41
35
36
52
53
76
77
88
89
I/O48
(INIT)
I/O72
(INIT)
I/O96
(INIT)
I/O144
(INIT)
VCC
GND
VCC
GND
VCC
GND
VCC
GND
42
43
37
38
54
55
78
79
90
91
I/O49
(D14)
I/O73
(D14)
I/O97
(D14)
I/O145
(D14)
44
45
39
40
56
57
80
81
92
93
I/O50
(D13)
I/O74
(D13)
I/O98
(D13)
I/O146
(D13)
36
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
256 I/O
AT40K40AL
Bottom Side (Left to Right)
240
84
PLCC
384 I/O
I/O147
I/O148
I/O149
I/O150
GND
100 TQFP 144 LQFP 208 PQFP
PQFP
I/O51
I/O52
I/O75
I/O76
I/O77
I/O78
I/O99
I/O100
I/O101
I/O102
I/O103
I/O104
I/O151
I/O152
I/O153
I/O154
I/O155
I/O156
VCC
41
42
58
59
82
83
84
85
94
95
96
97
GND
I/O105
I/O106
GND
98
I/O157
I/O158
I/O159
I/O160
I/O161
I/O162
GND
I/O79
I/O80
VCC
I/O107
I/O108
VCC
I/O163
I/O164
VCC
99
100
101
I/O53
(D12)
I/O81
(D12)
I/O109
(D12)
I/O165
(D12)
46
47
43
44
60
61
86
87
102
103
I/O54
(D11)
I/O82
(D11)
I/O110
(D11)
I/O166
(D11)
I/O55
I/O56
GND
I/O83
I/O84
GND
I/O111
I/O112
GND
I/O167
I/O168
GND
62
63
64
88
89
90
104
105
106
I/O113
I/O114
I/O115
I/O116
I/O169
I/O170
I/O171
I/O172
I/O173
I/O85
I/O86
107
108
37
2818F–FPGA–07/06
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
256 I/O
AT40K40AL
Bottom Side (Left to Right)
84
PLCC
240
PQFP
384 I/O
I/O174
GND
100 TQFP 144 LQFP 208 PQFP
I/O175
I/O176
I/O177
I/O178
I/O179
I/O180
GND
I/O87
I/O88
I/O89
I/O90
I/O117
I/O118
I/O119
I/O120
GND
91
92
93
94
109
110
111
112
I/O57
I/O58
VCC
VCC
I/O121
I/O122
I/O181
I/O182
I/O59
(D10)
I/O91
(D10)
I/O123
(D10)
I/O183
(D10)
48
49
45
46
65
66
95
96
113
114
I/O60
(D9)
I/O92
(D9)
I/O124
(D9)
I/O184
(D9)
I/O185
I/O186
GND
I/O187
I/O188
I/O189
I/O190
I/O61
I/O62
I/O93
I/O94
I/O125
I/O126
67
68
97
98
115
116
I/O63
(D8)
I/O95
(D8)
I/O127
(D8)
I/O191
(D8)
50
51
47
48
69
70
99
117
118
I/O64,
GCK4
I/O96,
GCK4
I/O128,
GCK4
I/O192,
GCK4
100
GND
CON
GND
CON
GND
CON
GND
CON
52
53
49
50
71
72
101
103
119
120
38
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
Right Side (Bottom to Top)
240
84
128 I/O
VCC
192 I/O
VCC
256 I/O
VCC
384 I/O
VCC
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
54
55
51
52
73
74
106
108
121
122
RESET
RESET
RESET
RESET
I/O65
(D7)
I/O97
(D7)
I/O129
(D7)
I/O193
(D7)
56
57
53
54
75
76
109
110
123
124
I/O66,
GCK5
I/O98,
GCK5
I/O130,
GCK5
I/O194,
GCK5
I/O67
I/O68
I/O99
I/O131
I/O132
I/O133
I/O134
I/O195
I/O196
I/O197
I/O198
GND
77
78
111
112
125
126
I/O100
I/O101
I/O102
I/O135
I/O136
I/O199
I/O200
I/O201
I/O202
I/O203
I/O204
VCC
127
128
VCC
GND
GND
I/O69
(D6)
I/O103
(D6)
I/O137
(D6)
I/O205
(D6)
58
55
56
79
80
113
129
I/O70
I/O71
I/O72
I/O104
I/O105
I/O106
I/O138
I/O139
I/O140
I/O206
I/O207
I/O208
I/O209
I/O210
GND
114
115
116
130
131
132
I/O211
I/O212
I/O213
I/O214
I/O215
I/O216
GND
I/O107
I/O108
I/O141
I/O142
I/O143
I/O144
GND
117
118
133
134
GND
GND
I/O109
I/O110
81
119
135
136
137
I/O145
I/O146
I/O217
I/O218
39
2818F–FPGA–07/06
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
256 I/O
AT40K40AL
384 I/O
Right Side (Bottom to Top)
84
PLCC
240
PQFP
100 TQFP 144 LQFP 208 PQFP
I/O73,
FCK3
I/O111,
FCK3
I/O147,
FCK3
I/O219,
FCK3
82
83
120
121
138
I/O74
I/O112
VCC
I/O148
VCC
I/O220
VCC
139
140
I/O75
(D5)
I/O113
(D5)
I/O149
(D5)
I/O221
(D5)
59
60
57
58
84
85
122
123
141
142
I/O76
(CS0)
I/O114
(CS0)
I/O150
(CS0)
I/O222
(CS0)
GND
I/O223
I/O224
I/O225
I/O226
I/O227
I/O228
GND
I/O151
I/O152
GND
143
VCC
I/O229
I/O230
I/O231
I/O232
I/O233
I/O234
GND
I/O153
I/O154
I/O155
I/O156
I/O115
I/O116
124
125
144
145
I/O77
I/O78
I/O117
I/O118
I/O157
I/O158
I/O235
I/O236
I/O237
I/O238
I/O239(D4)
I/O240
VCC
59
60
86
87
126
127
146
147
I/O79(D4)
I/O80
I/O119(D4)
I/O120
VCC
I/O159(D4)
I/O160
VCC
61
62
63
64
61
62
63
64
88
89
90
91
128
129
130
131
148
149
150
151
VCC
GND
GND
GND
GND
I/O81
(D3)
I/O121
(D3)
I/O161
(D3)
I/O241
(D3)
65
66
65
66
92
93
132
133
152
153
I/O82
I/O122
I/O162
I/O242
(CHECK)
(CHECK)
(CHECK)
(CHECK)
40
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
256 I/O
AT40K40AL
Right Side (Bottom to Top)
240
84
PLCC
384 I/O
I/O243
I/O244
I/O245
I/O246
GND
100 TQFP 144 LQFP 208 PQFP
PQFP
I/O83
I/O84
I/O123
I/O124
I/O163
I/O164
67
94
95
134
135
154
155
I/O125
I/O126
I/O165
I/O166
I/O167
I/O168
I/O247
I/O248
I/O249
I/O250
I/O251
I/O252
VCC
136
137
156
157
GND
I/O169
I/O170
GND
158
I/O253
I/O254
I/O255
I/O256
I/O257
I/O258
GND
I/O85
(D2)
I/O127
(D2)
I/O171
(D2)
I/O259
(D2)
67
68
68
69
96
97
138
139
159
I/O86
I/O128
VCC
I/O172
VCC
I/O260
VCC
160
161
162
I/O87
I/O129
I/O173
I/O261
98
99
140
141
I/O88,
FCK4
I/O130,
FCK4
I/O174,
FCK4
I/O262,
FCK4
163
I/O131
I/O132
GND
I/O175
I/O176
GND
I/O263
I/O264
GND
164
165
166
GND
100
142
I/O177
I/O178
I/O179
I/O180
I/O265
I/O266
I/O267
I/O268
I/O269
I/O133
I/O134
167
168
41
2818F–FPGA–07/06
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
256 I/O
AT40K40AL
Right Side (Bottom to Top)
84
PLCC
240
PQFP
384 I/O
I/O270
GND
100 TQFP 144 LQFP 208 PQFP
I/O135
I/O136
I/O137
I/O138
I/O181
I/O182
I/O183
I/O184
I/O271
I/O272
I/O273
I/O274
I/O275
I/O276
GND
143
144
145
146
169
170
171
172
I/O89
I/O90
GND
VCC
VCC
I/O91
(D1)
I/O139
(D1)
I/O185
(D1)
I/O277
(D1)
69
70
70
71
101
102
147
148
173
174
I/O92
I/O140
I/O186
I/O278
I/O279
I/O280
I/O281
I/O282
GND
I/O187
I/O188
I/O189
I/O190
I/O283
I/O284
I/O285
I/O286
I/O93
I/O94
I/O141
I/O142
103
104
149
150
175
176
I/O95
(D0)
I/O143
(D0)
I/O191
(D0)
I/O287
(D0)
71
72
72
73
105
151
177
I/O96,
GCK6
I/O144,
GCK6
I/O192,
GCK6
I/O288,
GCK6
106
152
178
(CSOUT)
(CSOUT)
(CSOUT)
(CSOUT)
CCLK
VCC
CCLK
VCC
CCLK
VCC
CCLK
VCC
73
74
75
74
75
76
107
108
109
153
154
159
179
180
181
TSTCLK
TSTCLK
TSTCLK
TSTCLK
42
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
Top Side (Right to Left)
240
84
128 I/O
192 I/O
256 I/O
384 I/O
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
GND
GND
GND
GND
76
77
77
78
110
111
160
161
182
I/O97
(A0)
I/O145
(A0)
I/O193
(A0)
I/O289
(A0)
183
184
I/O98,
GCK7
(A1)
I/O146,
GCK7
(A1)
I/O194,
GCK7
(A1)
I/O290,
GCK7
(A1)
78
79
112
162
I/O99
I/O147
I/O148
I/O195
I/O196
I/O291
I/O292
I/O293
I/O294
GND
113
114
163
164
185
186
I/O100
I/O295
I/O296
I/O101
I/O149
I/O197
I/O297
79
80
80
81
115
116
165
166
187
188
(CS1,A2)
(CS1,A2)
(CS1,A2)
(CS1,A2)
I/O102
(A3)
I/O150
(A3)
I/O198
(A3)
I/O298
(A3)
I/O199
I/O200
VCC
I/O299
I/O300
VCC
GND
GND
75(1)
NC
76(1)
NC
189(1)
NC
I/O151(1)
I/O201(1)
I/O301(1)
109(1) NC
117
159(1) NC
I/O152
I/O153
I/O154
I/O202
I/O203
I/O204
I/O302
I/O303
I/O304
I/O305
I/O306
GND
190
191
192
I/O103
167
168
I/O104(1)
I/O307
I/O308
I/O309
I/O310
I/O311
I/O312
GND
I/O155
I/O156
I/O205
I/O206
I/O207
I/O208
GND
169
170
193
194
195
GND
GND
118
171
196
Note:
1. Shared with TSTCLK. No Connect.
43
2818F–FPGA–07/06
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
Top Side (Right to Left)
84
240
128 I/O
I/O105
I/O106
192 I/O
I/O157
I/O158
I/O159
I/O160
VCC
256 I/O
I/O209
I/O210
I/O211
I/O212
VCC
384 I/O
I/O313
I/O314
I/O315
I/O316
VCC
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
119
120
172
173
197
198
199
200
201
I/O213
I/O214
I/O317
I/O318
GND
I/O319
I/O320
I/O321
I/O322
I/O323
I/O324
GND
I/O215
I/O216
GND
VCC
I/O107
(A4)
I/O161
(A4)
I/O217
(A4)
I/O325
(A4)
81
82
82
83
121
122
174
175
202
203
I/O108
(A5)
I/O162
(A5)
I/O218
(A5)
I/O326
(A5)
I/O163
I/O164
I/O165
I/O166
I/O219
I/O220
I/O221
I/O222
I/O327
I/O328
I/O329
I/O330
GND
176
177
178
179
205
206
207
208
I/O109
I/O110
84
85
123
124
I/O331
I/O332
I/O333
I/O334
I/O111
(A6)
I/O167
(A6)
I/O223
(A6)
I/O335
(A6)
83
84
86
87
125
126
180
181
209
210
I/O112
(A7)
I/O168
(A7)
I/O224
(A7)
I/O336
(A7)
GND
VCC
GND
VCC
GND
VCC
GND
VCC
1
2
88
89
127
128
182
183
211
212
Note:
1. Shared with TSTCLK. No Connect.
44
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
256 I/O
AT40K40AL
384 I/O
Top Side (Right to Left)
240
84
PLCC
100 TQFP 144 LQFP 208 PQFP
PQFP
I/O113
(A8)
I/O169
(A8)
I/O225
(A8)
I/O337
(A8)
3
4
90
91
129
130
184
185
213
I/O114
(A9)
I/O170
(A9)
I/O226
(A9)
I/O338
(A9)
214
I/O339
I/O340
I/O341
I/O342
GND
I/O115
I/O116
I/O171
I/O172
I/O173
I/O174
I/O227
I/O228
I/O229
I/O230
I/O343
I/O344
I/O345
I/O346
92
93
131
132
186
187
188
189
215
216
217
218
I/O117
(A10)
I/O175
(A10)
I/O231
(A10)
I/O347
(A10)
5
6
94
95
133
134
190
191
220
221
I/O118
(A11)
I/O176
(A11)
I/O232
(A11)
I/O348
(A11)
VCC
GND
GND
I/O233
I/O234
I/O349
I/O350
I/O351
I/O352
I/O353
I/O354
GND
I/O235
I/O236
VCC
I/O355
I/O356
VCC
VCC
I/O177
I/O178
I/O179
I/O180
GND
222
223
224
225
226
227
I/O237
I/O238
I/O239
I/O240
GND
I/O357
I/O358
I/O359
I/O360
GND
I/O119
I/O120
GND
135
136
137
192
193
194
I/O241
I/O361
Note:
1. Shared with TSTCLK. No Connect.
45
2818F–FPGA–07/06
AT40K05AL
128 I/O
AT40K10AL
192 I/O
AT40K20AL
AT40K40AL
Top Side (Right to Left)
84
PLCC
240
PQFP
256 I/O
I/O242
I/O243
I/O244
384 I/O
I/O362
I/O363
I/O364
I/O365
I/O366
GND
100 TQFP 144 LQFP 208 PQFP
I/O181
I/O182
195
196
228
229
I/O367
I/O368
I/O369
I/O370
I/O121
I/O122
I/O183
I/O184
I/O245
I/O246
197
198
230
231
I/O123
(A12)
I/O185
(A12)
I/O247
(A12)
I/O371
(A12)
7
8
96
97
138
139
199
200
232
233
I/O124
(A13)
I/O186
(A13)
I/O248
(A13)
I/O372
(A13)
GND
VCC
GND
VCC
I/O249
I/O250
I/O373
I/O374
I/O375
I/O376
I/O377
I/O378
GND
I/O187
I/O188
I/O189
I/O190
I/O251
I/O252
I/O253
I/O254
I/O379
I/O380
I/O381
I/O382
234
235
236
237
I/O125
I/O126
140
141
201
202
I/O127
(A14)
I/O191
(A14)
I/O255
(A14)
I/O383
(A14)
9
98
142
203
238
I/O128,
GCK8
(A15)
I/O192,
GCK8
(A15)
I/O256,
GCK8
(A15)
I/O384,
GCK8
(A15)
10
11
99
143
144
204
205
239
240
VCC
VCC
VCC
VCC
100
Note:
1. Shared with TSTCLK. No Connect.
46
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
Part/Package Availability and User I/O Counts (including Dual-function Pins)
Package(1)
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
84 PLCC
62
78
62
78
–
78
62
–
100 TQFP
144 LQFP
208 PQFP
240 PQFP
114
128
–
114
161
–
114
161
–
114
161
193
Note:
1. Devices in same package are pin-to-pin compatible.
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100T1
100-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
144-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP)
208-lead, Plastic Quad Flat Package (PQFP)
144L1
208Q1
240Q1
240-lead, Plastic Quad Flat Package (PQFP)
47
2818F–FPGA–07/06
AT40K05AL Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
AT40K05AL-1AJC
AT40K05AL-1AQC
AT40K05AL-1BQC
AT40K05AL-1DQC
84J
100T1
144L1
208Q1
Commercial
(0°C to 70°C)
5,000 - 10,000
3.3V
3.3V
1
1
AT40K05AL-1AJI
AT40K05AL-1AQI
AT40K05AL-1BQI
AT40K05AL-1DQI
84J
100T1
144L1
208Q1
Industrial
(-40°C to 85°C)
5,000 - 10,000
AT40K10AL Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
AT40K10AL-1AJC
AT40K10AL-1AQC
AT40K10AL-1BQC
AT40K10AL-1DQC
84J
100T1
144L1
208Q1
Commercial
(0°C to 70°C)
10,000 - 20,000
3.3V
3.3V
1
1
AT40K10AL-1AJI
AT40K10AL-1AQI
AT40K10AL-1BQI
AT40K10AL-1DQI
84J
100T1
144L1
208Q1
Industrial
(-40°C to 85°C)
10,000 - 20,000
AT40K20AL Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
20,000 - 30,000
3.3V
1
AT40K20AL-1AJC
AT40K20AL-1AQC
AT40K20AL-1BQC
AT40K20AL-1DQC
84J
100T1
144L1
208Q1
Commercial
(0°C to 70°C)
20,000 - 30,000
3.3V
1
AT40K20AL-1AJI
AT40K20AL-1AQI
AT40K20AL-1BQI
AT40K20AL-1DQI
84J
100T1
144L1
208Q1
Industrial
(-40°C to 85°C)
AT40K40AL Ordering Information
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range(1)
AT40K40AL-1BQC
AT40K40AL-1DQC
AT40K40AL-1EQC
144L1
208Q1
240Q1
Commercial
(0°C to 70°C)
40,000 - 50,000
3.3V
3.3V
1
1
AT40K40AL-1BQI
AT40K40AL-1DQI
AT40K40AL-1EQI
144L1
208Q1
240Q1
Industrial
(-40°C to 85°C)
40,000 - 50,000
Note:
1. For military parts, contact Atmel at fpga@atmel.com.
Green Package Options (Pb/Halide-free/RoHS Compliant)
Usable Gates
Operating Voltage Speed Grade (ns)
Ordering Code
Package
Operation Range
5,000 - 10,000
10,000 - 20,000
20,000 - 30,000
4,000 - 50,000
AT40K05AL-1BQU
AT40K10AL-1BQU
AT40K20AL-1BQU
AT40K40AL-1BQU
Industrial
(-40°C to 85°C)
3.3V
1
144L1
48
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
Packaging Information
84J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
30.099
29.210
30.099
29.210
–
30.353
D1
E
–
29.413 Note 2
30.353
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
29.413 Note 2
28.702
D2/E2 27.686
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
84J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
49
2818F–FPGA–07/06
100T1 – TQFP
D
D1
XX
e
E
E1
N
b
Bottom View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.05
0.95
MAX
0.15
1.05
NOM
NOTE
SYMBOL
A2
A1
6
A2
D
1.00
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
0.22
A1
D1
E
2, 3
2, 3
4, 5
L1
Side View
E1
e
b
0.17
0.27
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions, including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum
b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and
an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating place to the lowest point on the package body.
11/30/01
TITLE
100T1, 100-lead (14 x 14 x 1.0 mm Body), Thin Plastic
Quad Flat Pack (TQFP)
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
100T1
A
R
50
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
144L1 – LQFP
D1
D
XX
e
E1
E
N
b
Bottom View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.05
1.35
MAX
0.15
1.45
NOM
NOTE
SYMBOL
A1
A2
D
6
A2
1.40
22.00 BSC
20.00 BSC
22.00 BSC
20.00 BSC
0.50 BSC
0.22
A1
D1
E
2, 3
2, 3
4, 5
L1
Side View
E1
e
b
0.17
0.27
L1
1.00 REF
1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
Notes:
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum
b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and
an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating place to the lowest point on the package body.
11/30/01
TITLE
144L1, 144-lead (20 x 20 x 1.4 mm Body), Low Profile
Plastic Quad Flat Pack (LQFP)
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
144L1
A
R
51
2818F–FPGA–07/06
208Q1 – PQFP
D1
A2
L1
A1
E1
Side View
e
b
Top View
D
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.25
3.20
MAX
0.50
3.60
NOM
–
NOTE
SYMBOL
A1
A2
D
3.40
E
30.60 BSC
28.00 BSC
30.60 BSC
28.00 BSC
0.50 BSC
–
D1
E
2, 3
2, 3
4
E1
e
b
0.17
0.27
L1
1.30 REF
Bottom View
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-1, for proper dimensions, tolerances, datums, etc.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07 mm.
03/10/05
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
208Q1, 208-lead (28 x 28 mm Body, 2.6 Form Opt.),
Plastic Quad Flat Pack (PQFP)
208Q1
C
R
52
AT40KAL Series FPGA
2818F–FPGA–07/06
AT40KAL Series FPGA
240Q1 – PQFP
D1
D
E1
E
Top View
Bottom View
A2
A1
e
b
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
0.25
3.20
MAX
0.50
3.60
NOM
–
NOTE
SYMBOL
A1
A2
D
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-029, Variation GA, for additional information.
3.40
34.60 BSC
32.00 BSC
34.60 BSC
32.00 BSC
0.50 BSC
–
3
2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994.
3. To be determined at seating plane.
4. Dimensions D1 and E1 do not include mold protrusions. Allowable
protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch. Dimensions D1 and E1 shall be
determined at datum plane.
5. Dimension b does not include Dambar protrusion. Allowable Dambar
protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm. Dambar cannot be located on the lower
radius or the foot. The minimum space between protrusion and an adjacent
lead shall not be less than 0.07 mm.
D1
E
2, 4
3
E1
e
2, 4
b
0.17
0.27
5
L1
1.30 REF
3/29/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
240Q1, 240-lead, 32 x 32 mm Body, 2.6 Form Opt.,
Plastic Quad Flat Pack (PQFP)
240Q1
A
R
53
2818F–FPGA–07/06
Revision History
Revision Level – Release Date History
F – July 2006
Added Green (Pb/Halide-free/RoHS Compliant) 144-lead LQFP.
54
AT40KAL Series FPGA
2818F–FPGA–07/06
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
Regional Headquarters
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
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Tel: 1(719) 576-3300
Europe
Atmel Sarl
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Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
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38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
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Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
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Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
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2818F–FPGA–07/06
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