AT45D011-JC [ATMEL]
1-Megabit 5.0-volt Only Serial DataFlash; 1兆位5.0伏，只有串行数据闪存
| 型号： | AT45D011-JC |
| 厂家： | 
ATMEL |
| 描述： | 1-Megabit 5.0-volt Only Serial DataFlash |
| 文件： | 总20页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single 4.5V - 5.5V Supply
• Serial Interface Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
• Optional Page and Block Erase Operations
• One 264-Byte SRAM Data Buffer
• Internal Program and Control Timer
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low-Power Dissipation
– 15 mA Active Read Current Typical
– 10 µA CMOS Standby Current Typical
• 15 MHz Max Clock Frequency
• Hardware Data Protection Feature
• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
1-Megabit
5.0-volt Only
Serial
DataFlash®
Description
AT45D011
Preliminary
The AT45D011 is a 5.0-volt only, serial interface Flash memory suitable for in-system
reprogramming. Its 1,081,344 bits of memory are organized as 512 pages of 264
bytes each. In addition to the main memory, the AT45D011 also contains one SRAM
data buffer of 264 bytes. Unlike conventional Flash memories that are accessed ran-
domly with multiple address lines and a parallel interface, the DataFlash uses a serial
interface to sequentially access its data. The simple serial interface facilitates hard-
(continued)
Pin Configurations
SOIC
Pin Name
Function
SI
SCK
1
2
3
4
8
7
6
5
SO
CS
Chip Select
Serial Clock
Serial Input
Serial Output
GND
VCC
WP
RESET
CS
SCK
SI
SO
AT45DB011
Hardware Page
Write Protect Pin
WP
Preliminary 16-
Megabit 2.7-volt
Only Serial
RESET
Chip Reset
Ready/Busy
PLCC
RDY/BUSY
TSSOP Top View
Type 1
DataFlash
RDY/BUSY
1
2
3
4
5
6
7
14
13
12
11
10
9
CS
NC
NC
NC
NC
NC
SI
SCK
SI
5
6
7
8
9
29 WP
RESET
WP
28 RESET
27 RDY/BUSY
26 NC
SO
NC
NC
VCC
GND
SCK
SO
25 NC
NC 10
NC 11
NC 12
NC 13
24 NC
23 NC
22 NC
8
21 NC
Rev. 1123A–08/98
Note: PLCC package pins 16
and 17 are DON’T CONNECT
ware layout, increases system reliability, minimizes switch-
ing noise, and reduces package size and active pin count.
The device is optimized for use in many commercial and
industrial applications where high density, low pin count,
low voltage, and low power are essential. Typical applica-
tions for the DataFlash are digital voice storage, image
storage, and data storage. The device operates at clock
frequencies up to 15 MHz with a typical active read current
consumption of 15 mA.
To allow for simple in-system reprogrammability, the
AT45D011 does not require high input voltages for pro-
gramming. The device operates from a single power sup-
ply, 4.5V to 5.5V, for both the program and read
operations. The AT45D011 is enabled through the chip
select pin (CS) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and
the Serial Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER (264 BYTES)
SCK
CS
I/O INTERFACE
RESET
V
CC
GND
RDY/BUSY
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the
AT45D011 is divided into three levels of granularity com-
prising of sectors, blocks, and pages. The Memory Archi-
tecture Diagram illustrates the breakdown of each level and
details the number of pages per sector and block. All pro-
gram operations to the DataFlash occur on a page by page
basis; however, the optional erase operations can be per-
formed at the block or page level.
AT45DB011
2
AT45DB011
Memory Architecture Diagram
SECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
SECTOR 0
PAGE 0
PAGE 1
8 Pages
SECTOR 0 = 2112 BYTES (2K + 64)
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
PAGE 6
PAGE 7
PAGE 8
PAGE 9
SECTOR 1 = 65,472 BYTES (62K + 1984)
BLOCK 29
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 34
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 2 = 67,584 BYTES (64K + 2K)
BLOCK 61
BLOCK 62
BLOCK 63
PAGE 509
PAGE 510
PAGE 511
Block = 2112 bytes
(2K + 64)
Page = 264 bytes
(256 + 8)
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Table 1 and Table 2. A valid
instruction starts with the falling edge of CS followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
bits are sent to initialize the read operation. Following the
32 don’t care bits, additional pulses on SCK result in serial
data being output on the SO (serial output) pin. The CS pin
must remain low during the loading of the opcode, the
address bits, and the reading of data. When the end of a
page in main memory is reached during a main memory
page read, the device will continue reading at the beginning
of the same page. A low to high transition on the CS pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from the data buffer
using an opcode of 54H. To perform a buffer read, the eight
bits of the opcode must be followed by 15 don’t care bits,
nine address bits, and eight don't care bits. Since the buffer
size is 264-bytes, nine address bits (BFA8-BFA0) are
required to specify the first byte of data to be read from the
buffer. The CS pin must remain low during the loading of
the opcode, the address bits, the don’t care bits, and the
reading of data. When the end of the buffer is reached, the
device will continue reading back at the beginning of the
buffer. A low to high transition on the CS pin will terminate
the read operation and tri-state the SO pin.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from the data buffer.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 512
pages in the main memory, bypassing the data buffer and
leaving the contents of the buffer unchanged. To start a
page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits. In the AT45D011, the
first six address bits are reserved for larger density devices
(see Notes on page 10), the next nine address bits (PA8-
PA0) specify the page address, and the next nine address
bits (BA8-BA0) specify the starting byte address within the
page. The 32 don’t care bits which follow the 24 address
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page
of data can be transferred from the main memory to buffer.
An 8-bit opcode of 53H is followed by the six reserved bits,
nine address bits (PA8-PA0) which specify the page in
3
main memory that is to be transferred, and nine don’t care
bits. The CS pin must be low while toggling the SCK pin to
load the opcode, the address bits, and the don’t care bits
from the SI pin. The transfer of the page of data from the
main memory to the buffer will begin when the CS pin tran-
sitions from a low to a high state. During the transfer of a
page of data (tXFR), the status register can be read to deter-
mine whether the transfer has been completed or not.
page are internally self timed and should take place in a
maximum time of tEP. During this time, the status register
will indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
OUT BUILT-IN ERASE: A previously erased page within
main memory can be programmed with the contents of the
buffer. An 8-bit opcode of 88H is followed by the six
reserved bits, nine address bits (PA8-PA0) that specify the
page in the main memory to be written, and nine additional
don’t care bits. When a low to high transition occurs on the
CS pin, the part will program the data stored in the buffer
into the specified page in the main memory. It is necessary
that the page in main memory that is being programmed
has been previously erased. The programming of the page
is internally self timed and should take place in a maximum
time of tP. During this time, the status register will indicate
that the part is busy.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of
data in main memory can be compared to the data in the
buffer. An 8-bit opcode of 60H is followed by 24 address
bits consisting of the six reserved bits, nine address bits
(PA8-PA0) which specify the page in the main memory that
is to be compared to the buffer, and nine don’t care bits.
The loading of the opcode and the address bits is the same
as described previously. The CS pin must be low while tog-
gling the SCK pin to load the opcode, the address bits, and
the don't care bits from the SI pin. On the low to high transi-
tion of the CS pin, the 264 bytes in the selected main mem-
ory page will be compared with the 264 bytes in the buffer.
During this time (tXFR), the status register will indicate that
the part is busy. On completion of the compare operation,
bit 6 of the status register is updated with the result of the
compare.
PAGE ERASE: The optional Page Erase command can be
used to individually erase any page in the main memory
array allowing the Buffer to Main Memory Page Program
without Built-In Erase command to be utilized at a later
time. To perform a Page Erase, an opcode of 81H must be
loaded into the device, followed by six reserved bits, nine
address bits (PA8-PA0), and nine don’t care bits. The nine
address bits are used to specify which page of the memory
array is to be erased. When a low to high transition occurs
on the CS pin, the part will erase the selected page to 1s.
The erase operation is internally self-timed and should take
place in a maximum time of tPE. During this time, the status
register will indicate that the part is busy.
Program
BUFFER WRITE: Data can be shifted in from the SI pin
into the data buffer. To load data into the buffer, an 8-bit
opcode of 84H is followed by 15 don’t care bits and nine
address bits (BFA8-BFA0). The nine address bits specify
the first byte in the buffer to be written. The data is entered
following the address bits. If the end of the data buffer is
reached, the device will wrap around back to the beginning
of the buffer. Data will continue to be loaded into the buffer
until a low to high transition is detected on the CS pin.
BLOCK ERASE: A block of eight pages can be erased at
one time allowing the Buffer to Main Memory Page Pro-
gram without Built-In Erase command to be utilized to
reduce programming times when writing large amounts of
data to the device. To perform a Block Erase, an opcode of
50H must be loaded into the device, followed by six
reserved bits, six address bits (PA8-PA3), and 12 don’t
care bits. The six address bits are used to specify which
block of eight pages is to be erased. When a low to high
transition occurs on the CS pin, the part will erase the
selected block of eight pages to 1s. The erase operation is
internally self-timed and should take place in a maximum
time of tBE. During this time, the status register will indicate
that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE: Data written into the buffer can be pro-
grammed into the main memory. An 8-bit opcode of 83H is
followed by the six reserved bits, nine address bits (PA8-
PA0) that specify the page in the main memory to be writ-
ten, and nine additional don’t care bits. When a low to high
transition occurs on the CS pin, the part will first erase the
selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the
main memory. Both the erase and the programming of the
AT45DB011
4
AT45DB011
Block Erase Addressing
PA8
PA7
PA6
PA5
0
PA4
0
PA3
0
PA2
X
PA1
X
PA0
X
Block
0
0
0
0
1
2
3
0
0
0
0
0
1
X
X
X
0
0
0
0
1
0
X
X
X
0
0
0
0
1
1
X
X
X
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
60
61
62
63
MAIN MEMORY PAGE PROGRAM: This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase operations. Data is first
shifted into the buffer from the SI pin and then programmed
into a specified page in the main memory. An 8-bit opcode
of 82H is followed by the six reserved bits and 18 address
bits. The nine most significant address bits (PA8-PA0)
select the page in the main memory where data is to be
written, and the next nine address bits (BFA8-BFA0) select
the first byte in the buffer to be written. After all address bits
are shifted in, the part will take data from the SI pin and
store it in the data buffer. If the end of the buffer is reached,
the device will wrap around back to the beginning of the
buffer. When there is a low to high transition on the CS pin,
the part will first erase the selected page in main memory to
all 1s and then program the data stored in the buffer into
the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and
should take place in a maximum of time tEP. During this
time, the status register will indicate that the part is busy.
self-timed and should take place in a maximum time of tEP.
During this time, the status register will indicate that the
part is busy.
If a sector is programmed or reprogrammed sequentially
page by page, then the programming algorithm shown in
Figure 1 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sec-
tor, then the programming algorithm shown in Figure 2 is
recommended.
STATUS REGISTER: The status register can be used to
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of
57H must be loaded into the device. After the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most-signifi-
cant bits of the status register will contain device informa-
tion, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itself (as long as CS remains low and
SCK is being toggled) starting again with bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
AUTO PAGE REWRITE: This mode is only needed if multi-
ple bytes within a page or multiple pages of data are modi-
fied in a random fashion. This mode is a combination of two
operations: Main Memory Page to Buffer Transfer and
Buffer to Main Memory Page Program with Built-In Erase.
A page of data is first transferred from the main memory to
the data buffer, and then the same data (from the buffer) is
programmed back into its original page of main memory.
An 8-bit opcode of 58H is followed by the six reserved bits,
nine address bits (PA8-PA0) that specify the page in main
memory to be rewritten, and nine additional don’t care bits.
When a low to high transition occurs on the CS pin, the part
will first transfer data from the page in main memory to the
buffer and then program the data from the buffer back into
same page of main memory. The operation is internally
Ready/busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
cause the device to be in a busy state: Main Memory Page
5
to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-In Erase,
Buffer to Main Memory Page Program without Built-In
Erase, Page Erase, Block Erase, Main Memory Page Pro-
gram, and Auto Page Rewrite.
machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The device incorporates an internal power-on reset circuit,
so there are no restrictions on the RESET pin during
power-on sequences. The RESET pin is also internally
pulled high; therefore, in low pin count applications, con-
nection of the RESET pin is not necessary if this pin and
feature will not be utilized. However, it is recommended
that the RESET pin be driven high externally whenever
possible.
The result of the most recent Main Memory Page to Buffer
Compare operation is indicated using bit 6 of the status
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
least one bit of the data in the main memory page does not
match the data in the buffer.
The device density is indicated using bits 5, 4, and 3 of the
status register. For the AT45D011, the three bits are 0, 0,
and 1. The decimal value of these three binary bits does
not equate to the device density; the three bits represent a
combinational code relating to differing densities of Serial
DataFlash devices, allowing a total of eight different density
configurations.
READY/BUSY: This open drain output pin will be driven
low when the device is busy in an internally self-timed oper-
ation. This pin, which is normally in a high state (through an
external pull-up resistor), will be pulled low during program-
ming operations, compare operations, and during page-to-
buffer transfers.
HARDWARE PAGE WRITE PROTECT: If the WP pin is
held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256
pages is to first drive the protect pin high and then use the
program commands previously mentioned. The WP pin is
internally pulled high; therefore, in low pin count applica-
tions, connection of the WP pin is not necessary if this pin
and feature will not be utilized. However, it is recom-
mended that the WP pin be driven high externally when-
ever possible.
The busy status indicates that the Flash memory array and
the buffer cannot be accessed.
Power On/Reset State
When power is first applied to the device, or when recover-
ing from a reset condition, the device will default to SPI
mode 3. In addition, the SO pin will be in a high impedance
state, and a high to low transition on the CS pin will be
required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sam-
pling the inactive clock state.
RESET: A low state on the reset pin (RESET) will terminate
the operation in progress and reset the internal state
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
COMP
0
0
1
X
X
X
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
AT45DB011
6
AT45DB011
DC and AC Operating Range
AT45D011
0°C to 70°C
-40°C to 85°C
4.5V to 5.5V
Com.
Ind.
Operating Temperature (Case)
V
CC Power Supply(1)
Note:
1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-
ational mode is started.
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
ISB
Standby Current
CS, RESET, WP = VIH,
10
20
µA
all inputs at CMOS levels
ICC1
ICC2
Active Current,
Read Operation
f = 15 MHz; IOUT = 0 mA;
15
25
25
50
mA
mA
VCC = 5.5V
Active Current,
VCC = 5.5V
Program/Erase Operation
ILI
Input Load Current
Output Leakage Current
Input Low Voltage
VIN = CMOS levels
VI/O = CMOS levels
10
10
µA
µA
V
ILO
VIL
0.8
VIH
VOL
VOH1
VOH2
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
2.0
V
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
7
AC Characteristics
Symbol
fSCK
tWH
tWL
Parameter
Min
Typ
Max
Units
MHz
ns
SCK Frequency
15
SCK High Time
30
30
SCK Low Time
ns
tCS
Minimum CS High Time
CS Setup Time
250
250
250
ns
tCSS
tCSH
tCSB
tSU
ns
CS Hold Time
ns
CS High to RDY/BUSY Low
Data In Setup Time
Data In Hold Time
200
ns
10
15
0
ns
tH
ns
tHO
Output Hold Time
ns
tDIS
tV
tXFR
tEP
Output Disable Time
Output Valid
20
25
ns
ns
Page to Buffer Transfer/Compare Time
Page Erase and Programming Time
Page Programming Time
Page Erase Time
120
10
7
200
20
µs
ms
ms
ms
ms
µs
tP
15
tPE
6
10
tBE
Block Erase Time
7
15
tRST
tREC
RESET Pulse Width
RESET Recovery Time
10
1
µs
Input Test Waveforms and
Measurement Levels
2.4V
Output Test Load
DEVICE
UNDER
TEST
AC
AC
2.0
DRIVING
LEVELS
MEASUREMENT
LEVEL
30 pF
0.8
0.45V
tR, tF < 5 ns (10% to 90%)
AT45DB011
8
AT45DB011
AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the SCK signal being low when CS makes a high-
to-low transition, and Waveform 2 shows the SCK signal
being high when CS makes a high-to-low transition. Both
waveforms show valid timing diagrams. The setup and hold
times for the SI signal are referenced to the low-to-high
transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI
Mode 0, and Waveform 2 shows timing that is compatible
with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low
tCS
CS
tCSS
tWH
tWL
tCSH
SCK
SO
SI
tV
tHO
tDIS
HIGH IMPEDANCE
tSU
HIGH IMPEDANCE
VALID OUT
tH
VALID IN
Waveform 2 – Inactive Clock Polarity High
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
SO
SI
tV
tHO
tDIS
HIGH Z
HIGH IMPEDANCE
VALID OUT
tH
tSU
VALID IN
9
Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC
tCSS
SCK
tRST
RESET
HIGH IMPEDANCE
HIGH IMPEDANCE
SO
SI
Command Sequence for Read/Write Operations (Except Status Register Read)
SI
CMD
8 bits
8 bits
8 bits
MSB
r r r r r r X X
X X X X X X X X
Page Address
X X X X X X X X
LSB
Reserved for
Byte/Buffer Address
larger densities
(PA8-PA0)
(BA8-BA0/BFA8-BFA0)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0”.
3. For densities larger than 1M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
AT45DB011
10
AT45DB011
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER TO
MAIN MEMORY
PAGE PROGRAM
BUFFER (264 BYTES)
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER
BUFFER
WRITE
I/O INTERFACE
SI
Main Memory Page Program through Buffer
· Completes writing into buffer
· Starts self-timed erase/program operation
CS
BFA7-0
r ···r , PA8-7
PA6-0, BFA8
SI
CMD
n
n+1
Last Byte
Buffer Write
· Completes writing into buffer
CS
SI
CMD
X
X···X, BFA8
BFA7-0
n
n+1
Last Byte
Buffer to Main Memory Page Program
(Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS
SI
CMD
r ···r , PA8-7
PA6-0, X
X
n = 1st byte written
Each transition represents
8 bits and 8 clock cycles
n+1 = 2nd byte written
11
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
MAIN MEMORY
PAGE TO
BUFFER
MAIN MEMORY
PAGE READ
BUFFER (264 BYTES)
BUFFER
READ
I/O INTERFACE
SO
Main Memory Page Read
CS
SI
CMD
r ···r , PA8-7
PA6-0, BA8
BA7-0
X
X
X
X
n
n+1
SO
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS
SI
CMD
r ···r , PA8-7
PA6-0, X
X
SO
Buffer Read
CS
SI
CMD
X
X···X, BFA8
BFA7-0
X
SO
n
n+1
n = 1st byte read
Each transition represents
8 bits and 8 clock cycles
n+1 = 2nd byte read
AT45DB011
12
AT45DB011
Detailed Bit-Level Read Timing – Inactive Clock Polarity Low
Main Memory Page Read
CS
SCK
1
2
3
4
5
0
60
X
61
X
62
X
63
X
64
X
65
66
67
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
MSB
Buffer Read
CS
SCK
1
0
2
3
4
5
0
36
X
37
X
38
X
39
X
40
X
41
42
43
tSU
COMMAND OPCODE
SI
1
0
1
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
MSB
Status Register Read
CS
SCK
1
2
1
3
4
5
6
7
1
8
1
9
10
11
12
16
17
tSU
COMMAND OPCODE
SI
0
0
1
0
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
1
D
0
D
7
MSB
LSB
MSB
13
Detailed Bit-Level Read Timing – Inactive Clock Polarity High
Main Memory Page Read
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
67
68
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
4
MSB
Buffer Read
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
4
MSB
Status Register Read
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
0
1
0
1
0
1
1
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
4
D
0
D
7
D
6
MSB
LSB
MSB
AT45DB011
14
AT45DB011
Table 1
Main Memory
Page Read
Buffer
Read
Main Memory Page
to Buffer Transfer
Main Memory Page
to Buffer Compare
Buffer
Write
Opcode
52H
54H
53H
0
60H
0
84H
0
0
1
1
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
0
r
X
r
r
X
r
X
r
r
X
r
r
X
r
r
X
X
r
r
X
r
X
X
r
r
X
r
r
r
X
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
X
X
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BFA8
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
X
BFA8
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (Don’t Care)
r (reserved bits)
X
X
X
X
X
X
X
X
X
X
X
X
•
•
•
X (64th bit)
15
Table 2
Buffer to
Main Memory
Page Program
without Built-In
Erase
Buffer to
Main Memory
Page Program
with Built-In Erase
Main Memory
Page Program
Through Buffer
Auto Page
Rewrite
Through Buffer
Page
Erase
Block
Erase
Opcode
Status
Register
83H
1
88H
1
81H
1
50H
0
82H
1
58H
0
57H
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
1
0
1
0
0
0
1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA8
PA7
PA6
PA5
PA4
PA3
X
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BFA8
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (Don’t Care)
r (reserved bits)
AT45DB011
16
AT45DB011
Figure 1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially
START
provide address
and data
BUFFER WRITE
(84H)
MAIN MEMORY PAGE PROGRAM
(82H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)
END
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
17
Figure 2. Algorithm for Randomly Modifying Data
START
provide address of
page to modify
MAIN MEMORY PAGE
If planning to modify multiple
bytes currently stored within
a page of the Flash array
to BUFFER TRANSFER
(53H)
BUFFER WRITE
(84H)
MAIN MEMORY PAGE PROGRAM
(82H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H)
(2)
Auto Page Rewrite
(58H)
INCREMENT PAGE
(2)
ADDRESS POINTER
END
Notes: 1. To preserve data integrity, each page of a DataFlash
Sector Addressing
sector must be updated/rewritten at least once
within every 10,000 cumulative page erase/program
operations within that sector.
PA2-
PA0
PA8
0
PA7
0
PA6
0
PA5
0
PA4
0
PA3
0
Sector
2. A Page Address Pointer must be maintained to indi-
cate which page is to be rewritten. The Auto Page
Rewrite command must use the address specified
by the Page Address Pointer.
X
X
X
0
1
2
0
X
X
X
X
X
1
X
X
X
X
X
3. Other algorithms can be used to rewrite portions of
the Flash array. Low power applications may choose
to wait until 10,000 cumulative page erase/program
operations have accumulated before rewriting all
pages of the sector. See application note AN-4
(“Using Atmel’s Serial DataFlash”) for more details.
AT45DB011
18
AT45DB011
Ordering Information
ICC (mA)
fSCK (MHz)
Active
Standby
Ordering Code
Package
Operation Range
15
25
0.02
AT45D011-JC
AT45D011-SC
AT45D011-XC
32J
8S2
14X
Commercial
(0°C to 70°C)
15
25
0.02
AT45D011-JI
AT45D011-SI
AT45D011-XI
32J
8S2
14X
Industrial
(-40°C to 85°C)
Package Type
32J
8S2
14X
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
8-Lead, 0.210" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
14-Lead, 0.170" Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
19
Packaging Information
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
8S2, 8-Lead, 0.210" Wide, Plastic Gull Wing Small
Outline (EIAJ SOIC)
Dimensions in Inches and (Millimeters)
.025(.635) X 30° - 45°
.020 (.508)
.012 (.305)
.045(1.14) X 45° PIN NO. 1
.012(.305)
IDENTIFY
.008(.203)
.530(13.5)
.213 (5.41) .330 (8.38)
.205 (5.21) .300 (7.62)
.553(14.0)
.490(12.4)
.547(13.9)
.032(.813)
.026(.660)
PIN 1
.021(.533)
.013(.330)
.595(15.1)
.585(14.9)
.050 (1.27) BSC
.030(.762)
.015(3.81)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.390(9.90)
AT CONTACT
POINTS
.013 (.330)
.004 (.102)
.022(.559) X 45° MAX (3X)
0
8
REF
.010 (.254)
.007 (.178)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
.035 (.889)
.020 (.508)
14X, 14-Lead, 0.170" Wide, Thin Shrink Small
Outline Package (TSSOP)
Dimensions in Millimeters and (Inches)*
INDEX MARK
PIN
1
6.50 (.256)
6.25 (.246)
4.50 (.177)
4.30 (.169)
5.10 (.201)
4.90 (.193)
1.20 (.047) MAX
.650 (.026) BSC
0.30 (.012)
0.15 (.006)
0.05 (.002)
SEATING
PLANE
0.19 (.007)
0.20 (.008)
0.09 (.004)
0
8
REF
0.75 (.030)
0.45 (.018)
*Controlling dimension: millimeters
AT45DB011
20
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