AT45D021-TI [ATMEL]
2-Megabit 5-volt Only Serial DataFlash; 2兆位5伏只能将串行数据闪存
| 型号： | AT45D021-TI |
| 厂家： | 
ATMEL |
| 描述： | 2-Megabit 5-volt Only Serial DataFlash |
| 文件： | 总18页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single 4.5V - 5.5V Supply
• Serial Interface Architecture
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 1024 Pages (264 Bytes/Page) Main Memory
• Two 264-Byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
• Internal Program and Control Timer
• Fast Page Program Time – 7 ms Typical
• 80 µs Typical Page to Buffer Transfer Time
• Low Power Dissipation
– 15 mA Active Read Current Typical
– 15 µA CMOS Standby Current Typical
• 10 MHz Max Clock Frequency
• Hardware Data Protection Feature
2-Megabit
5-volt Only
Serial
DataFlash®
• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
AT45D021
The AT45D021 is a 5-volt only, serial interface Flash memory suitable for in-system
reprogramming. Its 2,162,688 bits of memory are organized as 1024 pages of 264-
bytes each. In addition to the main memory, the AT45D021 also contains two data
SRAM buffers of 264-bytes each. The buffers allow receiving of data while a page in
the main memory is being reprogrammed. Unlike conventional Flash memories that
are accessed randomly with multiple address lines and a parallel interface, the
DataFlash uses a serial interface to sequentially access its data. The simple serial
interface facilitates hardware layout, increases system reliability, minimizes switching
(continued)
PLCC
Pin Configurations
Pin Name
Function
CS
Chip Select
Serial Clock
Serial Input
Serial Output
SCK
SI
5
6
7
8
9
29 WP
28 RESET
27 RDY/BUSY
26 NC
SCK
SI
SO
NC
NC
25 NC
NC 10
NC 11
NC 12
NC 13
24 NC
SO
23 NC
22 NC
WP
Harware Page Write
Protect Pin
21 NC
RESET
Chip Reset
Note:
PLCC package pins 16 and 17
are DON’T CONNECT.
RDY/BUSY Ready/Busy
TSOP Top View
Type 1
PLCC
GND
NC
NC
CS
SCK
SI
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
NC
2
RDY/BUSY
RESET
WP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
NC
2
4
WP
3
5
RESET
RDY/BUSY
NC
NC
4
6
NC
5
SO
NC
NC
NC
NC
NC
NC
NC
7
VCC
GND
NC
6
8
NC
7
9
NC
8
10
11
12
13
14
NC
NC
9
NC
NC
10
11
12
13
14
NC
CS
Rev. 0869B–07/98
NC
SCK
SI
NC
SO
noise, and reduces package size and active pin count. The
device is optimized for use in many commercial and indus-
trial applications where high density, low pin count, low
voltage, and low power are essential. Typical applications
for the DataFlash are digital voice storage, image storage,
and data storage. The device operates at clock frequencies
up to 10 MHz with a typical active read current consump-
tion of 15 mA.
gramming. The device operates from a single power sup-
ply, 4.5V to 5.5V, for both the program and read
operations. The AT45D021 is enabled through the chip
select pin (CS) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and
the Serial Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
To allow for simple in-system reprogrammability, the
AT45D021 does not require high input voltages for pro-
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
SCK
CS
I/O INTERFACE
RESET
V
CC
GND
RDY/BUSY
SI
SO
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Tables 1 and 2. A valid instruc-
tion starts with the falling edge of CS followed by the appro-
priate 8-bit opcode and the desired buffer or main memory
address location. While the CS pin is low, toggling the SCK
pin controls the loading of the opcode and the desired
buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are
transferred with the most significant bit (MSB) first.
first five address bits are reserved for larger density
devices (see Notes on page 8), the next 10 address bits
(PA9-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address
within the page. The 32 don’t care bits which follow the 24
address bits are sent to initialize the read operation. Fol-
lowing the 32 don’t care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS pin must remain low during the loading of the
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same page. A low to high transition on the
CS pin will terminate the read operation and tri-state the
SO pin.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 1024
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits. In the AT45D021, the
BUFFER READ: Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
buffer 2. To perform a buffer read, the eight bits of the
AT45D021
2
AT45D021
opcode must be followed by 15 don’t care bits, nine
address bits, and eight don't care bits. Since the buffer size
is 264-bytes, nine address bits (BFA8-BFA0) are required
to specify the first byte of data to be read from the buffer.
The CS pin must remain low during the loading of the
opcode, the address bits, the don’t care bits, and the read-
ing of data. When the end of a buffer is reached, the device
will continue reading back at the beginning of the buffer. A
low to high transition on the CS pin will terminate the read
operation and tri-state the SO pin.
opcode, 83H for buffer 1 or 86H for buffer 2, is followed by
the five reserved bits, 10 address bits (PA9-PA0) that spec-
ify the page in the main memory to be written, and nine
additional don't care bits. When a low to high transition
occurs on the CS pin, the part will first erase the selected
page in main memory to all 1s and then program the data
stored in the buffer into the specified page in the main
memory. Both the erase and the programming of the page
are internally self timed and should take place in a maxi-
mum time of tEP. During this time, the status register will
indicate that the part is busy.
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page
of data can be transferred from the main memory to either
buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and
55H for buffer 2, is followed by the five reserved bits, 10
address bits (PA9-PA0) which specify the page in main
memory that is to be transferred, and nine don’t care bits.
The CS pin must be low while toggling the SCK pin to load
the opcode, the address bits, and the don’t care bits from
the SI pin. The transfer of the page of data from the main
memory to the buffer will begin when the CS pin transitions
from a low to a high state. During the transfer of a page of
data (tXFR), the status register can be read to determine
whether the transfer has been completed or not.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
OUT BUILT-IN ERASE: A previously erased page within
main memory can be programmed with the contents of
either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1
or 89H for buffer 2, is followed by the five reserved bits, 10
address bits (PA9-PA0) that specify the page in the main
memory to be written, and nine additional don’t care bits.
When a low to high transition occurs on the CS pin, the part
will program the data stored in the buffer into the specified
page in the main memory. It is necessary that the page in
main memory that is being programmed has been previ-
ously programmed to all 1s (erased state). The program-
ming of the page is internally self timed and should take
place in a maximum time of tP. During this time, the status
register will indicate that the part is busy.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of
data in main memory can be compared to the data in buffer
1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and 61H for
buffer 2, is followed by 24 address bits consisting of the five
reserved bits, 10 address bits (PA9-PA0) which specify the
page in the main memory that is to be compared to the
buffer, and nine don't care bits. The loading of the opcode
and the address bits is the same as described previously.
The CS pin must be low while toggling the SCK pin to load
the opcode, the address bits, and the don't care bits from
the SI pin. On the low to high transition of the CS pin, the
264 bytes in the selected main memory page will be com-
pared with the 264 bytes in buffer 1 or buffer 2. During this
time (tXFR), the status register will indicate that the part is
busy. On completion of the compare operation, bit 6 of the
status register is updated with the result of the compare.
MAIN MEMORY PAGE PROGRAM: This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase operations. Data is first
shifted into buffer 1 or buffer 2 from the SI pin and then pro-
grammed into a specified page in the main memory. An 8-
bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed
by the five reserved bits and 19 address bits. The 10 most
significant address bits (PA9-PA0) select the page in the
main memory where data is to be written, and the next nine
address bits (BFA8-BFA0) select the first byte in the buffer
to be written. After all address bits are shifted in, the part
will take data from the SI pin and store it in one of the data
buffers. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When
there is a low to high transition on the CS pin, the part will
first erase the selected page in main memory to all 1s and
then program the data stored in the buffer into the specified
page in the main memory. Both the erase and the program-
ming of the page are internally self timed and should take
place in a maximum of time tEP. During this time, the status
register will indicate that the part is busy.
Program
BUFFER WRITE: Data can be shifted in from the SI pin
into either buffer 1 or buffer 2. To load data into either
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,
is followed by 15 don't care bits and nine address bits
(BFA8-BFA0). The nine address bits specify the first byte in
the buffer to be written. The data is entered following the
address bits. If the end of the data buffer is reached, the
device will wrap around back to the beginning of the buffer.
Data will continue to be loaded into the buffer until a low to
high transition is detected on the CS pin.
AUTO PAGE REWRITE: This mode is only needed if multi-
ple bytes within a page or multiple pages of data are modi-
fied in a random fashion. This mode is a combination of two
operations: Main Memory Page to Buffer Transfer and
Buffer to Main Memory Page Program with Built-In Erase.
A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE: Data written into either buffer 1 or buffer
2 can be programmed into the main memory. An 8-bit
3
or buffer 2) is programmed back into its original page of
main memory. An 8-bit opcode, 58H for buffer 1 or 59H for
buffer 2, is followed by the five reserved bits, 10 address
bits (PA9-PA0) that specify the page in main memory to be
rewritten, and nine additional don't care bits. When a low to
high transition occurs on the CS pin, the part will first trans-
fer data from the page in main memory to a buffer and then
program the data from the buffer back into same page of
main memory. The operation is internally self-timed and
should take place in a maximum time of tEP. During this
time, the status register will indicate that the part is busy.
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
least one bit of the data in the main memory page does not
match the data in the buffer.
The device density is indicated using bits 5, 4, and 3 of the
status register. For the AT45D021, the three bits are 0, 1,
and 0. The decimal value of these three binary bits does
not equate to the device density; the three bits represent a
combinational code relating to differing densities of Serial
DataFlash devices, allowing a total of eight different density
configurations.
If the main memory is programmed or reprogrammed
sequentially page by page, then the programming algo-
rithm shown in Figure 1 is recommended. Otherwise, if
multiple bytes in a page or several pages are programmed
randomly in the main memory, then the programming algo-
rithm shown in Figure 2 is recommended.
Read/Program Mode Summary
The modes listed above can be separated into two groups
— modes which make use of the flash memory array
(Group A) and modes which do not make use of the flash
memory array (Group B).
Group A modes consist of:
STATUS REGISTER: The status register can be used to
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of
57H must be loaded into the device. After the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most-signifi-
cant bits of the status register will contain device informa-
tion, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itself (as long as CS remains low and
SCK is being toggled) starting again with bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
1. Main memory page read
2. Main memory page to buffer 1 (or 2) transfer
3. Main memory page to buffer 1 (or 2) compare
4. Buffer 1 (or 2) to main memory page program with
built-in erase
5. Buffer 1 (or 2) to main memory page program with-
out built-in erase
6. Main memory page program
7. Auto page rewrite
Group B modes consist of:
1. Buffer 1 (or 2) read
2. Buffer 1 (or 2) write
3. Status read
Ready/busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are six operations which can
cause the device to be in a busy state: Main Memory Page
to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-In Erase,
Buffer to Main Memory Page Program without Built-In
Erase, Main Memory Page Program, and Auto Page
Rewrite.
If a Group A mode is in progress (not fully completed) then
another mode in Group A should not be started. However,
during this time in which a Group A mode is in progress,
modes in Group B can be started.
This gives the Serial DataFlash the ability to virtually
accommodate a continuous data stream. While data is
being programmed into main memory from buffer 1, data
can be loaded into buffer 2 (or vice versa). See application
note AN-4 (“Using Atmel’s Serial DataFlash”) for more
details.
HARDWARE PAGE WRITE PROTECT: If the WP pin is
held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256
pages is to first drive the protect pin high and then use the
program commands previously mentioned.
The result of the most recent Main Memory Page to Buffer
Compare operation is indicated using bit 6 of the status
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
COMP
0
1
0
X
X
X
AT45D021
4
AT45D021
RESET: A low state on the reset pin (RESET) will terminate
the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The busy status indicates that the Flash memory array and
one of the buffers cannot be accessed; read and write
operations to the other buffer can still be performed.
Power On/Reset State
When power is first applied to the device, or when recover-
ing from a reset condition, the device will default to SPI
mode 3. In addition, the SO pin will be in a high impedance
state, and a high to low stransition on the CS pin will be
required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sam-
pling the inactive clock state.
The device also incorporates an internal power-on reset
circuit; therefore, there are no restrictions on the RESET
pin during power-on sequences.
READY/BUSY: This open drain output pin will be driven
low when the device is busy in an internally self-timed oper-
ation. This pin, which is normally in a high state (through an
external pull-up resistor), will be pulled low during program-
ming operations, compare operations, and during page-to-
buffer transfers.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
DC and AC Operating Range
AT45D021
0°C to 70°C
-40°C to 85°C
4.5V to 5.5V
Com.
Ind.
Operating Temperature (Case)
V
CC Power Supply(1)
Note:
1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-
ational mode is started.
5
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
ISB
Standby Current
CS, RESET, WP = VIH, all inputs at
CMOS levels
15
30
µA
ICC1
ICC2
ILI
Active Current, Read Operation
Active Current, Program/Erase Operation
Input Load Current
f = 10 MHz; IOUT = 0 mA; VCC = 5.5V
VCC = 5.5V
15
25
25
50
10
10
0.8
mA
mA
µA
µA
V
VIN = CMOS Levels
ILO
Output Leakage Current
Input Low Voltage
VI/O = CMOS Levels
VIL
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
IOL = 2.1 mA
0.45
V
Output High Voltage
IOH = -400 µA
2.4
4.2
V
Output High Voltage
IOH = -100 µA; VCC = 4.5V
V
AC Characteristics
Symbol
fSCK
tWH
tWL
Parameter
Min
Typ
Max
Units
SCK Frequency
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
µs
µs
SCK High Time
40
40
SCK Low Time
tCS
Minimum CS High Time
CS Setup Time
250
250
250
tCSS
tCSH
tCSB
tSU
CS Hold Time
CS High to RDY/BUSY Low
Data In Setup Time
Data In Hold Time
200
10
25
0
tH
tHO
Output Hold Time
tDIS
tV
tXFR
tEP
Output Disable Time
Output Valid
75
80
Page to Buffer Transfer/Compare Time
Page Erase and Programming Time
Page Programming Time
RESET Pulse Width
RESET Recovery Time
80
10
7
150
20
tP
14
tRST
tREC
10
1
Input Test Waveforms and Measurement Levels
Output Test Load
2.4V
AC
AC
DEVICE
UNDER
TEST
2.0
DRIVING
LEVELS
MEASUREMENT
LEVEL
0.8
0.45V
30 pF
tR, tF < 20 ns (10% to 90%)
AT45D021
6
AT45D021
AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the SCK signal being low when CS makes a high-
to-low transition, and Waveform 2 shows the SCK signal
being high when CS makes a high-to-low transition. Both
wavforms show valid timing diagrams. The setup and hold
times for the SI signal are referenced to the low-to-high
transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI
Mode 0, and Waveform 2 shows timing that is compatible
with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low
tCS
CS
tCSS
tWH
tWL
tCSH
SCK
SO
SI
tV
tHO
tDIS
HIGH IMPEDANCE
tSU
HIGH IMPEDANCE
VALID OUT
tH
VALID IN
Waveform 2 – Inactive Clock Polarity High
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
SO
SI
tV
tHO
tDIS
HIGH Z
HIGH IMPEDANCE
VALID OUT
tH
tSU
VALID IN
7
Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC
tCSS
SCK
tRST
RESET
HIGH IMPEDANCE
HIGH IMPEDANCE
SO
SI
Command Sequence for Read/Write Operations (Except Status Register Read)
SI
CMD
8 bits
8 bits
8 bits
MSB
r r r r r X X X
X X X X X X X X
X X X X X X X X
LSB
Reserved for
Page Address
(PA9-PA0)
Byte/Buffer Address
larger densities
(BA8-BA0/BFA8-BFA0)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 2M bit or smaller.
3. For densities larger than 2M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
AT45D021
8
AT45D021
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
MAIN MEMORY
PAGE PROGRAM
THROUGH BUFFER 2
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER 1
BUFFER 1
WRITE
BUFFER 2
WRITE
I/O INTERFACE
SI
Main Memory Page Program through Buffers
· Completes writing into selected buffer
· Starts self-timed erase/program operation
CS
SI
CMD
r r r r r , PA9-7 PA6-0, BFA8
BFA7-0
n
n+1
Last Byte
Buffer Write
· Completes writing into selected buffer
CS
SI
CMD
X
X···X, BFA8
BFA7-0
n
n+1
Last Byte
Buffer to Main Memory Page Program
(Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS
SI
CMD
r r r r r, PA9-7
PA6-0, X
X
n = 1st byte read
Each transition represents
8 bits and 8 clock cycles
n+1 = 2nd byte read
9
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
FLASH MEMORY ARRAY
PAGE (264 BYTES)
MAIN MEMORY
PAGE TO
MAIN MEMORY
PAGE TO
BUFFER 2
BUFFER 1
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
BUFFER 1
READ
MAIN MEMORY
PAGE READ
BUFFER 2
READ
I/O INTERFACE
SO
Main Memory Page Read
CS
SI
CMD
r r r r r, PA9-7
PA6-0, BA8
BA7-0
X
X
X
X
n
n+1
SO
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS
SI
CMD
r r r r r, PA9-7
PA6-0, X
X
SO
Buffer Read
CS
SI
CMD
X
X···X, BFA8
BFA7-0
X
SO
n
n+1
n = 1st byte written
Each transition represents
8 bits and 8 clock cycles
n+1 = 2nd byte written
AT45D021
10
AT45D021
Detailed Bit-Level Read Timing – Inactive Clock Polarity Low
Main Memory Page Read
CS
SCK
1
2
3
4
5
0
60
X
61
X
62
X
63
X
64
X
65
66
67
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
MSB
Buffer Read
CS
SCK
1
0
2
3
4
5
0
36
X
37
X
38
X
39
X
40
X
41
42
43
tSU
COMMAND OPCODE
SI
1
0
1
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
MSB
Status Register Read
CS
SCK
1
2
1
3
4
5
6
7
1
8
1
9
10
11
12
16
17
tSU
COMMAND OPCODE
SI
0
0
1
0
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
1
D
0
D
7
MSB
LSB
MSB
11
Detailed Bit-Level Read Timing – Inactive Clock Polarity High
Main Memory Page Read
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
67
68
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
4
MSB
Buffer Read
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
4
MSB
Status Register Read
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
0
1
0
1
0
1
1
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO
D
7
D
6
D
5
D
4
D
0
D
7
D
6
MSB
LSB
MSB
AT45D021
12
AT45D021
Table 1.
Main Memory
Page to Buffer 1
Transfer
Main Memory
Page to Buffer 2
Transfer
Main Memory
Page to Buffer 1
Compare
Main Memory
Page to Buffer 2
Compare
Main Memory
Page Read
Buffer 1
Read
Buffer 2
Read
Buffer 1
Write
Buffer 2
Write
Opcode
52H
54H
56H
53H
0
55H
0
60H
0
61H
0
84H
87H
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
r
X
X
r
r
r
r
X
X
r
r
X
X
r
r
r
r
X
X
X
X
r
r
r
r
X
X
r
X
X
X
r
r
r
r
X
X
r
X
X
r
r
r
r
X
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
X
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BFA8
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
X
BFA8
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
X
BFA8
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
BFA8
BFA7
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (Don’t Care)
r (reserved bits)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
•
•
•
X (64th bit)
13
Table 2.
Buffer 1 to
Main
Memory
Page
Program
without
Built-In
Erase
Buffer 2 to
Main
Memory
Page
Program
without
Built-In
Erase
Buffer 1 to
Buffer 2 to
Main
Memory
Page
Program
with Built-In
Erase
Main
Memory
Page
Program
with Built-In
Erase
Main
Main
Memory
Page
Program
Through
Buffer 1
Memory
Page
Program
Through
Buffer 2
Auto Page
Rewrite
Through
Buffer 1
Auto Page
Rewrite
Through
Buffer 2
Status
Register
Opcode
82H
1
83H
1
86H
1
88H
1
89H
1
85H
1
58H
0
59H
0
57H
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (Don’t Care)
r (reserved bits)
AT45D021
14
AT45D021
Figure 1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially
START
provide address
and data
BUFFER WRITE
(84H, 87H)
MAIN MEMORY PAGE PROGRAM
(82H, 85H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
END
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
15
Figure 2. Algorithm for Randomly Modifying Data
START
provide address of
page to modify
MAIN MEMORY PAGE
If planning to modify multiple
bytes currently stored within
a page of the Flash array
to BUFFER TRANSFER
(53H, 55H)
BUFFER WRITE
(84H, 87H)
MAIN MEMORY PAGE PROGRAM
(82H, 85H)
BUFFER to MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
Auto Page Rewrite(2)
(58H, 59H)
INCREMENT PAGE
ADDRESS POINTER(2)
END
Notes: 1. To preserve data integrity, each page of the DataFlash memory array must be updated/rewritten at least once within every
10,000 cumulative page erase/program operations.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the Flash array. See application
note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
AT45D021
16
AT45D021
Ordering Information
ICC (mA)
fSCK
(MHz)
Active
Standby
Ordering Code
AT45D021-JC
AT45D021-RC
AT45D021-TC
AT45D021-JI
AT45D021-RI
AT45D021-TI
Package
32J
Operation Range
10
25
0.03
Commercial
(0°C to 70°C)
28R
28T
10
25
0.03
32J
Industrial
(-40°C to 85°C)
28R
28T
Package Type
32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC)
32J
28R
28T
28-Lead, 0.330" Wide, Plastic Gull-Wing Small Outline Package (SOIC)
28-Lead, Plastic Thin Small Outline Package (TSOP)
17
Packaging Information
32J, 32-Lead, Plastic J-Leaded Chip Carrier
Package (PLCC)
28R, 28-Lead, 0.330" Wide, Plastic Gull Wing Small
Outline Package (SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
Dimensions in Inches and (Millimeters)
.025(.635) X 30° - 45°
.045(1.14) X 45° PIN NO. 1
.012(.305)
.008(.203)
IDENTIFY
.530(13.5)
.490(12.4)
.553(14.0)
.547(13.9)
.595(15.1)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.585(14.9)
.030(.762)
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.015(3.81)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.390(9.90)
AT CONTACT
POINTS
.022(.559) X 45° MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
28T, 28-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
*Controlling dimension: millimeters
AT45D021
18
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