AT45DB041A-JC_技术文档

Features

• 100% Compatible to AT45DB041

• Single 2.5V - 3.0V or 2.7V - 3.6V Supply

• Serial Interface Architecture

• Page Program Operation

– Single Cycle Reprogram (Erase and Program)

– 2048 Pages (264 Bytes/Page) Main Memory

• Optional Page and Block Erase Operations

• Two 264-byte SRAM Data Buffers – Allows Receiving of Data

while Reprogramming of Nonvolatile Memory

• Continuous Read Capability through Entire Array

• Internal Program and Control Timer

4-megabit

2.5-volt Only

Serial

• Low Power Dissipation

– 4 mA Active Read Current Typical

– 2 µA CMOS Standby Current Typical

• 13 MHz Max Clock Frequency

• Hardware Data Protection Feature

DataFlash^®

• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

AT45DB041A

Description

The AT45DB041A is a 2.5-volt only, serial interface Flash memory suitable for

in-system reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages

of 264 bytes each. In addition to the main memory, the AT45DB041A also contains

two SRAM data buffers of 264 bytes each. The buffers allow receiving of data while

a page in the main memory is being reprogrammed. Unlike conventional Flash

(continued)

Recommend using

AT45DB041B for new

designs.

Pin Configurations

TSOP Top View

Pin Name

Function

Type 1

CS

Chip Select

Serial Clock

Serial Input

Serial Output

RDY/BUSY

RESET

WP

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

NC

2

SCK

SI

3

NC

4

NC

5

VCC

GND

NC

6

7

SO

8

NC

9

Hardware Page Write

Protect Pin

NC

10

11

12

13

14

WP

CS

SCK

SI

RESET

Chip Reset

Ready/Busy

SO

RDY/BUSY

PLCC

SOIC

CBGA Top View

Through Package

GND

NC

CS

SCK

SI

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

NC

1

2

3

2

3

NC

SCK

SI

5

6

7

8

9

29 WP

4

WP

28 RESET

27 RDY/BUSY

26 NC

5

RESET

RDY/BUSY

NC

SO

NC

A

6

NC

SO

NC

7

25 NC

B

C

D

E

8

NC

NC 10

NC 11

NC 12

NC 13

24 NC

SCK

GND

VCC

9

NC

23 NC

10

11

12

13

14

NC

22 NC

CS RDY/BSY WP

NC

21 NC

NC

SO

NC

SI

RESET

NC

Rev. 1432D–01/01

Note: PLCC package pins 16

and 17 are DON’T CONNECT.

1

memories that are accessed randomly with multiple

address lines and a parallel interface, the DataFlash uses a

serial interface to sequentially access its data. The simple

serial interface facilitates hardware layout, increases sys-

tem reliability, minimizes switching noise, and reduces

package size and active pin count. The device is optimized

for use in many commercial and industrial applications

where high density, low pin count, low voltage, and low

power are essential. Typical applications for the DataFlash

are digital voice storage, image storage, and data storage.

The device operates at clock frequencies up to 13 MHz

with a typical active read current consumption of 4 mA.

To allow for simple in-system reprogrammability, the

AT45DB041A does not require high input voltages for pro-

gramming. The device operates from a single power

supply, 2.5V to 3.0V or 2.7V to 3.6V, for both the program

and read operations. The AT45DB041A is enabled through

the chip select pin (CS) and accessed via a three-wire

interface consisting of the Serial Input (SI), Serial Output

(SO), and the Serial Clock (SCK).

All programming cycles are self-timed, and no separate

erase cycle is required before programming.

Block Diagram

WP

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER 1 (264 BYTES)

BUFFER 2 (264 BYTES)

SCK

CS

I/O INTERFACE

RESET

VCC

GND

RDY/BUSY

SI

SO

Memory Array

To provide optimal flexibility, the memory array of the

AT45DB041A is divided into three levels of granularity

comprising of sectors, blocks, and pages. The Memory

Architecture Diagram illustrates the breakdown of each

level and details the number of pages per sector and block.

All program operations to the DataFlash occur on a page-

by-page basis; however, the optional erase operations can

be performed at the block or page level.

AT45DB041A

2

AT45DB041A

Memory Architecture Diagram

SECTOR ARCHITECTURE

BLOCK ARCHITECTURE

PAGE ARCHITECTURE

SECTOR 0 = 8 Pages

2112 bytes (2K + 64)

BLOCK 0

BLOCK 1

BLOCK 2

8 Pages

PAGE 0

PAGE 1

SECTOR 0

SECTOR 1 = 248 Pages

65,472 bytes (62K + 1984)

PAGE 6

PAGE 7

PAGE 8

PAGE 9

SECTOR 2 = 256 Pages

67,584 bytes (64K + 2K)

BLOCK 30

BLOCK 31

BLOCK 32

BLOCK 33

SECTOR 3 = 512 Pages

135,168 bytes (128K + 4K)

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

BLOCK 62

BLOCK 63

BLOCK 64

BLOCK 65

SECTOR 4 = 512 Pages

135,168 bytes (128K + 4K)

SECTOR 5 = 512 Pages

135,168 bytes (128K + 4K)

PAGE 2045

PAGE 2046

PAGE 2047

BLOCK 254

BLOCK 255

Block = 2112 bytes

(2K + 64)

Page = 264 bytes

(256 + 8)

Device Operation

The device operation is controlled by instructions from the

host processor. The list of instructions and their associated

opcodes are contained in Tables 1 through 4. A valid

instruction starts with the falling edge of CS followed by the

appropriate 8-bit opcode and the desired buffer or main

memory address location. While the CS pin is low, toggling

the SCK pin controls the loading of the opcode and the

desired buffer or main memory address location through

the SI (serial input) pin. All instructions, addresses and data

are transferred with the most-significant bit (MSB) first.

Mode 3. A separate opcode (refer to Table 1 on page 8 for

a complete list) is used to select which category will be

used for reading. Please refer to the “Detailed Bit-level

Read Timing” diagrams in this datasheet for details on the

clock cycle sequences for each mode.

CONTINUOUS ARRAY READ: By supplying an initial

starting address for the main memory array, the Continu-

ous Array Read command can be utilized to sequentially

read a continuous stream of data from the device by simply

providing a clock signal; no additional addressing

information or control signals need to be provided. The

DataFlash incorporates an internal address counter that

will automatically increment on every clock cycle, allowing

one continuous read operation without the need of addi-

tional address sequences. To perform a continuous read,

an opcode of 68H or E8H must be clocked into the device

followed by 24 address bits and 32 don’t care bits. The first

four bits of the 24-bit address sequence are reserved for

upward and downward compatibility to larger and smaller

density devices (see Notes under “Command Sequence for

Read/Write Operations” diagram). The next 11 address bits

(PA10-PA0) specify which page of the main memory array

to read, and the last nine bits (BA8-BA0) of the 24-bit

address sequence specify the starting byte address within

the page. The 32 don’t care bits that follow the 24 address

bits are needed to initialize the read operation. Following

the 32 don’t care bits, additional clock pulses on the SCK

pin will result in serial data being output on the SO (serial

output) pin.

Buffer addressing is referenced in the datasheet using the

terminology BFA8-BFA0 to denote the nine address bits

required to designate a byte address within a buffer. Main

memory addressing is referenced using the terminology

PA10-PA0 and BA8-BA0 where PA10-PA0 denotes the

11 address bits required to designate a page address and

BA8-BA0 denotes the nine address bits required to desig-

nate a byte address within the page.

Read Commands

By specifying the appropriate opcode, data can be read

from the main memory or from either one of the two data

buffers. The DataFlash supports two categories of read

modes in relation to the SCK signal. The differences

between the modes are in respect to the inactive state of

the SCK signal as well as which clock cycle data will begin

to be output. The two categories, which are comprised of

four modes total, are defined as Inactive Clock Polarity Low

or Inactive Clock Polarity High and SPI Mode 0 or SPI

3

The CS pin must remain low during the loading of the

opcode, the address bits, the don’t care bits, and the read-

ing of data. When the end of a page in main memory is

reached during a Continuous Array Read, the device will

continue reading at the beginning of the next page with no

delays incurred during the page boundary crossover (the

crossover from the end of one page to the beginning of the

next page). When the last bit in the main memory array has

been read, the device will continue reading back at the

beginning of the first page of memory. As with crossing

over page boundaries, no delays will be incurred when

wrapping around from the end of the array to the beginning

of the array.

the f_BARspecification. The Burst Array Read bypasses both

data buffers and leaves the contents of the buffers

unchanged.

MAIN MEMORY PAGE READ: A Main Memory Page

Read allows the user to read data directly from any one of

the 2048 pages in the main memory, bypassing both of the

data buffers and leaving the contents of the buffers

unchanged. To start a page read, an opcode of 52H or D2H

must be clocked into the device followed by 24 address bits

and 32 don’t care bits. The first four bits of the 24-bit

address sequence are reserved bits, the next 11 address

bits (PA10-PA0) specify the page address, and the next

nine address bits (BA8-BA0) specify the starting byte

address within the page. The 32 don’t care bits which fol-

low the 24 address bits are sent to initialize the read

operation. Following the 32 don’t care bits, additional

pulses on SCK result in serial data being output on the SO

(serial output) pin. The CS pin must remain low during the

loading of the opcode, the address bits, the don’t care bits,

and the reading of data. When the end of a page in main

memory is reached during a Main Memory Page Read, the

device will continue reading at the beginning of the same

page. A low-to-high transition on the CS pin will terminate

the read operation and tri-state the SO pin.

A low-to-high transition on the CS pin will terminate the

read operation and tri-state the SO pin. The maximum SCK

frequency allowable for the Continuous Array Read is

defined by the f_CARspecification. The Continuous Array

Read bypasses both data buffers and leaves the contents

of the buffers unchanged.

BURST ARRAY READ: The Burst Array Read operation

functions almost identically to the Continuous Array Read

operation but allows much higher read throughputs by uti-

lizing faster clock frequencies. The Burst Array Read

command allows the device to burst an entire page of data

out at the maximum SCK frequency defined by the f_BAR

parameter. Differences between the Burst Array Read and

Continuous Array Read operations are limited to timing

only. The opcodes utilized and the opcode and addressing

sequence for the Burst Array Read are identical to the Con-

tinuous Array Read. The opcode of 68H or E8H must be

clocked into the device followed by the 24 address bits and

32 don’t care bits. Following the 32 don’t care bits, addi-

tional clock pulses on the SCK pin will result in serial data

being output on the SO (serial output) pin.

BUFFER READ: Data can be read from either one of the

two buffers, using different opcodes to specify which buffer

to read from. An opcode of 54H or D4H is used to read data

from buffer 1, and an opcode of 56H or D6H is used to read

data from buffer 2. To perform a Buffer Read, the eight bits

of the opcode must be followed by 15 don’t care bits, nine

address bits, and eight don’t care bits. Since the buffer size

is 264-bytes, nine address bits (BFA8-BFA0) are required

to specify the first byte of data to be read from the buffer.

The CS pin must remain low during the loading of the

opcode, the address bits, the don’t care bits, and the read-

ing of data. When the end of a buffer is reached, the device

will continue reading back at the beginning of the buffer. A

low-to-high transition on the CS pin will terminate the read

operation and tri-state the SO pin.

As with the Continuous Array Read, the CS pin must

remain low during the loading of the opcode, the address

bits, the don’t care bits, and the reading of data. During a

Burst Array Read, when the end of a page in main memory

is reached (the last bit of the page has been clocked out),

the system must delay the next SCK pulse by a minimum

time of t_BRBD. This delay is necessary to allow the device

enough time to cross over the burst read boundary, which

is defined as the end of one page in memory to the begin-

ning of the next page. When the last bit in the main memory

array has been read, the device will continue reading back

at the beginning of the first page of memory. The transition

from the last bit of the array back to the beginning of the

array is also considered a burst read boundary. Therefore,

the system must delay the SCK pulse that will be used to

read the first bit of the memory array by a minimum time of

STATUS REGISTER READ: The status register can be

used to determine the device’s Ready/Busy status, the

result of a Main Memory Page to Buffer Compare opera-

tion, or the device density. To read the status register, an

opcode of 57H or D7H must be loaded into the device.

After the last bit of the opcode is shifted in, the eight bits of

the status register, starting with the MSB (bit 7), will be

shifted out on the SO pin during the next eight clock cycles.

The five most-significant bits of the status register will con-

tain device information, while the remaining three least-

significant bits are reserved for future use and will have

undefined values. After bit 0 of the status register has been

shifted out, the sequence will repeat itself (as long as CS

remains low and SCK is being toggled) starting again with

bit 7. The data in the status register is constantly updated,

so each repeating sequence will output new data.

t_BRBD

.

A low-to-high transition on the CS pin will terminate the

read operation and tri-state the SO pin. The maximum SCK

frequency allowable for the Burst Array Read is defined by

AT45DB041A

4

AT45DB041A

Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDY/BUSY

COMP

0

1

X

Ready/Busy status is indicated using bit 7 of the status reg-

ister. If bit 7 is a 1, then the device is not busy and is ready

to accept the next command. If bit 7 is a 0, then the device

is in a busy state. The user can continuously poll bit 7 of the

status register by stopping SCK once bit 7 has been output.

The status of bit 7 will continue to be output on the SO pin,

and once the device is no longer busy, the state of SO will

change from 0 to 1. There are eight operations which can

cause the device to be in a busy state: Main Memory Page

to Buffer Transfer, Main Memory Page to Buffer Compare,

Buffer to Main Memory Page Program with Built-in Erase,

Buffer to Main Memory Page Program without Built-in

Erase, Page Erase, Block Erase, Main Memory Page Pro-

gram, and Auto Page Rewrite.

part will first erase the selected page in main memory to all

1s and then program the data stored in the buffer into the

specified page in the main memory. Both the erase and the

programming of the page are internally self-timed and

should take place in a maximum time of t_EP. During this

time, the status register will indicate that the part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-

OUT BUILT-IN ERASE: A previously erased page within

main memory can be programmed with the contents of

either buffer 1 or buffer 2. To start the operation, an 8-bit

opcode, 88H for buffer 1 or 89H for buffer 2, must be

followed by the four reserved bits, 11 address bits (PA10-

PA0) that specify the page in the main memory to be writ-

ten, and nine additional don’t care bits. When a low-to-high

transition occurs on the CS pin, the part will program the

data stored in the buffer into the specified page in the main

memory. It is necessary that the page in main memory that

is being programmed has been previously erased. The pro-

gramming of the page is internally self-timed and should

take place in a maximum time of t_P. During this time, the

status register will indicate that the part is busy.

The result of the most recent Main Memory Page to Buffer

Compare operation is indicated using bit 6 of the status

register. If bit 6 is a 0, then the data in the main memory

page matches the data in the buffer. If bit 6 is a 1, then at

least one bit of the data in the main memory page does not

match the data in the buffer.

The device density is indicated using bits 5, 4, and 3 of the

status register. For the AT45DB041A, the three bits are 0,

1, and 1. The decimal value of these three binary bits does

not equate to the device density; the three bits represent a

combinational code relating to differing densities of Serial

DataFlash devices, allowing a total of eight different density

configurations.

PAGE ERASE: The optional Page Erase command can be

used to individually erase any page in the main memory

array allowing the Buffer to Main Memory Page Program

without Built-in Erase command to be utilized at a later

time. To perform a Page Erase, an opcode of 81H must be

loaded into the device, followed by four reserved bits,

11 address bits (PA10-PA0), and nine don’t care bits. The

nine address bits are used to specify which page of the

memory array is to be erased. When a low-to-high transi-

tion occurs on the CS pin, the part will erase the selected

page to 1s. The erase operation is internally self-timed and

should take place in a maximum time of t_PE. During this

time, the status register will indicate that the part is busy.

Program and Erase Commands

BUFFER WRITE: Data can be shifted in from the SI pin

into either buffer 1 or buffer 2. To load data into either

buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,

must be followed by 15 don’t care bits and nine address

bits (BFA8-BFA0). The nine address bits specify the first

byte in the buffer to be written. The data is entered follow-

ing the address bits. If the end of the data buffer is reached,

the device will wrap around back to the beginning of the

buffer. Data will continue to be loaded into the buffer until a

low-to-high transition is detected on the CS pin.

BLOCK ERASE: A block of eight pages can be erased at

one time allowing the Buffer to Main Memory Page Pro-

gram without Built-in Erase command to be utilized to

reduce programming times when writing large amounts of

data to the device. To perform a Block Erase, an opcode of

50H must be loaded into the device, followed by four

reserved bits, eight address bits (PA10-PA3), and 12 don’t

care bits. The eight address bits are used to specify which

block of eight pages is to be erased. When a low-to-high

transition occurs on the CS pin, the part will erase the

selected block of eight pages to 1s. The erase operation is

internally self-timed and should take place in a maximum

time of t_BE. During this time, the status register will indicate

that the part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH

BUILT-IN ERASE: Data written into either buffer 1 or buffer

2 can be programmed into the main memory. To start the

operation, an 8-bit opcode, 83H for buffer 1 or 86H for

buffer 2, must be followed by the four reserved bits, 11

address bits (PA10-PA0) that specify the page in the main

memory to be written, and nine additional don’t care bits.

When a low-to-high transition occurs on the CS pin, the

5

Block Erase Addressing

PA10

PA9

PA8

PA7

PA6

0

PA5

0

PA4

0

PA3

0

PA2

X

PA1

X

PA0

X

Block

0

1

2

3

0

1

X

0

1

0

X

0

1

X

•

1

0

1

0

1

0

1

X

252

253

254

255

MAIN MEMORY PAGE PROGRAM THROUGH BUFFER:

This operation is a combination of the Buffer Write and

Buffer to Main Memory Page Program with Built-in Erase

operations. Data is first shifted into buffer 1 or buffer 2 from

the SI pin and then programmed into a specified page in

the main memory. To initiate the operation, an 8-bit

opcode, 82H for buffer 1 or 85H for buffer 2, must be fol-

lowed by the four reserved bits and 20 address bits. The 11

most significant address bits (PA10-PA0) select the page in

the main memory where data is to be written, and the next

nine address bits (BFA8-BFA0) select the first byte in the

buffer to be written. After all address bits are shifted in, the

part will take data from the SI pin and store it in one of the

data buffers. If the end of the buffer is reached, the device

will wrap around back to the beginning of the buffer. When

there is a low-to-high transition on the CS pin, the part will

first erase the selected page in main memory to all 1s and

then program the data stored in the buffer into the specified

page in the main memory. Both the erase and the program-

ming of the page are internally self-timed and should take

place in a maximum of time t_EP. During this time, the status

register will indicate that the part is busy.

transfer of a page of data (t_XFR), the status register can be

read to determine whether the transfer has been completed

or not.

MAIN MEMORY PAGE TO BUFFER COMPARE: A page

of data in main memory can be compared to the data in

buffer 1 or buffer 2. To initiate the operation, an 8-bit

opcode, 60H for buffer 1 and 61H for buffer 2, must be fol-

lowed by 24 address bits consisting of the four reserved

bits, 11 address bits (PA10-PA0) which specify the page in

the main memory that is to be compared to the buffer, and

nine don’t care bits. The CS pin must be low while toggling

the SCK pin to load the opcode, the address bits, and the

don’t care bits from the SI pin. On the low-to-high transition

of the CS pin, the 264 bytes in the selected main memory

page will be compared with the 264 bytes in buffer 1 or

buffer 2. During this time (t_XFR), the status register will indi-

cate that the part is busy. On completion of the compare

operation, bit 6 of the status register is updated with the

result of the compare.

AUTO PAGE REWRITE: This mode is only needed if multi-

ple bytes within a page or multiple pages of data are

modified in a random fashion. This mode is a combination

of two operations: Main Memory Page to Buffer Transfer

and Buffer to Main Memory Page Program with Built-in

Erase. A page of data is first transferred from the main

memory to buffer 1 or buffer 2, and then the same data

(from buffer 1 or buffer 2) is programmed back into its

original page of main memory. To start the rewrite opera-

tion, an 8-bit opcode, 58H for buffer 1 or 59H for buffer 2,

must be followed by the four reserved bits, 11 address bits

(PA10-PA0) that specify the page in main memory to be

rewritten, and nine additional don’t care bits. When a low-

to-high transition occurs on the CS pin, the part will first

transfer data from the page in main memory to a buffer and

then program the data from the buffer back into same page

Additional Commands

MAIN MEMORY PAGE TO BUFFER TRANSFER: A page

of data can be transferred from the main memory to either

buffer 1 or buffer 2. To start the operation, an 8-bit opcode,

53H for buffer 1 and 55H for buffer 2, must be followed by

the four reserved bits, 11 address bits (PA10-PA0) which

specify the page in main memory that is to be transferred,

and nine don’t care bits. The CS pin must be low while tog-

gling the SCK pin to load the opcode, the address bits, and

the don’t care bits from the SI pin. The transfer of the page

of data from the main memory to the buffer will begin when

the CS pin transitions from a low to a high state. During the

AT45DB041A

6

AT45DB041A

of main memory. The operation is internally self-timed and

should take place in a maximum time of t_EP. During this

time, the status register will indicate that the part is busy.

SERIAL CLOCK (SCK): The SCK pin is an input-only pin

and is used to control the flow of data to and from the

DataFlash. Data is always clocked into the device on the

rising edge of SCK and clocked out of the device on the

falling edge of SCK.

If a sector is programmed or reprogrammed sequentially

page-by-page, then the programming algorithm shown in

Figure 1 on page 24 is recommended. Otherwise, if multi-

ple bytes in a page or several pages are programmed

randomly in a sector, then the programming algorithm

shown in Figure 2 on page 25 is recommended.

CHIP SELECT (CS): The DataFlash is selected when the

CS pin is low. When the device is not selected, data will not

be accepted on the SI pin, and the SO pin will remain in a

high-impedance state. A high-to-low transition on the CS

pin is required to start an operation, and a low-to-high tran-

sition on the CS pin is required to end an operation.

Operation Mode Summary

WRITE PROTECT: If the WP pin is held low, the first 256

pages of the main memory cannot be reprogrammed. The

only way to reprogram the first 256 pages is to first drive

the protect pin high and then use the program commands

previously mentioned. The WP pin is internally pulled high;

therefore, connection of the WP pin is not necessary if this

pin and feature will not be utilized. However, it is recom-

mended that the WP pin be driven high externally

whenever possible.

The modes described can be separated into two groups –

modes which make use of the Flash memory array (Group

A) and modes which do not make use of the Flash memory

array (Group B).

Group A modes consist of:

1. Main Memory Page Read

2. Main Memory Page to Buffer 1 (or 2) Transfer

3. Main Memory Page to Buffer 1 (or 2) Compare

RESET: A low state on the reset pin (RESET) will terminate

the operation in progress and reset the internal state

machine to an idle state. The device will remain in the reset

condition as long as a low level is present on the RESET

pin. Normal operation can resume once the RESET pin is

brought back to a high level.

4. Buffer 1 (or 2) to Main Memory Page Program with

Built-in Erase

5. Buffer 1 (or 2) to Main Memory Page Program

without Built-in Erase

6. Page Erase

7. Block Erase

The device incorporates an internal power-on reset circuit,

so there are no restrictions on the RESET pin during

power-on sequences. The RESET pin is also internally

pulled high; therefore, connection of the RESET pin is not

necessary if this pin and feature will not be utilized. How-

ever, it is recommended that the RESET pin be driven high

externally whenever possible.

8. Main Memory Page Program through Buffer

9. Auto Page Rewrite

Group B modes consist of:

1. Buffer 1 (or 2) Read

2. Buffer 1 (or 2) Write

3. Status Register Read

READY/BUSY: This open drain output pin will be driven

low when the device is busy in an internally self-timed oper-

ation. This pin, which is normally in a high state (through

a 1kΩ external pull-up resistor), will be pulled low during

programming operations, compare operations, and during

page-to-buffer transfers.

If a Group A mode is in progress (not fully completed) then

another mode in Group A should not be started. However,

during this time in which a Group A mode is in progress,

modes in Group B can be started.

This gives the Serial DataFlash the ability to virtually

accommodate a continuous data stream. While data is

being programmed into main memory from buffer 1, data

can be loaded into buffer 2 (or vice versa). See application

note AN-4 (“Using Atmel’s Serial DataFlash”) for more

details.

The busy status indicates that the Flash memory array and

one of the buffers cannot be accessed; read and write

operations to the other buffer can still be performed.

Power-on/Reset State

When power is first applied to the device, or when recover-

ing from a reset condition, the device will default to SPI

Mode 3. In addition, the SO pin will be in a high-impedance

state, and a high-to-low transition on the CS pin will be

required to start a valid instruction. The SPI mode will be

automatically selected on every falling edge of CS by

sampling the inactive clock state.

Pin Descriptions

SERIAL INPUT (SI): The SI pin is an input-only pin and is

used to shift data into the device. The SI pin is used for all

data input including opcodes and address sequences.

SERIAL OUTPUT (SO): The SO pin is an output-only pin

and is used to shift data out from the device.

7

Table 1. Read Commands

Command

SCK Mode

Opcode

68H