AT45DB081B-CNL-2.5 [ATMEL]
Flash, 1081344X8, 6 X 8 MM, 1 MM HEIGHT, 1.27 MM PITCH, CASON-8;
| 型号： | AT45DB081B-CNL-2.5 |
| 厂家： | 
ATMEL |
| 描述： | Flash, 1081344X8, 6 X 8 MM, 1 MM HEIGHT, 1.27 MM PITCH, CASON-8 时钟 ATM 异步传输模式 内存集成电路 |
| 文件： | 总33页 (文件大小：537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single 2.5V - 3.6V or 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
• 20 MHz Max Clock Frequency
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 4096 Pages (264 Bytes/Page) Main Memory
• Supports Page and Block Erase Operations
• Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low Power Dissipation
8-megabit
2.5-volt Only or
2.7-volt Only
DataFlash®
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• Hardware Data Protection Feature
• 100% Compatible to AT45DB081 and AT45DB081A
• 5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins
• Commercial and Industrial Temperature Ranges
• Green (Pb/Halide-free) Packaging Options
AT45DB081B
Description
The AT45DB081B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideally
suited for a wide variety of digital voice-, image-, program code- and data-storage
applications. Its 8,650,752 bits of memory are organized as 4096 pages of 264 bytes
each. In addition to the main memory, the AT45DB081B also contains two SRAM
data buffers of 264 bytes each. The buffers allow receiving of data while a page in the
main memory is being reprogrammed, as well as writing a continuous data stream.
For New
Designs Use
AT45DB081D
TSOP Top View
Pin Configurations
Type 1
Pin Name
Function
RDY/BUSY
RESET
WP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
CS
Chip Select
Serial Clock
Serial Input
Serial Output
3
NC
4
SCK
SI
NC
5
VCC
GND
NC
6
7
8
NC
9
SO
NC
10
11
12
13
14
CS
SCK
SI
WP
Hardware Page Write
Protect Pin
SO
RESET
Chip Reset
RDY/BUSY Ready/Busy
SOIC
CBGA Top View
through Package
GND
NC
NC
CS
SCK
SI
1
28
VCC
NC
1
2
3
2
27
26
25
24
23
22
21
20
19
18
17
16
15
3
NC
CASON
Top View through Package
4
WP
A
B
C
D
E
5
RESET
RDY/BUSY
NC
NC
NC
6
SI
SCK
1
2
3
4
8
7
6
5
SO
SO
NC
NC
NC
NC
NC
NC
NC
7
SCK
GND
VCC
8
NC
GND
VCC
WP
9
NC
CS RDY/BSY WP
RESET
CS
10
11
12
13
14
NC
SO
NC
SI
RESET
NC
NC
NC
NC
NC
NC
Rev. 2225J–DFLSH–2/08
EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three
step Read-Modify-Write operation. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses a SPI serial interface to sequentially access its data. DataFlash supports SPI mode
0 and mode 3. The simple serial interface facilitates hardware layout, increases system
reliability, minimizes switching noise, and reduces package size and active pin count.
The device is optimized for use in many commercial and industrial applications where
high density, low pin count, low voltage, and low power are essential. The device oper-
ates at clock frequencies up to 20 MHz with a typical active read current consumption of
4 mA.
To allow for simple in-system reprogrammability, the AT45DB081B does not require
high input voltages for programming. The device operates from a single power supply,
2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The
AT45DB081B is enabled through the chip select pin (CS) and accessed via a three-wire
interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock
(SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory array
may not be erased. In other words, the contents of the last page may not be filled with
FFH.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
SCK
CS
I/O INTERFACE
RESET
VCC
GND
RDY/BUSY
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the AT45DB081B is divided into three
levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture
Diagram illustrates the breakdown of each level and details the number of pages per
sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.
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AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Memory Architecture Diagram
SECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
SECTOR 0 = 8 Pages
2112 bytes (2K + 64)
BLOCK 0
BLOCK 1
BLOCK 2
8 Pages
PAGE 0
PAGE 1
SECTOR 0
SECTOR 1 = 248 Pages
65,472 bytes (62K + 1984)
PAGE 6
PAGE 7
PAGE 8
PAGE 9
SECTOR 2 = 256 Pages
67,584 bytes (64K + 2K)
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
SECTOR 3 = 512 Pages
135,168 bytes (128K + 4K)
SECTOR 4 = 512 Pages
135,168 bytes (128K + 4K)
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 8 = 512 Pages
135,168 bytes (128K + 4K)
PAGE 4093
PAGE 4094
PAGE 4095
SECTOR 9 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 510
BLOCK 511
Block = 2112 bytes
(2K + 64)
Page = 264 bytes
(256 + 8)
Device
Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with
the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling the SCK pin controls the loading of
the opcode and the desired buffer or main memory address location through the SI (serial input)
pin. All instructions, addresses and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8 - BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA11 - PA0 and BA8 - BA0 where PA11 - PA0
denotes the 12 address bits required to designate a page address and BA8 - BA0 denotes the
nine address bits required to designate a byte address within the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two data buffers. The DataFlash supports two categories of read modes in relation to
the SCK signal. The differences between the modes are in respect to the inactive state of the
SCK signal as well as which clock cycle data will begin to be output. The two categories, which
are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock
Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to <blue>Table 1 on
page 10 for a complete list) is used to select which category will be used for reading. Please
refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock
cycle sequences for each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory
array, the Continuous Array Read command can be utilized to sequentially read a continuous
stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continuous
read operation without the need of additional address sequences. To perform a continuous read,
an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32
don’t care bits. The first three bits of the 24-bit address sequence are reserved for upward and
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2225J–DFLSH–2/08
downward compatibility to larger and smaller density devices (see Notes under “Command
Sequence for Read/Write Operations” diagram). The next 12 address bits (PA11 - PA0) specify
which page of the main memory array to read, and the last nine bits (BA8 - BA0) of the 24-bit
address sequence specify the starting byte address within the page. The 32 don’t care bits that
follow the 24 address bits are needed to initialize the read operation. Following the 32 don’t care
bits, additional clock pulses on the SCK pin will result in serial data being output on the SO
(serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a Con-
tinuous Array Read, the device will continue reading at the beginning of the next page with no
delays incurred during the page boundary crossover (the crossover from the end of one page to
the beginning of the next page). When the last bit in the main memory array has been read, the
device will continue reading back at the beginning of the first page of memory. As with crossing
over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data directly
from any one of the 4096 pages in the main memory, bypassing both of the data buffers and
leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H
must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first
three bits of the 24-bit address sequence are reserved bits, the next 12 address bits (PA11 -
PA0) specify the page address, and the next nine address bits (BA8 - BA0) specify the starting
byte address within the page. The 32 don’t care bits which follow the 24 address bits are sent to
initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK result in
serial data being output on the SO (serial output) pin. The CS pin must remain low during the
loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the
end of a page in main memory is reached during a Main Memory Page Read, the device will
continue reading at the beginning of the same page. A low-to-high transition on the CS pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to
specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1,
and an opcode of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the
eight bits of the opcode must be followed by 15 don’t care bits, nine address bits, and eight don’t
care bits. Since the buffer size is 264 bytes, nine address bits (BFA8 - BFA0) are required to
specify the first byte of data to be read from the buffer. The CS pin must remain low during the
loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the
end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A
low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
STATUS REGISTER READ: The status register can be used to determine the device’s
Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of 57H or D7H must be loaded into the
device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting
with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five
most significant bits of the status register will contain device information, while the remaining
three least-significant bits are reserved for future use and will have undefined values. After bit 0
of the status register has been shifted out, the sequence will repeat itself (as long as CS remains
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AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
low and SCK is being toggled) starting again with bit 7. The data in the status register is con-
stantly updated, so each repeating sequence will output new data.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
COMP
1
0
0
1
X
X
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is
not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level
once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once
the device is no longer busy, the state of SO will change from 0 to 1. There are eight operations
which can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main
Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-in Erase,
Buffer to Main Memory Page Program without Built-in Erase, Page Erase, Block Erase, Main
Memory Page Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using
bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the
data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does
not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB081B, the four bits are 1, 0, 0 and 1. The decimal value of these four binary bits does
not equate to the device density; the three bits represent a combinational code relating to differ-
ing densities of Serial DataFlash devices, allowing a total of sixteen different density
configurations.
Program and
Erase Commands
BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2. To load
data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, must be followed by
15 don’t care bits and nine address bits (BFA8 - BFA0). The nine address bits specify the first
byte in the buffer to be written. The data is entered following the address bits. If the end of the
data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will
continue to be loaded into the buffer until a low-to-high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into
either buffer 1 or buffer 2 can be programmed into the main memory. To start the operation, an
8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by the three reserved bits, 12
address bits (PA11 - PA0) that specify the page in the main memory to be written, and nine addi-
tional don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase
the selected page in main memory to all 1s and then program the data stored in the buffer into
the specified page in the main memory. Both the erase and the programming of the page are
internally self-timed and should take place in a maximum time of tEP. During this time, the status
register will indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously
erased page within main memory can be programmed with the contents of either buffer 1 or
buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, must be fol-
lowed by the three reserved bits, 12 address bits (PA11 - PA0) that specify the page in the main
memory to be written, and nine additional don’t care bits. When a low-to-high transition occurs
on the CS pin, the part will program the data stored in the buffer into the specified page in the
main memory. It is necessary that the page in main memory that is being programmed has been
previously erased. The programming of the page is internally self-timed and should take place in
a maximum time of tP. During this time, the status register will indicate that the part is busy.
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2225J–DFLSH–2/08
Successive page programming operations without doing a page erase are not recommended. In
other words, changing bytes within a page from a “1” to a “0” during multiple page programming
operations without erasing that page is not recommended.
PAGE ERASE: The optional Page Erase command can be used to individually erase any page
in the main memory array allowing the Buffer to Main Memory Page Program without Built-in
Erase command to be utilized at a later time. To perform a Page Erase, an opcode of 81H must
be loaded into the device, followed by three reserved bits, 12 address bits (PA11 - PA0), and
nine don’t care bits. The 12 address bits are used to specify which page of the memory array is
to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected
page to 1s. The erase operation is internally self-timed and should take place in a maximum time
of tPE. During this time, the status register will indicate that the part is busy.
BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer to Main
Memory Page Program without Built-in Erase command to be utilized to reduce programming
times when writing large amounts of data to the device. To perform a Block Erase, an opcode of
50H must be loaded into the device, followed by three reserved bits, nine address bits (PA11 -
PA3), and 12 don’t care bits. The nine address bits are used to specify which block of eight
pages is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the
selected block of eight pages to 1s. The erase operation is internally self-timed and should take
place in a maximum time of tBE. During this time, the status register will indicate that the part is
busy.
Block Erase Addressing
PA11
PA10
PA9
PA8
PA7
PA6
PA5
0
PA4
0
PA3
0
PA2
X
PA1
X
PA0
X
Block
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
0
0
0
0
0
0
1
X
X
X
0
0
0
0
0
1
0
X
X
X
0
0
0
0
0
1
1
X
X
X
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
508
509
510
511
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination of the
Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is
first shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in
the main memory. To initiate the operation, an 8-bit opcode, 82H for buffer 1 or 85H for buffer 2,
must be followed by the three reserved bits and 21 address bits. The 12 most significant address
bits (PA11 - PA0) select the page in the main memory where data is to be written, and the next
nine address bits (BFA8 - BFA0) select the first byte in the buffer to be written. After all address
bits are shifted in, the part will take data from the SI pin and store it in one of the data buffers. If
the end of the buffer is reached, the device will wrap around back to the beginning of the buffer.
When there is a low-to-high transition on the CS pin, the part will first erase the selected page in
main memory to all 1s and then program the data stored in the buffer into the specified page in
the main memory. Both the erase and the programming of the page are internally self-timed and
6
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
should take place in a maximum of time tEP. During this time, the status register will indi-
cate that the part is busy.
Additional Commands
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred
from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit
opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the three reserved
bits, 12 address bits (PA11 - PA0) which specify the page in main memory that is to be
transferred, and nine don’t care bits. The CS pin must be low while toggling the SCK pin
to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer
of the page of data from the main memory to the buffer will begin when the CS pin tran-
sitions from a low to a high state. During the transfer of a page of data (tXFR), the status
register can be read to determine whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode,
60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting of
the three reserved bits, 12 address bits (PA11 - PA0) which specify the page in the main
memory that is to be compared to the buffer, and nine don’t care bits. The CS pin must
be low while toggling the SCK pin to load the opcode, the address bits, and the don’t
care bits from the SI pin. On the low-to-high transition of the CS pin, the 264 bytes in the
selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2.
During this time (tXFR), the status register will indicate that the part is busy. On comple-
tion of the compare operation, bit 6 of the status register is updated with the result of the
compare.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or
multiple pages of data are modified in a random fashion. This mode is a combination of
two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page
Program with Built-in Erase. A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed
back into its original page of main memory. To start the rewrite operation, an 8-bit
opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by the three reserved bits,
12 address bits (PA11 - PA0) that specify the page in main memory to be rewritten, and
nine additional don’t care bits. When a low-to-high transition occurs on the CS pin, the
part will first transfer data from the page in main memory to a buffer and then program
the data from the buffer back into same page of main memory. The operation is inter-
nally self-timed and should take place in a maximum time of tEP. During this time, the
status register will indicate that the part is busy.
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2225J–DFLSH–2/08
If a sector is programmed or reprogrammed sequentially page-by-page, then the programming
algorithm shown in <blue>Figure 1 on <blue>page 26 is recommended. Otherwise, if multiple
bytes in a page or several pages are programmed randomly in a sector, then the programming
algorithm shown in <blue>Figure 2 on <blue>page 27 is recommended. Each page within a sec-
tor must be updated/rewritten at least once within every 10,000 cumulative page erase/program
operations in that sector.
Operation Mode
Summary
The modes described can be separated into two groups – modes which make use of the Flash
memory array (Group A) and modes which do not make use of the Flash memory array (Group
B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer 1 (or 2) Transfer
3. Main Memory Page to Buffer 1 (or 2) Compare
4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
If a Group A mode is in progress (not fully completed) then another mode in Group A should not
be started. However, during this time in which a Group A mode is in progress, modes in Group B
can be started.
This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream.
While data is being programmed into main memory from buffer 1, data can be loaded into buffer
2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Pin Descriptions
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into the device. The
SI pin is used for all data input including opcodes and address sequences.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out from the
device.
SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow of data
to and from the DataFlash. Data is always clocked into the device on the rising edge of SCK and
clocked out of the device on the falling edge of SCK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is not
selected, data will not be accepted on the SI pin, and the SO pin will remain in a high-impedance
state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition on the CS pin is required to end an operation.
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AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high
and then use the program commands previously mentioned. If this pin and feature are not uti-
lized it is recommended that the WP pin be driven high externally.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long
as a low level is present on the RESET pin. Normal operation can resume once the RESET pin
is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended
that the RESET pin be driven high externally.
READY/BUSY: This open drain output pin will be driven low when the device is busy in an inter-
nally self-timed operation. This pin, which is normally in a high state (through a 1 kΩ external
pull-up resistor), will be pulled low during programming operations, compare operations, and
during page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Power-on/Reset When power is first applied to the device, or when recovering from a reset condition, the device
will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-
State
to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sampling the inactive clock state. After
power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms
before an operational mode is started.
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2225J–DFLSH–2/08
Table 1. Read Commands
Command
SCK Mode
Opcode
68H
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
Continuous Array Read
Main Memory Page Read
Buffer 1 Read
E8H
52H
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
D2H
54H
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
D4H
56H
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
Buffer 2 Read
D6H
57H
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
Status Register Read
D7H
Table 2. Program and Erase Commands
Command
SCK Mode
Any
Opcode
84H
87H
83H
86H
88H
89H
81H
50H
82H
85H
Buffer 1 Write
Buffer 2 Write
Any
Buffer 1 to Main Memory Page Program with Built-in Erase
Buffer 2 to Main Memory Page Program with Built-in Erase
Any
Any
Buffer 1 to Main Memory Page Program without Built-in Erase
Buffer 2 to Main Memory Page Program without Built-in Erase
Page Erase
Any
Any
Any
Any
Any
Any
Block Erase
Main Memory Page Program through Buffer 1
Main Memory Page Program through Buffer 2
Table 3. Additional Commands
Command
SCK Mode
Any
Opcode
53H
Main Memory Page to Buffer 1 Transfer
Main Memory Page to Buffer 2 Transfer
Main Memory Page to Buffer 1 Compare
Main Memory Page to Buffer 2 Compare
Auto Page Rewrite through Buffer 1
Auto Page Rewrite through Buffer 2
Any
55H
Any
60H
Any
61H
Any
58H
Any
59H
Note:
In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity
Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).
10
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Table 4. Detailed Bit-level Addressing Sequence
Address Byte
Address Byte
Address Byte
Additional
Don’tCare
Bytes
Opcode
50H
52H
53H
54H
55H
56H
57H
58H
59H
60H
61H
68H
81H
82H
83H
84H
85H
86H
87H
88H
89H
D2H
D4H
D6H
D7H
Opcode
Required
0 1 0 1 0 0 0 0 r
0 1 0 1 0 0 1 0 r
0 1 0 1 0 0 1 1 r
0 1 0 1 0 1 0 0 x
0 1 0 1 0 1 0 1 r
0 1 0 1 0 1 1 0 x
0 1 0 1 0 1 1 1
0 1 0 1 1 0 0 0 r
0 1 0 1 1 0 0 1 r
0 1 1 0 0 0 0 0 r
0 1 1 0 0 0 0 1 r
0 1 1 0 1 0 0 0 r
1 0 0 0 0 0 0 1 r
1 0 0 0 0 0 1 0 r
1 0 0 0 0 0 1 1 r
1 0 0 0 0 1 0 0 x
1 0 0 0 0 1 0 1 r
1 0 0 0 0 1 1 0 r
1 0 0 0 0 1 1 1 x
1 0 0 0 1 0 0 0 r
1 0 0 0 1 0 0 1 r
1 1 0 1 0 0 1 0 r
1 1 0 1 0 1 0 0 x
1 1 0 1 0 1 1 0 x
1 1 0 1 0 1 1 1
1 1 1 0 1 0 0 0 r
r
r
P
P
P
x
P
P
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
x
P
x
x
x
x
x
x
x
x
x
x
x
N/A
4 Bytes
N/A
r
r
P
P
x
P
P
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
r
r
P
P
x
r
x
r
x
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
1 Byte
N/A
P
x
P
P
x
P
x
P
x
P
x
P
x
P
x
P
x
P
P
x
P
x
x
x
x
x
B
B
B
B
B
B
B
B
B
1 Byte
N/A
N/A
P
N/A
P
N/A
r
r
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
P
P
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
N/A
r
r
P
P
x
x
x
x
x
x
x
x
x
N/A
r
r
P
P
x
x
x
x
x
x
x
x
x
N/A
r
r
P
P
x
x
x
x
x
x
x
x
x
N/A
r
r
P
P
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
4 Bytes
N/A
r
r
P
P
r
r
P
P
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
N/A
r
r
P
P
N/A
x
r
x
r
x
x
B
B
x
B
B
x
B
B
x
B
B
x
B
B
x
B
B
x
B
B
x
B
B
x
B
B
x
N/A
P
P
x
P
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
P
P
P
x
P
P
x
N/A
r
r
P
P
N/A
x
r
x
r
x
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
N/A
P
P
P
x
P
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
P
x
P
P
P
x
N/A
r
r
P
P
x
x
x
x
x
x
x
x
x
N/A
r
r
P
P
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
4 Bytes
1 Byte
1 Byte
N/A
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
N/A
P
N/A
P
N/A
E8H
r
r
P
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
4 Bytes
Note:
r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
11
2225J–DFLSH–2/08
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under Bias ............................... -55°C to +125°C
Storage Temperature.................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
DC and AC Operating Range
AT45DB081B (2.5V Version)
AT45DB081B
0°C to 70° C
-40° C to 85° C
2.7V to 3.6V
Com.
Ind.
0°C to 70° C
–
Operating Temperature
(Case)
V
CC Power Supply<blue>(1)
2.5V to 3.6V
Note:
1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-
tional mode is started.
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
ISB
Standby Current
CS, RESET, WP = VCC, all inputs
at CMOS levels
2
10
µA
I
>
CC1<blue
Active Current, Read
Operation
f = 20 MHz; IOUT = 0 mA;
VCC = 3.6V
4
10
35
mA
mA
(1)
ICC2
Active Current,
VCC = 3.6V
15
Program/Erase Operation
ILI
Input Load Current
Output Leakage Current
Input Low Voltage
VIN = CMOS levels
VI/O = CMOS levels
1
1
µA
µA
V
ILO
VIL
VIH
VOL
0.6
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
V
IOL = 1.6 mA; VCC = 2.7V
IOH = -100 µA
0.4
V
VOH
VCC - 0.2V
V
Note:
1. Icc1 during a buffer read is 20mA maximum.
12
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
AC Characteristics
AT45DB081B
(2.5V Version)
AT45DB081B
Symbol
fSCK
fCAR
tWH
tWL
Parameter
Min
Max
15
Min
Max
20
Units
MHz
MHz
ns
SCK Frequency
SCK Frequency for Continuous Array Read
SCK High Time
15
20
30
30
22
22
SCK Low Time
ns
tCS
Minimum CS High Time
CS Setup Time
250
250
250
250
250
250
ns
tCSS
tCSH
tCSB
tSU
ns
CS Hold Time
ns
CS High to RDY/BUSY Low
Data In Setup Time
Data In Hold Time
200
200
ns
10
15
0
5
10
0
ns
tH
ns
tHO
Output Hold Time
ns
tDIS
tV
tXFR
tEP
Output Disable Time
Output Valid
20
25
300
20
14
8
18
20
250
20
14
8
ns
ns
Page to Buffer Transfer/Compare Time
Page Erase and Programming Time
Page Programming Time
Page Erase Time
µs
ms
ms
ms
ms
µs
tP
tPE
tBE
Block Erase Time
12
12
tRST
tREC
RESET Pulse Width
RESET Recovery Time
10
10
1
1
µs
13
2225J–DFLSH–2/08
Input Test Waveforms and Measurement Levels
2.4V
AC
AC
2.0
DRIVING
LEVELS
MEASUREMENT
LEVEL
0.8
0.45V
tR, tF < 3 ns (10% to 90%)
Output Test Load
AC Waveforms
DEVICE
UNDER
TEST
30 pF
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
tCS
CS
tCSS
tWH
tWL
tCSH
SCK
SO
SI
tV
tHO
tDIS
HIGH IMPEDANCE
tSU
HIGH IMPEDANCE
VALID OUT
tH
VALID IN
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
SO
SI
tV
tHO
tDIS
HIGH Z
HIGH IMPEDANCE
VALID OUT
tH
tSU
VALID IN
14
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC
tCSS
SCK
tRST
RESET
HIGH IMPEDANCE
HIGH IMPEDANCE
SO
SI
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
SI
CMD
8 bits
8 bits
8 bits
MSB
r
r
r
X X X X X X X X X X X X X
X X X X X X X X
LSB
Reserved for
Page Address
(PA11-PA0)
Byte/Buffer Address
larger densities
(BA8-BA0/BFA8-BFA0)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 8M bits or smaller.
3. For densities larger than 8M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
15
2225J–DFLSH–2/08
Write
The following block diagram and waveforms illustrate the various write sequences available.
Operations
FLASH MEMORY ARRAY
PAGE (256 BYTES)
BUFFER 1 TO
PAGE PROGRAM
BUFFER 2 TO
PAGE PROGRAM
THROUGH BUFFER 2
PAGE PROGRAM
BUFFER 1 (256 BYTES)
BUFFER 2 (256 BYTES)
PAGE PROGRAM
THROUGH BUFFER 1
BUFFER 1
WRITE
BUFFER 2
WRITE
I/O INTERFACE
SI
Main Memory Page Program through Buffers
· Completes writing into selected buffer
· Starts self-timed erase/program operation
CS
SI
CMD
r r r , PA11-7 PA6-0, BFA8
BFA7-0
n
n+1
Last Byte
Buffer Write
· Completes writing into selected buffer
CS
SI
CMD
X
X···X, BFA8
BFA7-0
n
n+1
Last Byte
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS
SI
CMD
r r r , PA11-7
PA6-0, X
X
n = 1st byte read
Each transition represents
8 bits and 8 clock cycles
n+1 = 2nd byte read
16
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Read
The following block diagram and waveforms illustrate the various read sequences available.
Operations
FLASH MEMORY ARRAY
PAGE (264 BYTES)
MAIN MEMORY
PAGE TO
MAIN MEMORY
PAGE TO
BUFFER 1
BUFFER 2
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
BUFFER 1
READ
MAIN MEMORY
PAGE READ
BUFFER 2
READ
I/O INTERFACE
SO
Main Memory Page Read
CS
SI
CMD
r r r , PA11-7
PA6-0, BA8
BA7-0
X
X
X
X
n
n+1
SO
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS
SI
CMD
r r r , PA11-7
PA6-0, X
X
SO
Buffer Read
CS
SI
CMD
X
X···X, BFA8
BFA7-0
X
SO
n
n+1
n = 1st byte read
Each transition represents
8 bits and 8 clock cycles
n+1 = 2nd byte read
17
2225J–DFLSH–2/08
Detailed Bit-level Read Timing – Inactive Clock Polarity Low
Continuous Array Read (Opcode: 68H)
CS
SCK
1
0
2
1
63
X
64
X
65
66
67
68
tSU
SI
tV
DATA OUT
LSB
MSB
HIGH-IMPEDANCE
SO
D
D
D
D
D
D
D
D
D
5
7
6
5
2
1
0
7
6
BIT 2111
OF
PAGE n
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: 52H)
CS
SCK
1
0
2
3
4
5
0
60
61
62
X
63
X
64
65
66
67
tSU
COMMAND OPCODE
SI
1
0
1
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
5
7
6
18
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)
Buffer Read (Opcode: 54H or 56H)
CS
SCK
1
0
2
3
4
5
0
36
X
37
X
38
X
39
X
40
X
41
42
43
tSU
COMMAND OPCODE
SI
1
0
1
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
5
7
6
Status Register Read (Opcode: 57H)
CS
SCK
1
0
2
1
3
4
5
6
7
1
8
1
9
10
11
12
16
17
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
D
D
LSB
D
7
MSB
7
6
5
1
0
19
2225J–DFLSH–2/08
Detailed Bit-level Read Timing – Inactive Clock Polarity High
Continuous Array Read (Opcode: 68H)
CS
SCK
1
2
63
64
65
66
67
tSU
SI
0
1
X
X
X
tV
DATA OUT
LSB
MSB
HIGH-IMPEDANCE
SO
D
D
D
D
D
D
D
D
D
5
7
6
5
2
1
0
7
6
BIT 2111
OF
PAGE n
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: 52H)
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
67
68
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
D
4
7
6
5
20
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)
Buffer Read (Opcode: 54H or 56H)
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
0
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
D
4
7
6
5
Status Register Read (Opcode: 57H)
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
0
1
0
1
0
1
1
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
D
D
LSB
D
MSB
D
6
7
6
5
4
0
7
21
2225J–DFLSH–2/08
Detailed Bit-level Read Timing – SPI Mode 0
Continuous Array Read (Opcode: E8H)
CS
SCK
1
1
2
1
62
X
63
X
64
X
65
66
67
tSU
SI
tV
DATA OUT
LSB
MSB
HIGH-IMPEDANCE
SO
D
D
D
D
D
D
D
D
D
5
7
6
5
2
1
0
7
6
BIT 2111
OF
PAGE n
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK
1
1
2
3
4
5
0
60
61
62
X
63
X
64
X
65
66
67
tSU
COMMAND OPCODE
SI
1
0
1
X
X
tV
DATA OUT
HIGH-IMPEDANCE
D
D
D
D
4
SO
7
6
5
MSB
22
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Detailed Bit-level Read Timing – SPI Mode 0
Buffer Read (Opcode: D4H or D6H)
CS
SCK
1
1
2
3
4
5
0
36
X
37
X
38
X
39
X
40
X
41
42
43
tSU
COMMAND OPCODE
SI
1
0
1
tV
DATA OUT
HIGH-IMPEDANCE
D
D
D
D
4
SO
7
6
5
MSB
Status Register Read (Opcode: D7H)
CS
SCK
1
1
2
1
3
4
5
6
7
1
8
1
9
10
11
12
16
17
tSU
COMMAND OPCODE
SI
0
1
0
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
D
D
D
D
4
SO
D
D
LSB
D
7
MSB
7
6
5
1
0
MSB
23
2225J–DFLSH–2/08
Detailed Bit-level Read Timing – SPI Mode 3
Continuous Array Read (Opcode: E8H)
CS
SCK
1
2
63
64
65
66
67
tSU
SI
1
1
X
X
X
tV
DATA OUT
LSB
MSB
HIGH-IMPEDANCE
SO
D
D
D
D
D
D
D
D
D
5
7
6
5
2
1
0
7
6
BIT 2111
OF
PAGE n
BIT 0
OF
PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK
1
2
3
4
5
61
62
63
64
65
66
67
68
tSU
COMMAND OPCODE
SI
1
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
D
4
7
6
5
24
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Detailed Bit-level Read Timing – SPI Mode 3 (Continued)
Buffer Read (Opcode: D4H or D6H)
CS
SCK
1
2
3
4
5
37
38
39
40
41
42
43
44
tSU
COMMAND OPCODE
SI
1
1
0
1
0
X
X
X
X
X
tV
DATA OUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
D
4
7
6
5
Status Register Read (Opcode: D7H)
CS
SCK
1
2
3
4
5
6
7
8
9
10
11
12
17
18
tSU
COMMAND OPCODE
SI
1
1
0
1
0
1
1
1
tV
STATUS REGISTER OUTPUT
HIGH-IMPEDANCE
SO
D
MSB
D
D
D
D
LSB
D
MSB
D
6
7
6
5
4
0
7
25
2225J–DFLSH–2/08
Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array
START
provide address
and data
BUFFER WRITE
(84H, 87H)
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
END
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
26
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Figure 2. Algorithm for Randomly Modifying Data
START
provide address of
page to modify
MAIN MEMORY PAGE
If planning to modify multiple
bytes currently stored within
a page of the Flash array
TO BUFFER TRANSFER
(53H, 55H)
BUFFER WRITE
(84H, 87H)
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
AUTO PAGE REWRITE(2)
(58H, 59H)
INCREMENT PAGE
ADDRESS POINTER(2)
END
Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase/program operations.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Sector Addressing
PA11
PA10
PA9
PA8
0
PA7
0
PA6
0
PA5
0
PA4
0
PA3
0
PA2 - PA0
Sector
0
0
0
0
0
0
0
0
0
X
X
X
X
0
1
2
3
0
0
X
X
X
X
X
0
1
X
X
X
X
X
1
X
X
X
X
X
X
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6
7
8
9
27
2225J–DFLSH–2/08
Ordering Information
ICC (mA)
fSCK
(MHz)
Active
Standby
Ordering Code
Package
Operation Range
20
20
15
10
0.01
AT45DB081B-CC
AT45DB081B-CNC
AT45DB081B-RC
AT45DB081B-TC
14C1
8CN3
28R
Commercial
(0°C to 70°C)
28T
10
10
0.01
0.01
AT45DB081B-CI
AT45DB081B-CNI
AT45DB081B-RI
AT45DB081B-TI
14C1
8CN3
28R
Industrial
(-40°C to 85° C)
28T
AT45DB081B-CC-2.5
AT45DB081B-CNC-2.5
AT45DB081B-RC-2.5
AT45DB081B-TC-2.5
14C1
8CN3
28R
Commercial
(0°C to 70°C)
2.5V to 3.6V
28T
Green Packaging Options (Pb/Halide-free)
ICC (mA)
fSCK
(MHz)
Active
Standby
Ordering Code
Package
Operation Range
AT45DB081B-CNU
AT45DB081B-RU
AT45DB081B-TU
AT45DB081B-CU
8CN3
28R
Industrial
20
10
0.01
28T
(-40°C to 85° C)
14C1
Note:
Green packages cover lead-free requirements.
Package Type
14-ball (3 x 5 Array), Plastic Chip-scale Ball Grid Array (CBGA)
14C1
8CN3
28R
8-pad (6 mm x 8 mm ) Chip Array Small Outline No Lead Package (CASON)
28-lead, 0.330" Wide, Plastic Gull Wing Small Outline Package (SOIC)
28-lead, Plastic Thin Small Outline Package (TSOP)
28T
28
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
Packaging Information
14C1 – CBGA
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
4.60(0.181)
4.40(0.173)
A1 ID
7.10(0.280)
6.90(0.272)
SIDE VIEW
0.30 (0.012)MIN
TOP VIEW
1.40 (0.055) MAX
2.0 (0.079)
1.50 (0.059) REF
1.25 (0.049) REF
3
2
1
A
B
C
D
E
1.00 (0.0394) BSC
NON-ACCUMULATIVE
4.0 (0.157)
0.46 (0.018)
DIA BALL TYP
1.00 (0.0394) BSC
NON-ACCUMULATIVE
BOTTOM VIEW
04/11/01
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
14C1, 14-ball (3 x 5 Array), 4.5 x 7 x 1.4 mm Body, 1.0 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA)
14C1
A
R
29
2225J–DFLSH–2/08
8CN3 – CASON
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Pad Corner
L1
0.10 mm
TYP
8
1
e
7
2
3
COMMON DIMENSIONS
(Unit of Measure = mm)
6
5
MIN
MAX
1.0
NOM
NOTE
SYMBOL
b
A
4
A1
b
0.17
0.21
0.41 TYP
8.00
0.25
4
e1
L
D
7.90
5.90
8.10
6.10
Bottom View
E
6.00
e
1.27 BSC
1.095 REF
0.67 TYP
0.97
e1
L
4
4
L1
0.92
1.02
Notes: 1. All dimensions and tolerance conform to ASME Y 14.5M, 1994.
2. The surface finish of the package shall be EDM Charmille #24-27.
3. Unless otherwise specified tolerance: Decimal 0.05, Angular 2o.
4. Metal Pad Dimensions.
7/10/03
DRAWING NO. REV.
8CN3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8CN3, 8-pad (6 x 8 x 1.0 mm Body), Lead Pitch 1.27 mm,
Chip Array Small Outline No Lead Package (CASON)
B
R
30
AT45DB081B
2225J–DFLSH–2/08
AT45DB081B
28R – SOIC
B
E
E
1
PIN 1
e
D
A
A
1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
2.39
MAX
2.79
NOM
NOTE
SYMBOL
0º ~ 8º
A
–
C
A1
D
E
0.050
18.00
11.70
8.59
–
0.356
18.50
12.50
8.79
–
Note 1
Note 1
L
–
E1
B
–
0.356
0.203
0.94
–
0.508
0.305
1.27
C
L
–
–
Note: 1. Dimensions D and E1 do not include mold Flash
or protrusion. Mold Flash or protrusion shall not exceed
0.25 mm (0.010").
e
1.27 TYP
5/18/2004
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
28R, 28-lead, 0.330" Body Width,
Plastic Gull Wing Small Outline (SOIC)
28R
R
C
31
2225J–DFLSH–2/08
28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
13.60
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.90
13.20
11.70
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
13.40
11.80
8.00
D1
E
11.90 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.55 BASIC
12/06/02
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
28T
C
R
32
AT45DB081B
2225J–DFLSH–2/08
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International
Atmel Corporation
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Literature Requests
www.atmel.com/literature
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2225J–DFLSH–2/08
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