AT48802-16QC [ATMEL]
Spread- Spectrum Signal Processor Integrated Circuit; 扩频信号处理器集成电路
| 型号： | AT48802-16QC |
| 厂家： | 
ATMEL |
| 描述： | Spread- Spectrum Signal Processor Integrated Circuit |
| 文件： | 总23页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AT48802
Features
Two Independent PN (Pseudo-Random Noise) Generators
Programmable R7 (128) to R13 (8,192) PN Sequence Lengths
Programmable Tau-Dither Amplitude
Programmable PN Phase Adjustment to 1/16 Chip
Correlation Acquisition Interface
Programming Register Control
Microcontroller Compatible Bus Interface
Patent-Pending Frequency Diversity
•
•
•
•
•
•
•
•
Low Speed Link Data Path for Supervisory and Setup Functions
•
Spread-
Spectrum
Signal
Processor
Integrated
Circuit
Description
The AT48802 Spread-Spectrum Signal Processor (SSSP) chip from Atmel handles
all PN code generation, synchronization, and handshaking required for either station
(handset or base station) of a time division duplex direct sequence spread-spectrum
cordless telephone. The AT48802 supports RF spreading and despreading for the
best rejection of interference. In conjunction with a single-chip microcontroller, the
circuit performs the following functions:
• Generates a pseudo-random sequence for spreading the transmitted signal.
• Generates a pseudo-random sequence for despreading in the receiver.
• Generates a sliding phase PN for acquiring synchronization with an incoming
signal.
Preliminary
• Controls receive signal strength measurement timing for correlation peak
detection.
• Operates a tau-dither tracking loop, with adaptive threshold, to maintain
synchronization with the incoming signal.
• Controls transmit keying antenna switching for time-division duplexing.
(continued)
Pin Configuration
64 Lead PQFP
0624A
2-1
Description (Continued)
• Controls receive audio or data sampling time and
The AT48802 unique spread-spectrum architecture capi-
talizes on the benefits of long range, signal-to-noise im-
provements, multi-path protection, and privacy. This de-
sign employs proven analog FM modulation to achieve the
lowest possible system cost yet the highest processing
gain and sound quality. The chip is a fully static design.
duration.
• Controls wake-up and sleep functionality for remote
battery operated handset.
Block Diagram
AD INTR
RSSI
RSSI D/I
TIMING
BUS
INTERFACE
BUS
ALL BLOCKS
ALL BLOCKS
A/D CLOCK
CLOCK
TIMING AND
SYNC GENERATOR
MCLK
A/D
A/D DATA
INTERFACE
BUF CLK
A/D CE
µC
TX PWR
TR SW
GAIN
PN EN
TDD
CONTROL
RF
ALL BLOCKS
CONTROLS
PA HI/LO
DITHER
UPDATE
CHIP
PHASE
CONTROL
TAU
DITHER
GENERATOR
RECEIVE
PN
GENERATOR
MUX AND
DIVERSITY
CONTROL
TX RX PN
ADVANCE
SYNC
TX AUD MUTE
RX MUTE
TX CHOP
AUD T/H
* External Components
300K*
TRANSMIT
PN
GENERATOR
MUX
AUDIO
CONTROLS
1000 pF
RC
MASTER
R
AUX T/H
RINGER
ATTN DP
CLK
INTERNAL Ckts
I/Os
FLIPSW
INTERCOM
DC PWR CTRL
SLEEP/
WAKE
CONTROLS
RX DATA
CARRIER DET
TX DATA
INTERNAL
ME DOUT
ME DIN
DATA
PATH
µC
2-2
AT48802
AT48802
Pin Description
Name
AD CE
AD DATA
AD INTR
AD SCLK
ADVANCE
AD0
Pin#
26
30
29
28
7
I/O/T
O
Description
Chip enable for external A/D converter, true = low.
8 bit serial input for external A/D.
I
O
Interrupt to controller to read A/D data, true = high.
Clock for A/D converter.
O
I
Advance or retard the chip phase. High = advance.
General purpose bi-directional port for microcontroller interface.
General purpose bi-directional port for microcontroller interface.
General purpose bi-directional port for microcontroller interface.
General purpose bi-directional port for microcontroller interface.
General purpose bi-directional port for microcontroller interface.
General purpose bi-directional port for microcontroller interface.
General purpose bi-directional port for microcontroller interface.
General purpose bi-directional port for microcontroller interface.
Address Latch Enable for port AD. Down edge latches.
Can drive dial pulse relay or other function.
37
38
39
40
44
45
46
47
36
8
I/T
I/T
I/T
I/T
I/T
I/T
I/T
I/T
I
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ALE
ATTN DP
AUD T/H
O
15
O
Driver for audio track and hold.
Replica of MCLK high speed clock input, for driving microcontroller
clock input.
BUF CLK
42
O
CARRIER
17
48
O
O
Internal data path, high = carrier present.
DC PWR CTRL
Can control a V switch to turn on and off the other circuits.
CC
Indicates whether the tau-dither state is retarded or not retarded. High
= retarded.
DITHER
54
O
FLIPSW
GAIN
21
50
I
A programmable transition on this pin will cause the chip to wake-up.
May be used to control RF receive gain.
O
9
27
32
41
57
64
GND
I
DC power return = 0 Volts
INTERCOM
MCLK
51
10
23
20
2
I
A programmable transition on this pin will cause the chip to wake-up.
High speed clock input to chip.
I
ME DIN
ME DOUT
P0.0
I
Internal data path input from RF module.
Internal data output to RF module.
General purpose output port.
O
O
O
O
P0.1
3
General purpose output port.
P0.2
4
General purpose output port.
(continued)
2-3
Pin Description (Continued)
Name
P0.3
Pin#
5
I/O/T
O
Description
General purpose output port.
P0.4
6
O
General purpose output port.
P0.5
12
13
14
16
O
General purpose output port.
P0.6
O
General purpose output port.
P0.7
O
General purpose output port.
PA HL
O
May be used to control a switch which controls the RF transmit power.
For controlling whether the RF module runs on spread-spectrum or
narrowband.
PN EN
22
T
R
58
31
34
62
63
53
55
52
18
19
O
I
Low speed clock oscillator for sleep control.
Low speed clock oscillator for sleep control.
Read strobe input for port AD, low = true.
Ring control output.
RC
!RD
I
RINGER
RSSI ID
RX DATA
RX MUTE
SYNC
O
O
O
O
T
I
RSSI integrate/dump control.
Internal data path output to microcontroller.
Mute receive audio.
PN epoch sync for receive, transmit or both.
Not a user control. Hold high always.
Controls state of RF module transmit/receive switch.
SYS RST
TR SWITCH
O
Controls switch to disconnect audio from RF module modulation input
during receive part of TDD.
TX CHOP
60
O
TX DATA
49
59
I
Internal data path input from microcontroller.
TX AUD MUTE
O
For disconnecting transmit audio when data must be transmitted.
Turns on RF module transmit power during transmit part of TDD, and
off during receive part of TDD.
TX PWR
TX/RX PN
UPDATE
56
25
61
O
T
I
Pseudo-noise sequence to RF module.
Causes chip phase control to step the phase. Used in conjunction with
ADVANCE pin 7.
1
11
24
33
43
V
CC
DC power input = +V Volts.
CC
!WR
35
I
Write strobe for Port AD. Low = true.
2-4
AT48802
AT48802
control section has a DC power control output which can
Time Division Duplex Architecture
be used to shutdown external circuits V
.
CC
The AT48802 processor supports a Time Division Duplex
(TDD) mode of operation where the transceiver transmits
information during one time period and receives during an
alternating time period. This architecture has the benefit of
optimizing the frequency channel utilization as the trans-
mit and receive frequencies can be equal to or close to
one another, without spreading at two frequencies that are
wide apart. The chip generates all TDD signals, (including
those signals that account for time delays through the RF
transceiver) that are necessary to implement a full-duplex
voice communication system. All internal timing is derived
from a master external clock. The chip is fully static and
can work at any clock frequency less than 20 MHz. In all
the following discussions the clock rate is assumed to be
15.360 MHz which is available from the companion RF
module.
The chip should always be connected to V in order for
the sleep mode to be usable; the sleep mode circuits are
CC
alive and running as long as V is applied, however their
CC
power drain is extremely small.
The sleep circuits will wake-up the chip, and other circuits
if desired, in any one of three ways.
1. Time-out from the 4 kHz Oscillator will happen about
2 seconds (one half cycle of divided by 214 ) after go-
ing to sleep. Then the remote set could, for example,
briefly listen for an incoming call using narrowband re-
ception (which has little or no acquisition time), and
listen for a predetermined tone with a very narrow-
band filter. For different wake-up periods the value of
the C can be changed.
2. If the INTERCOM input is activated. The edge sense
is programmable at R6 b7.
The 15.360 MHz master clock is internally divided down to
a 7.5 kHz TDD rate, alternating between transmit cycle
and receive cycle. That is, the transmit and receive cycles
last for 66.67µs.
3. If the FLIPSW input is activated. The edge sense is
programmable at R11 b7.
When the chip wakes up it stores information about the
reason for wake-up in the I/O Registers at R14 b0-2 so the
microprocessor can respond in a suitable way. The edge
sense for FLIPSW and INTERCOM are programmed at
R14 b4-5. (Note: Throughout this document “Rx by”
means Register x bit y; x is hexadecimal.)
Sleep Mode and Battery Functionality
In most battery applications it is necessary to power down
one end of the communication link except when a call is to
be made. The sleep mode circuits of the AT48802 control
this function.
Once the chip is awake, only the microprocessor can put
it back into sleep mode. It does this through the bus port
at R0 b7. The OPERATE bit must be set before the com-
mand to STANDBY can be recognized. If the chip is
awake and the user activates the INTERCOM or FLIPSW
inputs, then the microprocessor can sense these actions
at R14 b4-5.
The sleep mode circuits consist of a timer which runs from
a low frequency (4 kHz) RC oscillator and a set of latches
to interact with the rest of the chip which runs from the high
frequency clock input. The sleep mode circuits also can
also disable and protect the I/O’s of the high frequency
circuits. The protected mode is such that the outputs are
three-stated and the input is floating. In addition, the sleep
Figure 1. Sleep Mode Arrangement
VCC
High Speed
Processing
Circuits
High Speed I/Os
High Speed I/Os
(Operate/!Standby
and Wake 0, Wake 1)
Sleep Mode Circuits
2-5
PN Code Generation
The AT48802 contains two independently programmable
pseudo-random noise (PN) generators. One is used for
transmit and the other is for receive. They are 13-stage
linear feedback shift registers clocked at f(master clock) /
16, or the “chip rate”, normally 960 kHz (based on a 15.36
MHz master clock). Each can be programmed to operate
with lengths of 7 to 13-stages PN (8,192 bit code se-
quence length). These lengths are actually linear maximal
lengths plus one to simplify the internal circuitry. The long
code length has the benefit of having many different maxi-
mal-length codes available for co-location operation in
similar spread-spectrum equipment with minimum mutual
interference, thus allowing efficient use of frequency chan-
nels. For example, there are over 600 maximal-length se-
quences available for R13 PN, and over 300 for R11 PN.
Each maximal-length code can be considered a unique
user channel.
calling you, then the base station is the MASTER (be-
cause it is initiating the radio link) and the handset is the
SLAVE. This function is set at R0 b6.
If the chip is the MASTER, then the transmit PN generator
is clocked from the clock generator and the receive PN
generator is clocked from the chip phase control (through
the tau-dither generator). If the chip is the SLAVE, then
both PN generators are clocked from the chip phase con-
trol. Therefore the MASTER transmit has independent tim-
ing and the SLAVE locks both PN generators, via the chip
phase control, to the receive signal. Finally, the MASTER
receive PN uses the chip phase control to lock to its re-
ceived signal from the SLAVE. In this way one can see the
outline of an acquisition process.
The AT48802 PN spectral control feature enables the ra-
dio frequency transmit spectrum to easily meet the FCC
requirement that out-of-band energy in a 100 kHz band-
width be at least 20dB below in-band maximum energy in
the same bandwidth. By this means one can achieve more
spreading and more widely spaced frequency channels
with less output filtering and still meet the requirements.
The TX RX PN output is three-stated for one MCLK (mas-
ter clock, the 15.36 MHz input ) at each transition. By
means of external pull resistors, this makes the PN volt-
The “Mask” bit in each PN register controls the counter
sequence by setting feedback tap weights to either 0 or 1.
The Transmit PN Generator (Tx PN) output and the Re-
ceive PN Generator (Rx PN) output are time division mul-
tiplexed precisely by the 50% duty-cycle TX PWR signal.
That is, during the transmit cycle, only the Tx PN codes
are outputted at the TX/RX PN pin. Conversely during the
receive cycle, only the Rx PN codes are outputted. There
is no prohibition against using the same code for transmit
and receive. The shift register taps are set at R2 b0-4 and
R1 b0-7 for receive, and R4 b0-4 and R3 b0-7 for transmit.
age waveform rest at V /2 for 60 ns on every transition.
CC
The objective is that the RF transmit power should go to
zero during these periods. This introduces a spectral
notch at 7.5 MHz on each side of center. If this waveform
is faithfully preserved by the spreading mixer and sub-
sequent amplifiers then the RF transmit spectrum will
have nulls near ±7.5 MHz. This reduces the normal PN
lobes which might otherwise exceed allowed amplitude. A
particular application may or may not need this feature; for
example, if only one frequency channel is being used, and
it is in the center of the band, then depending on the output
filter one may not have this problem. In such a case a sim-
ple lowpass filter may be used from the PN generator out-
put to the RF module PN input.
For definition purposes the end of the link which is initiat-
ing the link is the MASTER, and the end which is respond-
ing is the SLAVE. This means, e.g., for a cordless phone,
if you are calling out then the handset becomes the MAS-
TER and the base station is the SLAVE. If someone is
Figure 2. PN Coupling for Spectral Control
VCC
AT48802
470
A force-load function is provided for initializing the PN gen-
erator to ensure the transmit and receive PN generator
coefficients can be loaded into the counters without lock-
ing up during the first-time loading after a power up cycle.
This is common among multiple feedback PN counters.
The force-load bit can be set by a logic 1 to the FLOAD bit
in the control register (Register 0, bit 1).
0.1 uF
TX_RX_PN
To RF Circuit
R is chosen to make the immediate
value of PN output equal to VCC /2
R
The Transmit PN and the Receive PN counters can be
synchronized by asserting a logic 1 to the PN RESET bit
in the control register (Register 0, bit 0). The PN OUT
function at R0 b5 turns on the PN when set.
2-6
AT48802
AT48802
has as an input to the RSSI variation at TDD/2 measured
through the A/D converter interface and has output using
the UPDATE and ADVANCE controls. The control loop
should null the TDD/2 signal.
Frequency Diversity Improves
Signal-to-Noise Ratio
Built into the AT48802 is an exclusive frequency diversity
function, which enhances protection from PN noise due to
imperfect correlation. The chip encodes the PN code se-
quence such that when spread, the information is modu-
lated and transmitted redundantly in two side lobes. That
is, the redundant information is contained in two main
lobes with a null at the carrier instead of the classical sin-
gle lobe spreading spectra. The spreading bandwidth also
doubles, effectively doubling the spreading chip rate. This
has the benefit of increased processing gain and greatly
reducing the residual PN noise near the carrier after cor-
relation. The frequency diversity can be user enabled by
setting the BW (Band-Width) bit high in the PN register
(Register 2, bit 7 for Receive PN, and Register 4, bit 7 for
Transmit PN). The transmit and receive PN generators are
set independently.
The available tau-dither amounts are 1/16 chip peak-to-
peak, to 15/16 chip peak-to-peak, set at R5 b3-5. Dither
on/off is controlled via R0 b4 (track = high = dither on ).
The tau-dither phase is actually only a retard or no retard
with respect to the chip phase when tau-dither is off, this
is a detail which the control system designer may need.
If the tau-dither amplitude is changed it will not take affect
until the receive PN code is reloaded. The DITHER output
of the chip tells the microprocessor whether the dither
phase is retarded (High) or not retarded. High is retarded.
RSSI Interface
The purpose of this circuitry is to provide an interface to a
serial A/D converter and an integrate/dump filter, if de-
sired. The interface is synchronized to TDD. The data from
the A/D converter is converted to parallel and loaded to
the register at R8 b0-7. The RSSI function provides an in-
tegrated/dump command output with timing completely
adjustable throughout the TDD cycle and also completely
adjustable for pulse width, except the hardware will not al-
low the timing of RSSI ID to conflict with the A/D converter
command. This allows optimum filtering of the RSSI signal
if desired. The adjustable timing is necessary to allow for
different RF designs with different amounts of delay in the
IF filter. The sense of the RSSI ID output, that is, which
way is integrate and which way is dump, is controlled via
RC b6-7
Chip Phase and Tau-Dither Control
The chip phase control circuit enables the user to step the
chip phase in either direction by amounts from 1/16 to 8/16
chip per update. The size of the step is set in R5 b0-2, the
step direction is controlled by the ADVANCE line, and the
command to do a step is by pulsing the UPDATE line. The
maximum allowed update rate is MCLOCK/32.
The tau-dither circuit is used to assist in the tracking a cor-
relation peak. This is done as follows. When the locally
generated receive PN is a good match to the incoming sig-
nal at RF, then the RF signal is accurately despread and
the signal energy is gathered into a narrow spectral region
around the carrier. If a narrow IF filter is used to filter this
signal, then when the chip phase match to the incoming
signal is good then the most possible power will get
through the narrow IF filter; when the chip phase is ad-
vanced or retarded from the best place, then the signal
power in a narrow band will fall. The tau-dither circuits,
when activated, step the PN chip phase back and forth by
a settable amount at a rate of TDD/2. If one looks at the
RF module RSSI (receive signal strength indicator) by us-
ing the A/D converter interface, then when the PN phase
is, on the average, optimum then the alternating output of
RSSI will show small variation at a rate of TDD/2. If the
peak is not centered, then the RSSI variation at TDD/2
measured through the A/D converter interface, will be-
come larger because one phase of tau-dither will produce
less RSSI than the other. Now one can track the peak by
using the microprocessor to close this control loop which
RSSI ID timing is set via RC b0-5 for delay and RD b0-5
for pulse width. The smallest step is MCLK/32 = 2 us for a
15.36 MHz clock. The 5 bits allow adjustment over a range
of TDD/2. In order to get the other half TDD cycle, one
must invert the RSSI ID bits at RC b6-7, which will invert
the waveform.
Figure 3 shows the A/D converter timing for a converter
such as the Linear Technology LTC 1196 National Semi-
conductor ADC0831 or similar.
2-7
Figure 3. A/D Converter Acquisition Timing Diagram
15 Clock Cycles
AD CE
1/16 MCLK
AD SCLK
HI Z
HI Z
AD DATA
B7 B6 B5 B4 B3 B2 B1 B0 ZERO
RF Controls
AD SCLK is always present. When AD CE is high then the
A/D converter is in the low power mode. Sampling and
conversion begins on the next negative clock edge after
AD CE goes low. For AD CE = 15 cycles wide, conversion
is guaranteed to be completed and still allow time to output
8 data bits before the AD CE goes high again.
PN EN
The PN Enable function is intended to allow the RF mod-
ule to be set to either spread-spectrum or narrow band
transmission and reception. Narrowband mode is useful
for a telephone handset to very quickly wake-up and de-
termine if it is being signaled by the base, because the
more lengthy spread-spectrum acquisition process is
avoided when no signal is present, thus making the bat-
tery standby time long. If a narrowband signal is present
then a spread-spectrum acquisition may be done to fully
establish the link. The PN EN function is controlled by R2
b5-6 to be either low, high, or three-state high impedance.
TX PWR
The Transmit Power control is synchronous with the TDD
cycle so that the transmit power can turn on and off as
needed. Its sense is settable through R6 b1-2, or it can be
set always in one state for simplex applications.
TR SW
PA HI/LO
The Transmit Receive Switch function is intended to con-
trol an antenna transmit-receive switch. Its timing is syn-
chronous with TDD and the sense is settable through R9
b4-5, or can be set always in one state for simplex appli-
cations.
Power Amp High Low is an output to control the power
amp V
in the RF module so that in narrowband mode
CC
the transmit power can be held below 1mW to meet FCC
requirements. This is controlled through R6 b0.
Gain
Audio and Line Controls
Intended to control the LNA V or current to two different
CC
states in order to provide a receive path attenuator to keep
the RSSI level in best range for chip lock loop function.
The timing is synchronous with TDD or can be set always
in one state, via R9 b2-3.
TX AUD MUTE and RX MUTE
Transmit Audio Mute and Receive Mute are intended to
allow the user audio to be turned off as needed to prevent
the other end from hearing undesired signals or noise dur-
ing acquisition, or any other time. They are set via R0 b2-
3.
(continued)
2-8
AT48802
AT48802
Audio and Line Controls (Continued)
Microprocessor Bi-Directional Bus
Interface
TX CHOP
Most control functions, including most Spread-Spectrum
controls, PN registers, RF Controls, and telephone con-
trols are loadable into a set of control registers via an 8 bit
data bus. This 8 bit bi-directional address / data bus, AD7
- AD0 (LSB), is compatible with the 80C51 / 80C52 family
of microcontroller. Register data can be read back via the
same data bus. Twenty-one control registers (HEX 00 to
HEX 14) are provided for complete implementation of
cordless phone or wireless communication systems. Reg-
ister 8 and Register 14 are read only. Do not write to R14
b7.
Transmit Chop is timed with TDD and can turn off the
audio used to modulate transmit RF during the receive pe-
riod. If the RF module has a single synthesizer then this
function is needed to prevent a large sidetone due to re-
ceive RF local oscillator modulation. R13 b0-1 control this
function to be high, low, TDD or inverse TDD.
AUD T/H and AUX T/H
Both Audio Track/Hold and Auxiliary Track/Hold have the
same, independently settable function. If this chip is used
in a high rate TDD system with analog audio modulation
then it is necessary to track and hold the receive audio
since it is only present half the time at the TDD rate of 7.5
kHz. AUD T/H provides a fully adjustable TDD rate pulse
to do this. The pulse width and pulse timing are fully ad-
justable over the range of 1 TDD cycle in increments of
1/64 of a TDD cycle, i.e., 2.1us steps, for a 15.36 MHz
clock. The delay and pulse width are programmable via
RE b0-5 and RF b0-5 (R10 b0-5 and RF b0-5 for AUX
T/H). These register settings provide TDD/2 adjustability,
and rest of the range is provided by RE b6-7 (or R10 b6-7
for AUX T/H) which can invert the output, or cause it to be
always high or always low.
The microcontroller may run using the same 15.36 MHz
master clock that the ASIC uses. However that is not ab-
solutely necessary. In any case, it must be rated to oper-
ate to at least 16 MHz frequency.
Data Bus Write Cycle Timing
The bus multiplexes address information as well as data.
Address decoding is internally provided. The register ad-
dress is directly mapped to the low-order address bits.
That is, register 0 has the address code of HEX 00, while
register A has the address code of HEX 0A. During a
WRITE cycle, the address is latched into the address de-
coder by the falling edge of the ALE signal. Data from the
microprocessor must be valid when the WR signal goes
from a low-to-high state. Figure 4 shows the WRITE cycle
timing.
Ringer and ATTN DP
Ringer is controlled by R4 b5-6 and can be output always
high, always low, three-state and 1875 Hz tone to drive a
speaker or piezo transducer. Attenuator Dial Pulse is
available to drive a relay when needed for pulse dialing. In
the handset of a telephone there is no relay (it is in the
base) so this output could be used to turn on/off an audio
attenuator.
Figure 4. Write Cycle Timing Diagram
2-9
Data Bus Read Cycle Timing
The READ cycle’s multiplexed addressing scheme is the
same as the WRITE cycle. Address mapping is also simi-
larly made to the lower-order address bits. That is, register
0 has an address code of HEX 00, while register A has an
address code of HEX 0A. Data will be valid on the data
bus and RD signal latches data as it goes from a low to a
high state. The timing is shown in Figure 5 below.
Figure 5. Read Cycle Timing Diagram
Internal Data Path
The AT48802 has a 234 bits per second synchronous full
duplex internal data path. This uses in-band signaling by
Manchester coded BPSK modulating an 1875 Hz carrier,
so voice must be disabled when data is on. This path is
intended for call setup and control functions.
To receive data, R6 b5 (RDE receive data enable) must be
set. The CARRIER output pin 17 will indicate when valid
data is available. The ME DATA IN pin 23 must be pre-
sented with a digital signal; an analog signal would have to
be sent through a comparator with the correct amount of
hysteresis first. The RX DATA pin 53 has the received
data on it for use by the microcontroller. When reception is
complete then R6 b5 should be reset.
To transmit data, R6 b6 (TDE transmit data enable) must
be set. The data presented to the TX DATA pin 49 will be
transmitted out of the ME DOUT pin 20. The input data
must be synchronized, and this can be achieved by using
the DITHER pin 54 as a clock. When transmission is com-
plete the TDE bit should be reset.
The data receiver has fully adjustable internal timing to ac-
commodate the delays of various RF designs.
2-10
AT48802
AT48802
The alternate uses of port 0.0 all deal with timing signals
associated with the phase shift keyed data path operation.
These signals are used for correctly setting the timing de-
lays associated with hardware dependent delays in the RF
and audio data circuitry. Applications using the WLI refer-
ence design are not required to adjust the timing settings
(register 12 contents).
TDD Rate
R9 b7, when set low, causes the TDD rate to be normal
7500 Hz. When set high, the TDD rate is 1875 Hz. This
mode can cause the transmit signal to be 1875 Hz square
wave AM. This is useful when the handset must wake-up
and detect whether it is being signaled in a very short time.
If the PN is turned off then the receive microcontroller can
be setup as a very narrow 1875 Hz filter and detector to
decide very quickly if the base is signaling the handset. If
not, it may go back to sleep.
Table 2. Port bit 0.1 alternate usage:
P0.1
Reg 0x13
Test Selector P0.1 Function
bits [5:4]
0
Follows P0.1 (Reg 7 bit 1) normal
operation
When in 1875 Hz TDD mode, delays and pulse widths of
RSSI, AUD T/H, AUX T/H and internal data path timing do
not change, and still work in normal specified manner, so
this mode is only for very specialized use.
0
0
1
1
Data path demodulator, phase
shift keyed output
1
0
1
Data path demodulator,
integrator’s LSB
Port 0
Data path demodulator, carrier
detector output
Port 0 is a general purpose register output port of the
AT48802. It is suitable for various housekeeping functions
of a telephone such as making LED indicators turn on,
driving a DTMF generator, keypad sensor, etc. This port is
accessed through R7 b0-7 and its outputs appear on pins
2 through 6 and 12 through 14 of the chip.
The alternate uses of port 0.1 all deal with timing signals
associated with the phase shift keyed data path operation.
These signals are used for correctly setting the timing de-
lays associated with hardware dependent delays in the RF
and audio data circuitry. Applications using the WLI refer-
ence design are not required to adjust the timing settings
(register 12 contents).
Test Aids
Sync Output
Table 3. Port bit 0.2 alternate usage:
The SYNC pin 52 can be used to observe the timing of TX
PN epoch and/or RX PN epoch. The functionality is con-
trolled by R9 b0-1. The pulse indicates when the gener-
ators start their PN codes, which are called the epochs.
When a chip phase lock is achieved, the syncs are almost
coincident.
P0.2
Test Selector P0.2 Function
Reg 0x13 bit [6]
Follows P0.2 (Reg 7 bit 2) normal
operation
0
1
Receive PN Sync Pulse
The alternate use of port 0.2 allows the receive PN gener-
ator synchronization pulse to be probed. Note that an ex-
ternal pin on the ASIC is also dedicated to this function,
and can be controlled by register 9 bits 0 and 1.
Alternate Port 0
General purpose output port 0 bits 0-3 can be pro-
grammed in normal operation by writing to register 7. Al-
ternate usage of these bits for engineering test purposes
is enabled and disabled by first writing the desired configu-
ration to register 13 (decimal 19). Note that in each case,
a zero bit in register 13 enables the standard configuration
for the ASIC port 0 outputs.
Table 4. Port bit 0.3 alternate usage:
P0.3
Test Selector P0.3 Function
Reg 0x13 bit [7]
Follows P0.3 (Reg 7 bit 3) normal
operation
0
1
Table 1. Port bit 0.0 alternate usage:
Transmit PN Sync
P0.0
Reg 0x13
Test Selector P0.0 Function
The alternate use of port 0.3 allows the transmit PN gen-
erator synchronization pulse to be probed. Note that an
external pin on the ASIC is also dedicated to this function,
and can be controlled by register 9 bits 0 and 1.
bits [3:2]
0
Follows P0.0 (Reg 7 bit 0) normal
operation
0
0
1
Data path demodulator, receive
clock
1
0
Data path demodulator, receive
local oscillator
Data path demodulator, dump
signal (bit synchronized integrate
and dump processing)
1
1
2-11
Register Structure
Address/Usage
7
6
5
4
3
2
1
0
0x00
General Operation
Operate
!Standby
Master
!Slave
Track/
!Acquire
TX audio
mute
RX audio
mute
PN OUT
Force Load RE-SYNC
0x01
RX-P8
RX-BW
TX-P8
RX-P7
RX-P6
RX-P5
RX-P13
TX-P5
RX-P4
RX-P12
TX-P4
RX-P3
RX-P11
TX-P3
RX-P2
RX-P10
TX-P2
RX-P1
RX-P9
TX-P1
TX-P9
RX Polynomial
0x02
RX Polynomial
PN EN 1
PN EN 0
0x03
TX Polynomial
TX-P7
Ring
TX-P6
Ring
0x04
TX Polynomial
TX-BW
TX-P13
TX-P12
TX-P11
TX-P10
Function 1 Function 0
0x05
ACQ and Track
Control
PH1
PH0
TDE
TD2
TD1
TD0
N2
N1
N0
0x06
TX PWR / DPATH /
Ring
Flip Switch
Polarity
(Wakeup)
Ring Attn
Dial Pulse
RDE
RDP
TX PWR 1 TX PWR 0
PA HI/LO
0x07
General Purpose
Port
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
0x08
A/D bit 7
A/D bit 6
Soft Reset
A/D bit 5
TR SW 1
A/D bit 4
TR SW 0
A/D bit 3
GAIN 1
A/D bit 2
GAIN 0
A/D bit 1
A/D bit 0
RSSI A/D
0x09
Gain / TDD Rate /
Syncs
TDD Rate
Select
1875/!7500
Sync Mode Sync Select
(Bin/Tri)
TX/!RX
(continued)
2-12
AT48802
AT48802
Register Structure (Continued)
Address/Usage
7
6
5
4
3
2
1
0
0x0A
TX PN
Mask
TX PN
Mask
bit 12
TX PN
Mask
bit 11
TX PN
Mask
bit 10
TX PN
Mask
bit 9
TX PN
Mask
bit 8
TX PN
Mask
bit 7
TX PN
Mask
bit 6
TX PN
Mask
bit 5
0x0B
RX PN
Mask
RX PN
Mask
bit 12
RX PN
Mask
bit 11
RX PN
Mask
bit 10
RX PN
Mask
bit 9
RX PN
Mask
bit 8
RX PN
Mask
bit 7
RX PN
Mask
bit 6
RX PN
Mask
bit 5
0x0C
RSSI
Delay
RSSI ID 1
RSSI ID 0
TD5
TD5
TD5
TD4
TW4
TD4
TW4
TD4
TW4
TD3
TW3
TD3
TW3
TD3
TW3
TD2
TW2
TD2
TW2
TD2
TW2
TD1
TW1
TD1
TW1
TD1
TW1
TD0
TW0
TD0
TW0
TD0
TW0
0x0D
RSSI
Width
0x0E
AUD T/H
Delay
AUD T/H 1 AUD T/H 0
AUX T/H 1 AUX T/H 0
0x0F
AUD T/H
Width
0x10
AUX T/H
Delay
0x11
AUX T/H
Width
Intercom
Polarity
(Wakeup) 1 = Aux T/H
P0.7 mux
0 = Reg 7
0x12
Data Path
Delays
DPATH
DUMP 3
DPATH
DUMP 2
DPATH
DUMP 1
DPATH
LO1
DPATH
LO0
DPATH
CLK2
DPATH
CLK1
DPATH
CLK0
0x13
Bit
P0.3 OPT
P0.2 OPT P0.1 OPT1 P0.1 OPT0 P0.0 OPT1 P0.0 OPT0
TX CHOP 1 TX CHOP 0
Wake
TXPN Sync RX PN Sync
Test Mode
(dpath)
(dpath)
(dpath)
(dpath)
Functions
Sense
Intercom
Input Line
Sense Flip
Switch
Input Line
Wake
Intercom
sw latch
0x14
Sleep Mode / Wake
WAKE Flip
sw latch
Timer
time-out
latch
2-13
Register Functions
Function
Register
Bit #
Description
0 = Normal PN counter operation.
1 = Re-synchronizes RX PN and TX PN generators to
the same counting state.
RESYNC
0
0
0 = No action.
1 = Forces an immediate loading of the TX PN
polynomial from the transmit polynomial register into the
PN generator and the RX PN polynomial from the
receive polynomial register into the RX PN generator.
Force Load
0
1
0 = Sets a logic 0 to the RX MUTE pin 55.
1 = Sets a logic 1 to the RX MUTE pin 55.
RX Audio Mute
TX Audio Mute
0
0
0
0
2
3
4
5
0 = Sets a logic 0 to the TX MUTE pin 59.
1 = Sets a logic 1 to the TX MUTE pin 59.
Track
!Acquire
0 = tau-dither on.
1 = tau-dither off.
0 = TX RX PN pin 25 is disabled and always low.
1 = TX RX PN pin 25 is enabled and toggles.
PN OUT
0 = Sets the unit to Slave mode of operation (Unit
receiving a link setup request).
1 = Master mode operation (Unit originating a link setup
Master
!Slave
0
6
request).
Operate
!Standby
0
1
7
See section 2.2
RX-P1 through
RX-P8
Low-order receive PN polynomial (shift register tap
weights). P1 is LSB.
0-7
RX-P9 through
RX-P13
High-order receive PN polynomial (shift register tap
weights). P13 is MSB.
2
2
0-4
5-6
PN EN
PN EN 0
PN EN 1
PN EN pin 22
0
0
1
1
0
1
0
1
0
Three-state
Three-state
1
0 = Disables receive diversity mode.
1 = Enables receive diversity mode.
RX-BW
2
3
7
TX-P1 through
TX-P8
0-7
Low-order transmit PN polynomial. P1 is LSB.
High-order transmit PN polynomial. P13 is MSB.
TX-P9 through
TX-P13
4
4
0-4
5-6
Ring Func 0
Ring Func 1
Ring F0
Ring F1
Ringer pin 62
0
0
1
1
0
1
0
1
0
Three-state
1875 Hz
1
(continued)
2-14
AT48802
AT48802
Register Functions (Continued)
Function
Register
Bit #
Description
0 = Disables transmit diversity mode.
1 = Enables transmit diversity mode.
TX-BW
4
7
N0, N1, N2
(N0 = LSB)
5
0-2
Chip Phase Control Step Size.
N2, N1, N0
000
Step Size
1/16 Chip
2/16 Chip
3/16 Chip
4/16 Chip
5/16 Chip
6/16 Chip
7/16 Chip
8/16 Chip
001
010
011
100
101
110
111
TD0, TD1, TD2
(TD0 = LSB)
5
3-5
Tau-Dither Amplitude.
TD2, TD1, TD0 Peak-to-Peak Amplitude
000
001
010
011
100
101
110
111
1/16 Chip
3/16 Chip
5/16 Chip
7/16 Chip
9/16 Chip
11/16 Chip
13/16 Chip
15/16 Chip
Note: To load a new tau-dither value, it must be
followed by the loading of a Receiver PN code to latch
in the new Tau-Dither.
Selects one of 4 phases of the R11 sync (from the
Master’s Tx PN generator) with which to reset the
Master’s receive PN Generator when attempting to
acquire code lock with the Slave unit. This is useful in
acquisition when transitioning from R11 to R13 which is
four times as long. This specialized function is used in
the Atmel acquisition software.
PH0, PH1
PA HI/LO
5
6
6, 7
0 = PA HI/LO pin 16 low.
1 = PA HI/LO pin 16 high.
Intended for control of RF transmit power to a lower
level in narrowband mode.
0
(continued)
2-15
Register Functions (Continued)
Function
Register
Bit #
Description
Turn RF transmitter on or off.
TX PWR 0
TX PWR 1
6
1-2
TX PWR 0
TX PWR 1
TX PWR pin 56
0
0
1
1
0
1
0
1
0
TDD
!TDD
1
For attenuating the ring amplitude as heard in the
handset, or for controlling an off hook/pulse dial relay in
the base station of a telephone. Useful in handset when
there is no separate ring transducer from the speaker.
1 sets 1, 0 sets 0 at pin 8.
Ring Attn or
Dial Pulse
6
3
Receive data polarity. Inverts or does not invert receive
data in the internal data path.
RDP
6
5
6
7
4
Receive and transmit data enable.
0 = disable, 1 = enable input pins 49 and 53.
RDE TDE
5-6
7
Flip Switch
Polarity
Wakeup edge sense polarity for input pin 21
0 = down edge, 1 = up edge sensing.
Controls general purpose output port at pins 2-6 and
12-14. Non-inverting.
Port 0
0-7
Read only, contains the data from the A to D converter
gathered serially from pins 26, 28, 30. Non-inverting. Bit
0 = LSB.
RSSI AD
8
9
0-7
0-1
Sync Select
Sync Mode
These bits control how transmit and receive epoch sync
pulses appear on pin 52.
Select
Mode
Sync pin 52
Trinary, rec up,
xmt down
0
0
1
1
0
1
0
1
Binary, rec up
Trinary, xmt up,
rec down
Binary, xmt up
Intended to control two receive gain states in the RF
module.
Gain 0, 1
9
2-3
Gain 0
Gain 1
Gain pin 50
0
0
1
1
0
1
0
1
0
TDD
!TDD
1
(continued)
2-16
AT48802
AT48802
Register Functions (Continued)
Function
Register
Bit #
Description
Intended to control the transmit-receive switch in the RF
module.
TR SW 0, 1
9
4-5
TR SWITCH
TR SW 0
TR SW 1
pin 19
0
0
1
0
1
0
0
TDD
!TDD
1
1
1
Soft Reset
9
9
6
7
Not a user control.
TDD Rate Select
See Section 2.11, 1 = 1875 Hz, 0 = 7500 Hz.
These set the length of the PN code. Function is the
same for transmit and receive.
TX PN Mask
RX PN Mask
A
B
0-7
0-7
Shift Register Size
Code Length
8192
4096
2048
1024
512
Mask
FF
7F
R13
R12
R11
R10
R9
3F
1F
0F
R8
256
07
R7
128
03
R6
64
01
RSSI ID pin 63 delay with respect to internal TDD
positive edge. 1 LSB = 2.1 µs or 32MCLK. Bit 0 = LSB.
Range is TDD/2. The range is increased to TDD by
inverting the signal using RSSI I/D bits 6 and 7 (see
below).
RSSI Delay
C
C
0-5
6-7
RSSI ID
0-1
Used in conjunction with RSSI Delay.
RSSI ID
RSSI ID
RSSI ID pin 63
0
0
1
1
0
1
0
1
0
TDD, delayed
!TDD, delayed
1
Intended to be used with an integrate and dump filter;
See Section 2.6.
Used in conjunction with RSSI Delay.
1 LSB = 2.1µs or 32MCLK. Bit 0 = LSB.
RSSI Width
D
0-4
AUD TH Delay
AUD TH 0-1
AUD TH Width
E
E
F
0-5
6-7
0-4
Same functionality as RSSI above except applies to the
AUD TH signal at pin 15. See section 2.8.3.
(continued)
2-17
Register Functions (Continued)
Function
Register
Bit #
Description
AUX TH Delay
AUX TH 0-1
AUX TH Width
10
10
11
0-5
6-7
0-4
Same functionality as RSSI above except applies to the
AUX TH signal at pin 14 if so selected by Register 11 bit
6 (see below). See section 2.8.3. Pin 14 is dual use.
Controls a multiplexed output pin 14. 0 selects register
7 bit 6 non-inverted. 1 selects AUX TH function, see
above.
Port 0 bit 7 Mux
Intercom Polarity
11
11
6
7
Wakeup edge sense polarity for input pin 51. 0 = down
edge, 1 = up edge sensing.
These bits set the delays in the various sub-functions of
the internal data path receiver. This allows any arbitrary
time delay in the RF module design and still optimally
detect data.
Data Path
Delays
12
13
0-7
0-1
Intended to control an audio switch which disconnects
audio from the RF module modulation input during the
receive part of TDD. Pin 60.
TX CHOP 0, 1
TX CHOP 0
TX CHOP 1
TX CHOP pin 60
0
0
1
1
0
1
0
1
0
TDD
!TDD
1
Allows internal data path signals to be observed at pin 2
for engineering purposes, to assist in setting the data
path delays.
P0.0 OPT 0, 1
13
2-3
Port 0.0 muxed
P0.0 OPT1
P0.0 OPT0
function
0
0
0
1
Register 7 bit 0
RX_CLK
(me_din_smp)
Rx_LO
(delay_div512)
1
1
0
1
Dump
Equivalent function to Port 0 bit 0 above, except for Port
0 bit 1, pin 3.
P0.1 OPT 0, 1
13
4-5
Port 0.1 muxed
P0.1 OPT1
P0.1 OPT0
function
0
0
0
1
Register 7 bit 1
Demod, PSK
Demod O/P
Demod,
Integrator’s LSB
1
1
0
1
Demod, Carrier
Detector
(continued)
2-18
AT48802
AT48802
Register Functions (Continued)
Function
Register
Bit #
Description
0 selects register 7 bit 2 to output at pin 4.
1 selects RX PN Sync to output at pin 4.
P0.2 OPT
13
6
0 selects register 7 bit 3 to output at pin 5.
1 selects TX PN Sync to output at pin 5.
P0.3 OPT
13
14
7
Allows the microcontroller to see why the unit came
awake, to allow proper response.
Wake latches
0-2
Wake 0
Wake 1 Wake 2
Wakeup Cause
power on reset
timer
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
FLIPSW
timer and FLIPSW
INTERCOM
timer and
INTERCOM
1
0
1
FLIPSW and
INTERCOM
1
1
1
1
0
1
Everything
WAKE bits are cleared (set to 0) upon entering the
sleep mode. See section 2.2.
Direct sense of FLIPSW input pin 21. For example,
when the handset is already awake and the user wants
to hang up and start a new call, then the microcontroller
could sense this by scanning this bit. Not latched.
Sense FLIPSW
14
4
Direct sense of INTERCOM pin 51. For example, when
the handset is already awake and the user wants to
hang up and start an intercom call, then the
microcontroller could sense this by scanning this bit. Not
latched.
Sense
INTERCOM
14
14
5
7
Test Mode
Not a user function.
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Lead Temperature ...........................................300°C
Storage Temperature...................... -55°C to +125°C
V
, Supply Voltage .......................... -0.3V to +7.0V
CC
Input Pin Voltage........................-0.3V to V + 0.3V
CC
Input Pin Current.......................... -10 mA to +10 mA
2-19
Operating Characteristics
Parameter
, Supply Voltage
Conditions
Min
Max
6
Units
Volts
mA
V
4
CC
V
CC
= 5.0V,
TBD
I
, Supply Current
MCLK = 15.36 MHz
Standby Mode
DD
TBD
70
µA
Ambient Temperature
0
°C
DC Electrical Characteristics (1)
Unless Otherwise Specified, V = +5V, 0°C ≤ T ≤ 70°C
CC
A
Parameter
CMOS Input Specifications
V , Low Level Input Voltage
Min
Max
Units
0.3 V
Volts
Volts
µA
IL
CC
V , High level Input Voltage
IH
0.7 V
CC
I , Low Level Input Current
IL
-1.0
1.0
I , High Level Input Current
IH
µA
CMOS Output Specifications
V
V
, Low Level Output Voltage
0.4
Volts
Volts
OL
, High Level Output Voltage
OH
3.5
Output Current
Pins 15, 17, 19, 20, 26, 28, 29, 50, 53, 54, 55,
56, 58, 59, 60, 63
2
mA
Pins 16, 22, 37, 38, 39, 40, 44, 45, 46, 47, 52, 62
4
8
mA
mA
mA
mA
Pins 2, 3, 4, 5, 6, 12, 13, 14, 42
Pin 48
16
24
Pins 8, 25
Note: 1. Sleep Mode
The following pins are functional and active during sleep mode: all VCC and GND; 18, 21, 31, 48, 51, 58. All other inputs
are protected so that regardless of source voltage, within normal 0 to VCC limits, and impedance, including floating, no
static current larger than normal static current will be drawn from the power supply. All other outputs are three-stated by a
special internal control line from the sleep mode control circuits.
2-20
AT48802
AT48802
AC Electrical Characteristics
0°C ≤ T ≤ +70°C, 4.0V ≤ V ≤ 6.0
A
CC
T
= 1/f
CLK
MCLK
Parameter
Min
50
Max
Units
ns
t
t
t
t
, ALE High Pulse Width
ALE
, Address Valid to ALE Low
, Address Hold After ALE Low
10
ns
AV
10
ns
AH
, ALE Low to WR Low
AWL
20
ns
t , WR Pulse Width
2 T
sec
sec
ns
W
CLK
t , RD Pulse Width
R
2 T
CLK
t
t
, Data Valid to WR Transition
0
DVW
, Data Valid to RD Transition
10
ns
DVR
t , Data Hold After WR
10
10
10
0
ns
H
t
t
t
t
t
, WR High to ALE High
ns
WAH
, RD High to ALE High
, RD to Valid Data
ns
RAH
T
sec
sec
ns
RVD
CLK
, Data Hold After RD
0
T
CLK
DH
, ALE Low to RD Low
20
ARL
2-21
Figure 6. Write Cycle Timing Diagram
Figure 7. Read Cycle Timing Diagram
2-22
AT48802
AT48802
Ordering Information
Speed
(MHz)
Power
Ordering Code
Package
Operation Range
Supply
16
5V ± 20%
AT48802-16QC
64Q
Commercial
(0°C to 70°C)
AT48802-16QI
64Q
Industrial
(-40°C to 85°C)
Package Type
64 Lead, Plastic Gull Wing Quad Flatpack (PQFP)
64Q
2-23
相关型号：
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