AT49BV001N-12JC [ATMEL]

1-Megabit 128K x 8 Single 2.7-Volt Battery-Voltage Flash Memory; 1兆位128K ×8单2.7伏的电池电压闪存
AT49BV001N-12JC
型号: AT49BV001N-12JC
厂家: ATMEL    ATMEL
描述:

1-Megabit 128K x 8 Single 2.7-Volt Battery-Voltage Flash Memory
1兆位128K ×8单2.7伏的电池电压闪存

闪存 电池
文件: 总20页 (文件大小:174K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Features  
Single Supply for Read and Write: 2.7V to 3.6 (BV), 3.0 to 3.6V (LV)  
Fast Read Access Time - 70 ns  
Internal Program Control and Timer  
Sector Architecture  
– One 16K Byte Boot Block with Programming Lockout  
– Two 8K Byte Parameter Blocks  
– Two Main Memory Blocks (32K, 64K) Bytes  
Fast Erase Cycle Time - 10 seconds  
Byte By Byte Programming - 30 µs/Byte Typical  
Hardware Data Protection  
DATA Polling For End Of Program Detection  
Low Power Dissipation  
1-Megabit  
(128K x 8)  
– 25 mA Active Current  
– 50 µA CMOS Standby Current  
Single 2.7-Volt  
Battery-Voltage™  
Flash Memory  
Typical 10,000 Write Cycles  
Description  
The AT49BV/LV001(N)(T) is a 3-volt-only in-system reprogrammable Flash Memory.  
Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with  
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70  
ns with power dissipation of just 90 mW over the commercial temperature range.  
When the device is deselected, the CMOS standby current is less than 50 µA. For the  
(continued)  
AT49BV001  
AT49LV001  
DIP Top View  
Pin Configurations  
AT49BV001N  
AT49LV001N  
AT49BV001T  
AT49LV001T  
AT49BV001NT  
AT49LV001NT  
Pin Name  
A0 - A16  
CE  
Function  
*RESET  
A16  
A15  
A12  
A7  
1
2
3
4
5
6
7
8
9
32 VCC  
31 WE  
30 NC  
Addresses  
29  
A14  
28 A13  
27 A8  
Chip Enable  
Output Enable  
Write Enable  
RESET  
A6  
A5  
26 A9  
OE  
A4  
25 A11  
24 OE  
23 A10  
22 CE  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
A3  
WE  
A2 10  
A1 11  
A0 12  
RESET  
I/O0 - I/O7  
DC  
I/O0 13  
I/O1 14  
I/O2 15  
GND 16  
Data Inputs/Outputs  
Don’t Connect  
No Connect  
NC  
VSOP Top View (8 x 14mm) or  
TSOP Top View (8 x 20mm)  
Type 1  
PLCC Top View  
A11  
A9  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE  
2
A10  
CE  
A8  
3
A13  
A14  
NC  
4
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
GND  
I/O2  
I/O1  
I/O0  
A0  
A7  
A6  
A5  
A4  
A3  
5
6
7
8
9
29 A14  
28 A13  
27 A8  
26 A9  
25 A11  
24 OE  
23 A10  
22 CE  
21 I/O7  
5
6
WE  
7
VCC  
*RESET  
A16  
A15  
A12  
A7  
8
9
10  
11  
12  
13  
14  
15  
16  
A2 10  
A1 11  
A0 12  
I/O0 13  
A6  
A1  
A5  
A2  
A4  
A3  
Rev. 1110A–07/98  
*Note: This pin is a DC on the AT49BV001N(T) and AT49LV001N(T).  
AT49BV/LV001NT pin 1 for the DIP and PLCC packages  
and pin 9 for the TSOP package are don’t connect pins.  
The device is erased by executing the erase command  
sequence; the device internally controls the erase opera-  
tions. There are two 8K byte parameter block sections and  
two main memory blocks.  
To allow for simple in-system reprogrammability, the  
AT49BV/LV001(N)(T) does not require high input voltages  
for programming. Three-volt-only commands determine the  
read and programming operation of the device. Reading  
data out of the device is similar to reading from an EPROM;  
it has standard CE, OE, and WE inputs to avoid bus con-  
tention. Reprogramming the AT49BV/LV001(N)(T) is per-  
formed by erasing a block of data and then programming  
on a byte by byte basis. The byte programming time is a  
fast 50 µs. The end of a program cycle can be optionally  
detected by the DATA polling feature. Once the end of a  
byte program cycle has been detected, a new access for a  
read or program can begin. The typical number of program  
and erase cycles is in excess of 10,000 cycles.  
The device has the capability to protect the data in the boot  
block; this feature is enabled by a command sequence.  
The 16K byte boot block section includes a reprogramming  
lock out feature to provide data integrity. The boot sector is  
designed to contain user secure code, and when the fea-  
ture is enabled, the boot sector is protected from being  
reprogrammed.  
In the AT49BV/LV001N(T), once the boot block program-  
ming lockout feature is enabled, the contents of the boot  
block are permanent and cannot be changed. In the  
AT49BV/LV001(T), once the boot block programming lock-  
out feature is enabled, the contents of the boot block can-  
not be changed with input voltage levels of 5.5 volts or less.  
Block Diagram  
AT49BV/LV001(N)  
DATA INPUTS/OUTPUTS  
AT49BV/LV001(N)T  
DATA INPUTS/OUTPUTS  
I/O7 - I/O0  
I/O7 - I/O0  
VCC  
8
8
GND  
INPUT/OUTPUT  
BUFFERS  
INPUT/OUTPUT  
BUFFERS  
OE  
WE  
CONTROL  
LOGIC  
CE  
PROGRAM  
PROGRAM  
RESET  
DATA LATCHES  
DATA LATCHES  
Y DECODER  
X DECODER  
Y-GATING  
Y-GATING  
1FFFF  
1FFFF  
ADDRESS  
INPUTS  
MAIN MEMORY  
BLOCK 2  
BOOT BLOCK  
(16K BYTES)  
1C000  
1BFFF  
(64K BYTES)  
10000  
0FFFF  
PARAMETER  
BLOCK 1  
MAIN MEMORY  
BLOCK 1  
(8K BYTES)  
1A000  
19FFF  
(32K BYTES)  
08000  
07FFF  
PARAMETER  
BLOCK 2  
PARAMETER  
BLOCK 2  
(8K BYTES)  
18000  
17FFF  
(8K BYTES)  
06000  
05FFF  
MAIN MEMORY  
BLOCK 1  
PARAMETER  
BLOCK 1  
(32K BYTES)  
10000  
0FFFF  
(8K BYTES)  
04000  
03FFF  
MAIN MEMORY  
BLOCK 2  
BOOT BLOCK  
(16K BYTES)  
(64K BYTES)  
00000  
00000  
AT49BV/LV001(N)(T)  
2
AT49BV/LV001(N)(T)  
Device Operation  
READ: The AT49BV/LV001(N)(T) is accessed like an  
EPROM. When CE and OE are low and WE is high, the  
data stored at the memory location determined by the  
address pins is asserted on the outputs. The outputs are  
put in the high impedance state whenever CE or OE is  
high. This dual-line control gives designers flexibility in pre-  
venting bus contention.  
CHIP ERASE: If the boot block lockout has been enabled,  
the Chip Erase function will erase Parameter Block 1,  
Parameter Block 2, Main Memory Block 1, and Main Mem-  
ory Block 2 but not the boot block. If the Boot Block Lockout  
has not been enabled, the Chip Erase function will erase  
the entire chip. After the full chip erase the device will  
return back to read mode. Any command during chip erase  
will be ignored.  
COMMAND SEQUENCES: When the device is first pow-  
ered on it will be reset to the read or standby mode  
depending upon the state of the control line inputs. In order  
to perform other device functions, a series of command  
sequences are entered into the device. The command  
sequences are shown in the Command Definitions table.  
The command sequences are written by applying a low  
pulse on the WE or CE input with CE or WE low (respec-  
tively) and OE high. The address is latched on the falling  
edge of CE or WE, whichever occurs last. The data is  
latched by the first rising edge of CE or WE. Standard  
microprocessor write timings are used. The address loca-  
tions used in the command sequences are not affected by  
entering the command sequences.  
SECTOR ERASE: As an alternative to a full chip erase, the  
device is organized into sectors that can be individually  
erased. There are two 8K-byte parameter block sections  
and two main memory blocks. The 8K-byte parameter  
block sections can be independently erased and repro-  
grammed. The two main memory sections are designed to  
be used as alternative memory sectors. That is, whenever  
one of the blocks has been erased and reprogrammed, the  
other block should be erased and reprogrammed before  
the first block is again erased. The Sector Erase command  
is a six bus cycle operation. The sector address is latched  
on the falling WE edge of the sixth cycle while the 30H data  
input command is latched at the rising edge of WE. The  
sector erase starts after the rising edge of WE of the sixth  
cycle. The erase operation is internally controlled; it will  
automatically time to completion.  
RESET: A RESET input pin is provided to ease some sys-  
tem applications. When RESET is at a logic high level, the  
device is in its standard operating mode. A low level on the  
RESET input halts the present device operation and puts  
the outputs of the device in a high impedance state. If the  
RESET pin makes a high to low transition during a program  
or erase operation, the operation may not be successfully  
completed and the operation will have to be repeated after  
a high level is applied to the RESET pin. When a high level  
is reasserted on the RESET pin, the device returns to the  
read or standby mode, depending upon the state of the  
control inputs. By applying a 12V ± 0.5V input signal to the  
RESET pin, the boot block array can be reprogrammed  
even if the boot block lockout feature has been enabled  
(see Boot Block Programming Lockout Override section).  
The RESET feature is not available on the  
AT49BV/LV001N(T).  
BYTE PROGRAMMING: Once the memory array is  
erased, the device is programmed (to a logical “0”) on a  
byte-by-byte basis. Please note that a data “0” cannot be  
programmed back to a “1”; only erase operations can con-  
vert “0”s to “1”s. Programming is accomplished via the  
internal device command register and is a 4 bus cycle  
operation (please refer to the Command Definitions table).  
The device will automatically generate the required internal  
program pulses.  
The program cycle has addresses latched on the falling  
edge of WE or CE, whichever occurs last, and the data  
latched on the rising edge of WE or CE, whichever occurs  
first. Programming is completed after the specified tBP cycle  
time. The DATA polling feature may also be used to indi-  
cate the end of a program cycle.  
ERASURE: Before a byte can be reprogrammed, the main  
memory block or parameter block which contains the byte  
must be erased. The erased state of the memory bits is a  
logical “1”. The entire device can be erased at one time by  
using a 6 byte software code. The software chip erase  
code consists of 6 byte load commands to specific address  
locations with a specific data pattern (please refer to the  
Chip Erase Cycle Waveforms).  
BOOT BLOCK PROGRAMMING LOCKOUT: The device  
has one designated block that has a programming lockout  
feature. This feature prevents programming of data in the  
designated block once the feature has been enabled. The  
size of the block is 16K bytes. This block, referred to as the  
boot block, can contain secure code that is used to bring up  
the system. Enabling the lockout feature will allow the boot  
code to stay in the device while data in the rest of the  
device is updated. This feature does not have to be acti-  
vated; the boot block’s usage as a write protected region is  
optional to the user. The address range of the boot block is  
00000 to 03FFF for the AT49BV/LV001(N) while the  
After the software chip erase has been initiated, the device  
will internally time the erase operation so that no external  
clocks are required. The maximum time needed to erase  
the whole chip is tEC. If the boot block lockout feature has  
been enabled, the data in the boot sector will not be  
erased.  
3
address range of the boot block is 1C000 to 1FFFF for the  
AT49BV/LV001(N)T.  
may be accessed by hardware or software operation. The  
hardware operation mode can be used by an external pro-  
grammer to identify the correct programming algorithm for  
the Atmel product.  
Once the feature is enabled, the data in the boot block can  
no longer be erased or programmed with input voltage level  
of 5.5V or less. Data in the main memory block can still be  
changed through the regular programming method. To acti-  
vate the lockout feature, a series of six program commands  
to specific addresses with specific data must be performed.  
Please refer to the Command Definitions table.  
For details, see Operating Modes (for hardware operation)  
or Software Product Identification. The manufacturer and  
device code is the same for both modes.  
DATA POLLING: The AT49BV/LV001(N)(T) features  
DATA polling to indicate the end of a program cycle. During  
a program cycle an attempted read of the last byte loaded  
will result in the complement of the loaded data on I/O7.  
Once the program cycle has been completed, true data is  
valid on all outputs and the next cycle may begin. DATA  
polling may begin at any time during the program cycle.  
BOOT BLOCK LOCKOUT DETECTION: A software  
method is available to determine if programming of the boot  
block section is locked out. When the device is in the soft-  
ware product identification mode (see Software Product  
Identification Entry and Exit sections) a read from address  
location 00002H will show if programming the boot block is  
locked out for the AT49BV/LV001(N) and a read from  
address 1C002H will show if programming the boot block is  
locked out for the AT49BV/LV001(N)T. If the data on I/O0  
is low, the boot block can be programmed; if the data on  
I/O0 is high, the program lockout feature has been acti-  
vated and the block cannot be programmed. The software  
product identification code should be used to return to stan-  
dard operation.  
TOGGLE BIT: In addition to DATA polling the  
AT49BV/LV001(N)(T) provides another method for deter-  
mining the end of a program or erase cycle. During a pro-  
gram or erase operation, successive attempts to read data  
from the device will result in I/O6 toggling between one and  
zero. Once the program cycle has completed, I/O6 will stop  
toggling and valid data will be read. Examining the toggle  
bit may begin at any time during a program cycle.  
HARDWARE DATA PROTECTION: Hardware features  
protect against inadvertent programs to the  
AT49BV/LV001(N)(T) in the following ways: (a) VCC sense:  
if VCC is below 1.8V (typical), the program function is inhib-  
ited. (b) Program inhibit: holding any one of OE low, CE  
high or WE high inhibits program cycles. (c) Noise filter:  
pulses of less than 15 ns (typical) on the WE or CE inputs  
will not initiate a program cycle.  
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:  
The user can override the boot block programming lockout  
by taking the RESET pin to 12 volts during the entire chip  
erase, sector erase or byte programming operation. When  
the RESET pin is brought back to TTL levels the boot block  
programming lockout feature is again active. This feature is  
not available on the AT49BV/LV001N(T).  
PRODUCT IDENTIFICATION: The product identification  
mode identifies the device and manufacturer as Atmel. It  
AT49BV/LV001(N)(T)  
4
AT49BV/LV001(N)(T)  
Command Definition (in Hex)(1)  
1st Bus  
Cycle  
2nd Bus  
Cycle  
3rd Bus  
Cycle  
4th Bus  
Cycle  
5th Bus  
Cycle  
6th Bus  
Cycle  
Command  
Sequence  
Bus  
Cycles  
Addr  
Addr  
5555  
5555  
5555  
5555  
5555  
5555  
XXXX  
Data  
DOUT  
AA  
Addr Data Addr Data Addr Data Addr Data Addr Data  
Read  
1
6
6
4
6
3
3
1
Chip Erase  
2AAA  
2AAA  
2AAA  
2AAA  
2AAA  
2AAA  
55  
55  
55  
55  
55  
55  
5555  
5555  
5555  
5555  
5555  
5555  
80  
80  
A0  
80  
90  
F0  
5555  
5555  
Addr  
5555  
AA  
AA  
DIN  
AA  
2AAA  
2AAA  
55  
55  
5555  
SA(4)  
10  
30  
Sector Erase  
AA  
Byte Program  
Boot Block Lockout(2)  
Product ID Entry  
Product ID Exit(3)  
Product ID Exit(3)  
AA  
AA  
2AAA  
55  
5555  
40  
AA  
AA  
F0  
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)  
2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV001(N) and  
1C000H to 1FFFFH for the AT49BV/LV001(N)T.  
3. Either one of the Product ID Exit commands can be used.  
4. SA = sector addresses:  
For the AT49BV/LV001(N):  
SA = 10000 to 1FFFF for BOOT BLOCK  
Nothing will happen and the device goes back to the read mode in 100 ns  
SA = 04000 to 05FFF for PARAMETER BLOCK 1  
SA = 06000 to 07FFF for PARAMETER BLOCK 2  
SA = 08000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 1  
This command will erase - PB1, PB2 and MMB1  
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2  
For the AT49BV/LV001(N)T:  
SA = 1C000 to 1FFFF for BOOT BLOCK  
Nothing will happen and the device goes back to the read mode in 100 ns  
SA = 1A000 to 1BFFF for PARAMETER BLOCK 1  
SA = 18000 to 19FFF for PARAMETER BLOCK 2  
SA = 10000 to 17FFF for MAIN MEMORY ARRAY BLOCK 1  
This command will erase - PB1, PB2 and MMB1  
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 2  
Absolute Maximum Ratings*  
*NOTICE:  
Stresses beyond those listed under “Absolute Maxi-  
mum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional  
operation of the device at these or any other condi-  
tions beyond those indicated in the operational sec-  
tions of this specification is not implied. Exposure to  
absolute maximum rating conditions for extended  
periods may affect device reliability.  
Temperature Under Bias................................ -55°C to +125°C  
Storage Temperature..................................... -65°C to +150°C  
All Input Voltages  
(including NC Pins)  
with Respect to Ground...................................-0.6V to +6.25V  
All Output Voltages  
with Respect to Ground.............................-0.6V to VCC + 0.6V  
Voltage on OE  
with Respect to Ground...................................-0.6V to +13.5V  
5
DC and AC Operating Range  
AT49LV001(N)(T)-70  
AT49BV/LV001(N)(T)-90  
0°C - 70°C  
AT49BV/LV001(N)(T)-12  
0°C - 70°C  
Com.  
Ind.  
0°C - 70°C  
-40°C - 85°C  
3.0V - 3.6V  
Operating  
Temperature (Case)  
-40°C - 85°C  
-40°C - 85°C  
VCC Power Supply  
2.7V - 3.6V/3.0V - 3.6V  
2.7V - 3.6V/3.0V - 3.6V  
Operating Modes  
Ai  
Ai  
Ai  
X
Mode  
CE  
VIL  
VIL  
VIH  
X
OE  
VIL  
VIH  
X(1)  
X
WE  
RESET(6)  
I/O  
Read  
VIH  
VIL  
X
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIL  
DOUT  
DIN  
Program/Erase(2)  
Standby/Write Inhibit  
Program Inhibit  
Program Inhibit  
Output Disable  
Reset  
High Z  
VIH  
X
X
VIL  
VIH  
X
X
X
High Z  
High Z  
X
X
X
Product Identification  
A1 - A16 = VIL, A9 = VH,(3)  
A0 = VIL  
Manufacturer Code(4)  
Device Code(4)  
Hardware  
A1 - A16 = VIL, A9 = VH,(3)  
A0 = VIH  
VIL  
VIL  
VIH  
A0 = VIL, A1 - A16=VIL  
A0 = VIH, A1 - A16=VIL  
Manufacturer Code(4)  
Device Code(4)  
Software(5)  
Notes: 1. X can be VIL or VIH.  
2. Refer to AC Programming Waveforms.  
3. VH = 12.0V ± 0.5V.  
4. Manufacturer Code: 1FH, Device Code: 05H - AT49BV/LV001(N), 04H - AT49BV/LV001(N)T.  
5. See details under Software Product Identification Entry/Exit.  
6. This pin is not available on the AT49BV/LV001N(T).  
DC Characteristics  
Symbol  
Parameter  
Condition  
Min  
Max  
10  
10  
50  
3
Units  
µA  
µA  
µA  
mA  
mA  
V
ILI  
Input Load Current  
Output Leakage Current  
VCC Standby Current CMOS  
VCC Standby Current TTL  
VCC Active Current  
Input Low Voltage  
VIN = 0V to VCC  
ILO  
VI/O = 0V to VCC  
CE = VCC - 0.3V to VCC  
CE = 2.0V to VCC  
f = 5 MHz; IOUT = 0 mA  
ISB1  
ISB2  
(1)  
ICC  
25  
0.6  
VIL  
VIH  
VOL  
VOH  
Input High Voltage  
2.0  
2.4  
V
Output Low Voltage  
IOL = 2.1 mA  
.45  
V
Output High Voltage  
IOH = -400 µA  
V
Note:  
1. In the erase mode, ICC is 50 mA.  
AT49BV/LV001(N)(T)  
6
AT49BV/LV001(N)(T)  
AC Read Characteristics  
AT49LV001(N)(T)-70 AT49BV/LV001(N)(T)-90 AT49BV/LV001(N)(T)-12  
Symbol Parameter  
Units  
ns  
Min  
Max  
70  
Min  
Max  
90  
Min  
Max  
120  
120  
50  
tACC  
Address to Output Delay  
CE to Output Delay  
(1)  
tCE  
tOE  
tDF  
70  
90  
ns  
(2)  
OE to Output Delay  
0
0
35  
0
0
40  
0
0
ns  
(3)(4)  
CE or OE to Output Float  
25  
25  
30  
ns  
Output Hold from OE, CE or  
Address, whichever occurred first  
tOH  
0
0
0
ns  
AC Read Waveforms (1)(2)(3)(4)  
ADDRESS  
ADDRESS VALID  
CE  
tCE  
tOE  
OE  
tDF  
tOH  
tACC  
HIGH Z  
OUTPUT  
VALID  
OUTPUT  
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC  
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change  
without impact on tACC  
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).  
4. This parameter is characterized and is not 100% tested.  
Input Test Waveform and Measurement Level  
Output Load Test  
3.0V  
2.4V  
AC  
AC  
1.8K  
DRIVING  
LEVELS  
MEASUREMENT  
LEVEL  
1.5V  
OUTPUT  
PIN  
0.4V  
30 pF  
1.3K  
tR, tF < 5 ns  
Pin Capacitance  
(f = 1 MHz, T = 25°C)(1)  
Typ  
Max  
6
Units  
Conditions  
CIN  
4
8
pF  
pF  
VIN = 0V  
COUT  
12  
VOUT = 0V  
Note:  
1. This parameter is characterized and is not 100% tested.  
7
AC Byte Load Characteristics  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
t
AS, tOES  
Address, OE Set-up Time  
Address Hold Time  
tAH  
tCS  
tCH  
tWP  
tDS  
70  
0
ns  
Chip Select Set-up Time  
Chip Select Hold Time  
Write Pulse Width (WE or CE)  
Data Set-up Time  
ns  
0
ns  
90  
70  
0
ns  
ns  
ns  
ns  
t
DH, tOEH  
Data, OE Hold Time  
Write Pulse Width High  
90  
tWPH  
AC Byte Load Waveforms  
WE Controlled  
OE  
tOES  
tOEH  
ADDRESS  
CE  
tAS  
tAH  
tCH  
tCS  
WE  
tWPH  
tWP  
tDH  
tDS  
DATA IN  
CE Controlled  
OE  
tOES  
tOEH  
ADDRESS  
WE  
tAS  
tAH  
tCH  
tCS  
CE  
tWPH  
tWP  
tDH  
tDS  
DATA IN  
AT49BV/LV001(N)(T)  
8
AT49BV/LV001(N)(T)  
Program Cycle Characteristics  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
µs  
tBP  
Byte Programming Time  
Address Set-up Time  
Address Hold Time  
Data Set-up Time  
Data Hold Time  
30  
50  
tAS  
0
ns  
tAH  
70  
70  
0
ns  
tDS  
ns  
tDH  
ns  
tWP  
Write Pulse Width  
Write Pulse Width High  
Erase Cycle Time  
90  
90  
ns  
tWPH  
tEC  
ns  
10  
seconds  
Program Cycle Waveforms  
A0-A16  
Sector or Chip Erase Cycle Waveforms  
(1)  
OE  
CE  
t
t
WP  
WPH  
WE  
A0-A16  
DATA  
t
t
t
AS  
AH  
DH  
5555  
5555  
5555  
Note 2  
2AAA  
2AAA  
t
t
EC  
DS  
55  
BYTE 1  
80  
BYTE 2  
55  
BYTE 4  
Note 3  
BYTE 5  
AA  
BYTE 0  
AA  
BYTE 3  
Notes: 1. OE must be high only when WE and CE are both low.  
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.  
(See note 4 under command definitions.)  
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.  
9
Data Polling Characteristics(1)  
Symbol  
Parameter  
Min  
10  
Typ  
Max  
Units  
ns  
tDH  
Data Hold Time  
tOEH  
tOE  
OE Hold Time  
10  
ns  
OE to Output Delay(2)  
Write Recovery Time  
ns  
tWR  
0
ns  
Notes: 1. These parameters are characterized and not 100% tested.  
2. See tOE spec in AC Read Characteristics.  
DATA Polling Waveforms  
WE  
CE  
t
OEH  
OE  
t
DH  
t
WR  
t
OE  
HIGHZ  
An  
I/O7  
A0-A16  
An  
An  
An  
An  
Toggle Bit Characteristics(1)  
Symbol  
Parameter  
Min  
10  
Typ  
Max  
Units  
ns  
tDH  
Data Hold Time  
OE Hold Time  
tOEH  
tOE  
tOEHP  
tWR  
10  
ns  
OE to Output Delay(2)  
ns  
OE High Pulse  
150  
0
ns  
Write Recovery Time  
ns  
Notes: 1. These parameters are characterized and not 100% tested.  
2. See tOE spec in AC Read Characteristics.  
Toggle Bit Waveforms(1)(2)(3)  
WE  
CE  
tOEH  
tOEHP  
OE  
tOE  
tDH  
HIGH Z  
I/O6  
tWR  
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.  
The tOEHP specification must be met by the toggling input(s).  
2. Beginning and ending state of I/O6 will vary.  
3. Any address location may be used but the address should not vary.  
AT49BV/LV001(N)(T)  
10  
AT49BV/LV001(N)(T)  
Software Product  
Boot Block Lockout  
Identification Entry(1)  
Feature Enable Algorithm(1)  
LOAD DATA AA  
TO  
LOAD DATA AA  
ADDRESS 5555  
TO  
ADDRESS 5555  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
LOAD DATA 80  
TO  
ADDRESS 5555  
LOAD DATA 90  
TO  
ADDRESS 5555  
LOAD DATA AA  
TO  
ADDRESS 5555  
ENTER PRODUCT  
IDENTIFICATION  
(2)(3)(5)  
MODE  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
Software Product  
Identification Exit(1)  
LOAD DATA 40  
TO  
ADDRESS 5555  
OR  
LOAD DATA AA  
TO  
LOAD DATA F0  
TO  
ADDRESS 5555  
ANY ADDRESS  
(2)  
PAUSE 1 second  
LOAD DATA 55  
TO  
ADDRESS 2AAA  
EXIT PRODUCT  
IDENTIFICATION  
Notes for boot block lockout feature enable:  
(4)  
MODE  
1. Data Format: I/O7 - I/O0 (Hex);  
Address Format: A14 - A0 (Hex).  
LOAD DATA F0  
TO  
ADDRESS 5555  
2. Boot block lockout feature enabled.  
EXIT PRODUCT  
IDENTIFICATION  
(4)  
MODE  
Notes for software product identification  
1. Data Format: I/O7 - I/O0 (Hex);  
Address Format: A14 - A0 (Hex).  
2. A1 - A16 = VIL.  
Manufacture Code is read for A0 = VIL;  
Device Code is read for A0 = VIH.  
3. The device does not remain in identification mode if  
powered down.  
4. The device returns to standard operation mode.  
5. Manufacturer Code: 1FH  
Device Code: 05H - AT49BV/LV001(N)  
04H - AT49BV/LV001(N)T  
11  
AT49BV001 Ordering Information  
I
CC (mA)  
tACC  
(ns)  
Active  
Standby  
Ordering Code  
Package  
Operation Range  
90  
50  
0.1  
AT49BV001-90JC  
AT49BV001-90PC  
AT49BV001-90TC  
AT49BV001-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
50  
50  
50  
0.3  
0.1  
0.3  
AT49BV001-90JI  
AT49BV001-90PI  
AT49BV001-90TI  
AT49BV001-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49bV001-12JC  
AT49BV001-12PC  
AT49BV001-12TC  
AT49BV001-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49BV001-12JC  
AT49BV001-12PC  
AT49BV001-12TC  
AT49BV001-12VC  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
AT49BV/LV001(N)(T)  
12  
AT49BV/LV001(N)(T)  
AT49LV001 Ordering Information  
I
CC (mA)  
tACC  
(ns)  
Active  
Standby  
Ordering Code  
Package  
Operation Range  
70  
50  
0.1  
AT49LV001-70JC  
AT49LV001-70PC  
AT49LV001-70TC  
AT49LV001-70VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
50  
50  
50  
50  
50  
0.3  
0.1  
0.3  
0.1  
0.3  
AT49LV001-70JI  
AT49LV001-70PI  
AT49LV001-70TI  
AT49LV001-70VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
90  
AT49LV001-90JC  
AT49LV001-90PC  
AT49LV001-90TC  
AT49LV001-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001-90JI  
AT49LV001-90PI  
AT49LV001-90TI  
AT49LV001-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49LV001-12JC  
AT49LV001-12PC  
AT49LV001-12TC  
AT49LV001-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001-12JC  
AT49LV001-12PC  
AT49LV001-12TC  
AT49LV001-12VC  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
13  
AT49BV001N Ordering Information  
I
CC (mA)  
tACC  
(ns)  
Active  
Standby  
Ordering Code  
Package  
Operation Range  
90  
50  
0.1  
AT49BV001N-90JC  
AT49BV001N-90PC  
AT49BV001N-90TC  
AT49BV001N-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
50  
50  
50  
0.3  
0.1  
0.3  
AT49BV001N-90JI  
AT49BV001N-90PI  
AT49BV001N-90TI  
AT49BV001N-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49BV001N-12JC  
AT49BV001N-12PC  
AT49BV001N-12TC  
AT49BV001N-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49BV001N-12JC  
AT49BV001N-12PC  
AT49BV001N-12TC  
AT49BV001N-12VC  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
AT49BV/LV001(N)(T)  
14  
AT49BV/LV001(N)(T)  
AT49LV001N Ordering Information  
I
CC (mA)  
tACC  
(ns)  
Active  
Standby  
Ordering Code  
Package  
Operation Range  
70  
50  
0.1  
AT49LV001N-70JC  
AT49LV001N-70PC  
AT49LV001N-70TC  
AT49LV001N-70VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
50  
50  
50  
50  
50  
0.3  
0.1  
0.3  
0.1  
0.3  
AT49LV001N-70JI  
AT49LV001N-70PI  
AT49LV001N-70TI  
AT49LV001N-70VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
90  
AT49LV001N-90JC  
AT49LV001N-90PC  
AT49LV001N-90TC  
AT49LV001N-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001N-90JI  
AT49LV001N-90PI  
AT49LV001N-90TI  
AT49LV001N-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49LV001N-12JC  
AT49LV001N-12PC  
AT49LV001N-12TC  
AT49LV001N-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001N-12JC  
AT49LV001N-12PC  
AT49LV001N-12TC  
AT49LV001N-12VC  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
15  
AT49BV001T Ordering Information  
I
CC (mA)  
tACC  
(ns)  
Active  
Standby  
Ordering Code  
Package  
Operation Range  
90  
50  
0.1  
AT49BV001T-90JC  
AT49BV001T-90PC  
AT49BV001T-90TC  
AT49BV001T-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
50  
50  
50  
0.3  
0.1  
0.3  
AT49BV001T-90JI  
AT49BV001T-90PI  
AT49BV001T-90TI  
AT49BV001T-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49BV001T-12JC  
AT49BV001T-12PC  
AT49BV001T-12TC  
AT49BV001T-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49BV001T-12JC  
AT49BV001T-12PC  
AT49BV001T-12TC  
AT49BV001T-12VC  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
AT49BV/LV001(N)(T)  
16  
AT49BV/LV001(N)(T)  
AT49LV001T Ordering Information  
I
CC (mA)  
tACC  
(ns)  
Active  
Standby  
Ordering Code  
Package  
Operation Range  
70  
50  
0.1  
AT49LV001T-70JC  
AT49LV001T-70PC  
AT49LV001T-70TC  
AT49LV001T-70VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
50  
50  
50  
50  
50  
0.3  
0.1  
0.3  
0.1  
0.3  
AT49LV001T-70JI  
AT49LV001T-70PI  
AT49LV001T-70TI  
AT49LV001T-70VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
90  
AT49LV001T-90JC  
AT49LV001T-90PC  
AT49LV001T-90TC  
AT49LV001T-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001T-90JI  
AT49LV001T-90PI  
AT49LV001T-90TI  
AT49LV001T-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49LV001T-12JC  
AT49LV001T-12PC  
AT49LV001T-12TC  
AT49LV001T-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001T-12JC  
AT49LV001T-12PC  
AT49LV001T-12TC  
AT49LV001T-12VC  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
17  
AT49BV001NT Ordering Information  
tACC  
(ns)  
ICC (mA)  
Ordering Code  
Package  
Operation Range  
90  
50  
50  
50  
50  
0.1  
0.3  
0.1  
0.3  
AT49BV001NT-90JC  
AT49BV001NT-90PC  
AT49BV001NT-90TC  
AT49BV001NT-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49BV001NT-90JI  
AT49BV001NT-90PI  
AT49BV001NT-90TI  
AT49BV001NT-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49BV001NT-12JC  
AT49BV001NT-12PC  
AT49BV001NT-12TC  
AT49BV001NT-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49BV001NT-12JI  
AT49BV001NT-12PI  
AT49BV001NT-12TI  
AT49BV001NT-12VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
AT49BV/LV001(N)(T)  
18  
AT49BV/LV001(N)(T)  
AT49LV001NT Ordering Information  
tACC  
(ns)  
ICC (mA)  
Ordering Code  
Package  
Operation Range  
70  
50  
50  
50  
50  
50  
50  
0.1  
0.3  
0.1  
0.3  
0.1  
0.3  
AT49LV001NT-70JC  
AT49LV001NT-70PC  
AT49LV001NT-70TC  
AT49LV001NT-70VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001NT-70JI  
AT49LV001NT-70PI  
AT49LV001NT-70TI  
AT49LV001NT-70VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
90  
AT49LV001NT-90JC  
AT49LV001NT-90PC  
AT49LV001NT-90TC  
AT49LV001NT-90VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001NT-90JI  
AT49LV001NT-90PI  
AT49LV001NT-90TI  
AT49LV001NT-90VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
120  
AT49LV001NT-12JC  
AT49LV001NT-12PC  
AT49LV001NT-12TC  
AT49LV001NT-12VC  
32J  
Commercial  
32P6  
32T  
32V  
(0° to 70°C)  
AT49LV001NT-12JI  
AT49LV001NT-12PI  
AT49LV001NT-12TI  
AT49LV001NT-12VI  
32J  
Industrial  
32P6  
32T  
32V  
(-40° to 85°C)  
Package Type  
32J  
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)  
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)  
32-Lead, Plastic Thin Small Outline Package (TSOP) (8 x 20mm)  
32-Lead, Plastic Thin Small Outline Package (VSOP) (8 x 14mm)  
32P6  
32T  
32V  
19  
Packaging Information  
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)  
32P6, 32-Lead, 0.600" Wide,  
Dimensions in Inches and (Millimeters)  
JEDEC STANDARD MS-016 AE  
Plastic Dual In-line Package (PDIP)  
Dimensions in Inches and (Millimeters)  
1.67(42.4)  
1.64(41.7)  
.025(.635) X 30° - 45°  
.045(1.14) X 45° PIN NO. 1  
.012(.305)  
PIN  
1
IDENTIFY  
.008(.203)  
.530(13.5)  
.553(14.0)  
.490(12.4)  
.566(14.4)  
.530(13.5)  
.547(13.9)  
.032(.813)  
.026(.660)  
.021(.533)  
.013(.330)  
.595(15.1)  
.585(14.9)  
.090(2.29)  
MAX  
.030(.762)  
.015(3.81)  
.095(2.41)  
.060(1.52)  
.140(3.56)  
.120(3.05)  
.050(1.27) TYP  
1.500(38.10) REF  
.300(7.62) REF  
.430(10.9)  
.390(9.90)  
.220(5.59)  
MAX  
.005(.127)  
MIN  
AT CONTACT  
POINTS  
SEATING  
PLANE  
.065(1.65)  
.015(.381)  
.022(.559)  
.014(.356)  
.161(4.09)  
.125(3.18)  
.065(1.65)  
.041(1.04)  
.022(.559) X 45° MAX (3X)  
.110(2.79)  
.090(2.29)  
.630(16.0)  
.590(15.0)  
.453(11.5)  
.447(11.4)  
0
15  
.495(12.6)  
.485(12.3)  
REF  
.012(.305)  
.008(.203)  
.690(17.5)  
.610(15.5)  
32T, 32-Lead, Plastic Thin Small Outline  
Package (TSOP)  
32V, 32-Lead, Plastic Thin Small Outline  
Package (VSOP)  
Dimensions in Millimeters and (Inches)*  
Dimensions in Inches and (Millimeters)  
JEDEC OUTLINE MO-142 BA  
INDEX  
MARK  
INDEX  
MARK  
12.5(.492)  
12.3(.484)  
14.2(.559)  
13.8(.543)  
18.5(.728)  
18.3(.720)  
20.2(.795)  
19.8(.780)  
0.50(.020)  
BSC  
0.50(.020)  
BSC  
0.25(.010)  
0.15(.006)  
0.25(.010)  
0.15(.006)  
7.50(.295)  
REF  
7.50(.295)  
REF  
8.10(.319)  
7.90(.311)  
8.20(.323)  
7.80(.307)  
1.20(.047) MAX  
1.20(.047) MAX  
0.15(.006)  
0.05(.002)  
0.15(.006)  
0.05(.002)  
0
0
0.20(.008)  
0.10(.004)  
REF  
5
0.20(.008)  
0.10(.004)  
REF  
5
0.70(.028)  
0.50(.020)  
0.70(.028)  
0.50(.020)  
*Controlling dimension: millimeters  
AT49BV/LV001(N)(T  
20  

相关型号:

AT49BV001N-12JI

x8 Flash EEPROM
ETC

AT49BV001N-12JJ

Flash, 128KX8, 120ns, PQCC32, PLASTIC, MS-016AE, LCC-32
ATMEL

AT49BV001N-12JL

Flash, 128KX8, 120ns, PQCC32, PLASTIC, MS-016AE, LCC-32
ATMEL

AT49BV001N-12PC

1-Megabit 128K x 8 Single 2.7-Volt Battery-Voltage Flash Memory
ATMEL

AT49BV001N-12PI

x8 Flash EEPROM
ETC

AT49BV001N-12PJ

Flash, 128KX8, 120ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32
ATMEL

AT49BV001N-12PL

Flash, 128KX8, 120ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32
ATMEL

AT49BV001N-12TC

1-Megabit 128K x 8 Single 2.7-Volt Battery-Voltage Flash Memory
ATMEL

AT49BV001N-12TI

x8 Flash EEPROM
ETC

AT49BV001N-12TJ

Flash, 128KX8, 120ns, PDSO32, 8 X 20 MM, PLASTIC, MO-142BD, TSOP1-32
ATMEL

AT49BV001N-12TL

Flash, 128KX8, 120ns, PDSO32, 8 X 20 MM, PLASTIC, MO-142BD, TSOP1-32
ATMEL

AT49BV001N-12VC

1-Megabit 128K x 8 Single 2.7-Volt Battery-Voltage Flash Memory
ATMEL