AT49BV002AN-70TU [ATMEL]
Flash, 256KX8, 70ns, PDSO32, 8 X 20 MM, GREEN, PLASTIC, MO-142BD, TSOP1-32;
| 型号： | AT49BV002AN-70TU |
| 厂家： | 
ATMEL |
| 描述： | Flash, 256KX8, 70ns, PDSO32, 8 X 20 MM, GREEN, PLASTIC, MO-142BD, TSOP1-32 光电二极管 |
| 文件： | 总19页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Supply for Read and Write: 2.7 to 3.6V
• Fast Read Access Time – 70 ns
• Internal Program Control and Timer
• Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)
• Fast Erase Cycle Time – 4 Seconds
• Byte-by-Byte Programming – 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling for End of Program Detection
• Low Power Dissipation
2-megabit
(256K x 8)
– 15 mA Active Current
Single 2.7-volt
Battery-Voltage
Flash Memory
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Green (Pb/Halide-free) Packaging Option
1. Description
The AT49BV002A(N)(T) is a 2.7-volt-only in-system reprogrammable Flash Memory.
Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
70 ns with power dissipation of just 54 mW over the industrial temperature range.
AT49BV002A
AT49BV002AN
AT49BV002AT
AT49BV002ANT
When the device is deselected, the CMOS standby current is less than 50 µA. For the
AT49BV002AN(T) pin 1 for PLCC package and pin 9 for the TSOP package are no
connect pins. To allow for simple in-system reprogrammability, the
AT49BV002A(N)(T) does not require high input voltages for programming. Five-volt-
only commands determine the read and programming operation of the device. Read-
ing data out of the device is similar to reading from an EPROM; it has standard CE,
OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV002A(N)(T)
is performed by erasing a block of data and then programming on a byte by byte
basis. The byte programming time is a fast 30 µs. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the end of a byte program cycle
has been detected, a new access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000 cycles.
Not
Recommended
for New Design
The device is erased by executing the erase command sequence; the device inter-
nally controls the erase operations. There are two 8K byte parameter block sections,
four main memory blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is
enabled by a command sequence. The 16K-byte boot block section includes a repro-
gramming lock out feature to provide data integrity. The boot sector is designed to
contain user secure code, and when the feature is enabled, the boot sector is pro-
tected from being reprogrammed.
In the AT49BV002AN(T), once the boot block programming lockout feature is
enabled, the contents of the boot block are permanent and cannot be changed. In the
AT49BV002A(T), once the boot block programming lockout feature is enabled, the
contents of the boot block cannot be changed with input voltage levels of 5.5 volts or
less.
3353G–FLASH–8/05
2. Pin Configurations
Pin Name
Function
A0 - A17
CE
Addresses
Chip Enable
Output Enable
Write Enable
RESET
OE
WE
RESET
I/O0 - I/O7
Data Inputs/Outputs
2.1
32-lead PLCC Top View
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
A2 10
A1 11
A0 12
I/O0 13
2.2
32-lead VSOP (8 x 14 mm) or 32-lead TSOP, Type 1 (8 x 20 mm) Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
A17
WE
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
6
7
VCC
*RESET
A16
A15
A12
A7
8
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
Note:
*This pin is a NC on the AT49BV002AN(T).
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AT49BV002A(N)(T)
3353G–FLASH–8/05
AT49BV002A(N)(T)
3. Block Diagram
AT49BV002A(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
AT49BV002A(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
8
8
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
OE
WE
CONTROL
LOGIC
CE
PROGRAM
PROGRAM
RESET
DATA LATCHES
DATA LATCHES
Y DECODER
X DECODER
Y-GATING
Y-GATING
3FFFF
ADDRESS
INPUTS
3FFFF
MAIN MEMORY
BLOCK 4
BOOT BLOCK
(16K BYTES)
3C000
(64K BYTES)
30000
2FFFF
3BFFF
PARAMETER
BLOCK 1
MAIN MEMORY
BLOCK 3
(8K BYTES)
3A000
39FFF
(64K BYTES)
20000
1FFFF
PARAMETER
BLOCK 2
MAIN MEMORY
BLOCK 2
(8K BYTES)
38000
37FFF
(64K BYTES)
10000
0FFFF
MAIN MEMORY
BLOCK 1
MAIN MEMORY
BLOCK 1
(32K BYTES)
30000
2FFFF
(32K BYTES)
08000
07FFF
MAIN MEMORY
BLOCK 2
PARAMETER
BLOCK 2
(64K BYTES)
20000
1FFFF
(8K BYTES)
06000
05FFF
MAIN MEMORY
BLOCK 3
PARAMETER
BLOCK 1
(64K BYTES)
10000
0FFFF
(8K BYTES)
04000
03FFF
MAIN MEMORY
BLOCK 4
BOOT BLOCK
(16K BYTES)
(64K BYTES)
00000
00000
4. Device Operation
4.1
Read
The AT49BV002A(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins is asserted on the out-
puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
4.2
Command Sequences
When the device is first powered on it will be reset to the read or standby mode depending upon
the state of the control line inputs. In order to perform other device functions, a series of com-
mand sequences are entered into the device. The command sequences are shown in the
“Command Definition Table”. The command sequences are written by applying a low pulse on
the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE (except for the sixth cycle of the Sector Erase command), whichever
occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor
write timings are used. The address locations used in the command sequences are not affected
by entering the command sequences.
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3353G–FLASH–8/05
4.3
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program or erase operation, the operation
may not be successfully completed and the operation will have to be repeated after a high level
is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device
returns to the read or standby mode, depending upon the state of the control inputs. By applying
a 12V 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if
the boot block lockout feature has been enabled (see “Boot Block Programming Lockout” on
page 5). The RESET feature is not available on the AT49BV002AN(T).
4.4
Erasure
Before a byte can be reprogrammed, the main memory blocks or parameter blocks which con-
tains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire
device can be erased at one time by using a 6-byte software code. The software chip erase
code consists of 6-byte load commands to specific address locations with a specific data pattern
(please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase opera-
tion so that no external clocks are required. The maximum time needed to erase the whole chip
is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be
erased.
4.4.1
4.4.2
Chip Erase
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block
1, Parameter Block 2, Main Memory Block 1 - 4, but not the boot block. If the Boot Block Lockout
has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase
the device will return back to read mode. Any command during chip erase will be ignored.
Sector Erase
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections and four main memory blocks. The 8K-
byte parameter block sections and the four main memory blocks can be independently erased
and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector
address is latched on the rising WE edge of the sixth cycle and the 30H data input command is
also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the
sixth cycle. The erase operation is internally controlled; it will automatically time to completion.
4.5
Byte Programming
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the “Command Definition Table” on page 7). The
device will automatically generate the required internal program pulses.
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AT49BV002A(N)(T)
3353G–FLASH–8/05
AT49BV002A(N)(T)
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs
last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming
is completed after the specified tBP cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
4.6
Boot Block Programming Lockout
The device has one designated block that has a programming lockout feature. This feature pre-
vents programming of data in the designated block once the feature has been enabled. The size
of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be activated;
the boot block’s usage as a write protected region is optional to the user. The address range of
the boot block is 00000 to 03FFF for the AT49BV002A(N) while the address range of the boot
block is 3C000 to 3FFFF for the AT49BV002A(N)T.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed
with input voltage of 5.5V or less. Data in the main memory block can still be changed through
the regular programming method. To activate the lockout feature, a series of six program com-
mands to specific addresses with specific data must be performed. Please refer to the
“Command Definition Table” on page 7.
4.6.1
Boot Block Lockout Detection
A software method is available to determine if programming of the boot block section is locked
out. When the device is in the software product identification mode (see “Software Product Iden-
tification Entry and Exit” sections) a read from address location 00002H will show if
programming the boot block is locked out for the AT49BV002A(N), and a read from address
location 3C002H will show if programming the bootblock is locked out for AT49BV002A(N)T. If
the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the pro-
gram lockout feature has been activated and the block cannot be programmed. The software
product identification code should be used to return to standard operation.
4.6.2
Boot Block Programming Lockout Override
The user can override the boot block programming lockout by taking the RESET pin to 12 volts
during the entire chip erase, sector erase or byte programming operation. When the RESET pin
is brought back to TTL levels the boot block programming lockout feature is again active. This
feature is not available on the AT49BV002AN(T).
4.7
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see “Operating Modes” on page 8 (for hardware operation) or Software Product
Identification. The manufacturer and device code is the same for both modes.
5
3353G–FLASH–8/05
4.8
4.9
DATA Polling
Toggle Bit
The AT49BV002A(N)(T) features DATA polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been completed, true data is valid on all out-
puts and the next cycle may begin. DATA polling may begin at any time during the program
cycle.
In addition to DATA polling the AT49BV002A(N)(T) provides another method for determining the
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
4.10 Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV002A(N)(T) in the
following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited.
(b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles.
(c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a
program cycle.
6
AT49BV002A(N)(T)
3353G–FLASH–8/05
AT49BV002A(N)(T)
5. Command Definition Table
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Bus
Command Sequence
Read
Cycles
Addr
Addr
555
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
1
6
6
4
6
3
3
1
Chip Erase
AAA(2)
AAA
AAA
AAA
AAA
AAA
55
55
55
55
55
55
555
555
555
555
555
555
80
80
A0
80
90
F0
555
555
AA
AA
DIN
AA
AAA
AAA
55
55
555
10
30
Sector Erase
555
AA
SA(5)
Byte Program
555
AA
Addr
555
Boot Block Lockout(3)
Product ID Entry
Product ID Exit(4)
Product ID Exit(4)
555
AA
AAA
55
555
40
555
AA
555
AA
XXXX
F0
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows:
A11 - A0 (Hex); A11 - A17 (don’t care).
2. Since A11 is don’t care, AAA can be replaced with 2AA.
3. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV002A(N) and 3C000H to 3FFFFH for the
AT49BV002A(N)T
4. Either one of the Product ID Exit commands can be used.
5. SA = sector addresses:
For the AT49BV002A(N):
SA = 00000 to 03FFF for BOOT BLOCK
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2
SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 3
SA = 30000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 4
For the AT49BV002A(N)T:
SA = 3C000 to 3FFFF for BOOT BLOCK
SA = 3A000 to 3BFFF for PARAMETER BLOCK 1
SA = 38000 to 39FFF for PARAMETER BLOCK 2
SA = 30000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1
SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 2
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 3
SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 4
6. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Temperature Under Bias ............................... -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
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3353G–FLASH–8/05
7. DC and AC Operating Range
AT49BV002A(N)(T)-70
-40°C - 85°C
Operating Temperature (Case)
VCC Power Supply
Ind.
2.7V - 3.6V
8. Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
RESET(6)
VIH
Ai
Ai
Ai
X
I/O
DOUT
DIN
Read
Program/Erase(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Reset
VIH
VIH
High Z
VIH
X
VIH
X
VIL
VIH
X
VIH
X
X
VIH
High Z
High Z
X
X
VIL
X
Product Identification
A1 - A17 = VIL, A9 = VH,(3), A0 = VIL
A1 - A17 = VIL, A9 = VH,(3), A0 = VIH
A0 = VIL, A1 - A17=VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A17=VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1FH, Device Code: 07H - AT49BV002A(N), 08H - AT49BV002A(N)T
5. See details under “Software Product Identification Entry/Exit”.
6. This pin is not available on the AT49BV002AN(T).
9. DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
10
10
50
3
ILO
ISB1
VCC Standby Current CMOS CE = VCC - 0.3V to VCC
ISB2
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
CE = 2.0V to VCC
(1)
ICC
f = 5 MHz; IOUT = 0 mA
15
0.6
VIL
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
V
IOL = 2.1 mA
IOH = -400 µA
0.45
V
V
Note:
1. In the erase mode, ICC is 50 mA.
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AT49BV002A(N)(T)
10. AC Read Characteristics
AT49BV002A(N)(T)-70
Symbol
Parameter
Min
Max
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
70
70
35
25
(1)
tCE
ns
(2)
tOE
0
0
ns
(3)(4)
tDF
ns
Output Hold from OE, CE or
Address, whichever occurred first
tOH
0
ns
11. AC Read Waveforms (1)(2)(3)(4)
ADDRESS
CE
ADDRESS VALID
tCE
tOE
OE
tDF
tOH
tACC
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
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3353G–FLASH–8/05
12. Input Test Waveform and Measurement Level
2.4V
AC
AC
DRIVING
LEVELS
MEASUREMENT
LEVEL
1.5V
0.4V
tR, tF < 5 ns
13. Output Load Test
3.0V
1.8K
OUTPUT
PIN
30 pF
1.3K
14. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
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AT49BV002A(N)(T)
15. AC Byte Load Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
50
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
50
50
0
ns
tDS
ns
ns
ns
tDH, tOEH
tWPH
Data, OE Hold Time
Write Pulse Width High
50
16. AC Byte Load Waveforms
16.1 WE Controlled
OE
tOES
tOEH
ADDRESS
CE
tAS
tAH
tCH
tCS
WE
tWPH
tWP
tDH
tDS
DATA IN
16.2 CE Controlled
OE
tOES
tOEH
ADDRESS
WE
tAS
tAH
tCH
tCS
CE
tWPH
tWP
tDH
tDS
DATA IN
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3353G–FLASH–8/05
17. Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
50
tAS
0
ns
tAH
50
50
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
50
50
ns
tWPH
tEC
ns
4
8
seconds
18. Program Cycle Waveforms
A0 - A17
19. Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
A0 - A17
DATA
t
t
t
DH
AS
AH
555
555
555
Note 2
AAA
AAA
t
t
EC
DS
55
BYTE 1
80
BYTE 2
55
Note 3
BYTE 5
AA
BYTE 0
AA
BYTE 3
BYTE 4
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under “Command Definition Table” on page 7.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
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AT49BV002A(N)(T)
20. Data Polling Characteristics
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 9.
21. Data Polling Waveforms
WE
CE
t
OEH
OE
t
DH
t
WR
t
OE
HIGH Z
An
I/O7
A0-A17
An
An
An
An
22. Toggle Bit Characteristics
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
50
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 9.
23. Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tOEHP
OE
tOE
tDH
HIGH Z
I/O6
tWR
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
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3353G–FLASH–8/05
24. Software Product Identification
Entry(1)
26. Boot Block Lockout Feature
Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 555
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA 90
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
(2)(3)(5)
MODE
LOAD DATA 55
TO
ADDRESS AAA
25. Software Product Identification
Exit(1)
LOAD DATA 40
TO
ADDRESS 555
OR
LOAD DATA AA
TO
LOAD DATA F0
TO
(2)
PAUSE 1 second
ADDRESS 555
ANY ADDRESS
LOAD DATA 55
TO
ADDRESS AAA
EXIT PRODUCT
IDENTIFICATION
(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
MODE
2. Boot block lockout feature enabled.
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
Additional Device Code is read for address 0003H
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code:1FH
Device Code: 07H - AT49BV002A(N)
08H - AT49BV002A(N)T
Additional Device Code: 0FH - AT49BV002A(N)(T)
14
AT49BV002A(N)(T)
3353G–FLASH–8/05
AT49BV002A(N)(T)
27. Ordering Information
27.1 Standard Package
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
AT49BV002A-70JI
AT49BV002A-70TI
AT49BV002A-70VI
32J
32T
32V
Industrial
(-40° to 85°C)
AT49BV002AN-70JI
AT49BV002AN-70TI
AT49BV002AN-70VI
32J
32T
32V
Industrial
(-40° to 85°C)
70
15
0.05
AT49BV002AT-70JI
AT49BV002AT-70TI
AT49BV002AT-70VI
32J
32T
32V
Industrial
(-40° to 85°C)
AT49BV002ANT-70JI
AT49BV002ANT-70TI
AT49BV002ANT-70VI
32J
32T
32V
Industrial
(-40° to 85°C)
27.2 Green Package Option (Pb/Halide-free)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
AT49BV002AN-70JU
AT49BV002AN-70TU
AT49BV002AN-70VU
32J
32T
32V
Industrial
(-40° to 85°C)
70
15
0.05
AT49BV002ANT-70JU
AT49BV002ANT-70TU
32J
32T
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32-Lead, Thin Small Outline Package (TSOP)
32T
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
15
3353G–FLASH–8/05
28. Packaging Information
28.1 32J – PLCC
1.14(0.045) X 45
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45
0.318(0.0125)
0.191(0.0075)
E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45 MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
3.175
1.524
0.381
12.319
11.354
9.906
14.859
13.894
12.471
0.660
0.330
MAX
3.556
2.413
–
NOM
NOTE
SYMBOL
A
–
D2
A1
A2
D
–
–
–
12.573
D1
D2
E
–
11.506 Note 2
10.922
–
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010 (0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
–
15.113
E1
E2
B
–
14.046 Note 2
13.487
–
–
–
0.813
3. Lead coplanarity is 0.004 (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32J
B
R
16
AT49BV002A(N)(T)
3353G–FLASH–8/05
AT49BV002A(N)(T)
28.2 32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
8.00
D1
E
18.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
17
3353G–FLASH–8/05
28.3 32V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
14.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
13.80
12.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
14.00
12.40
8.00
D1
E
12.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
32V
B
R
18
AT49BV002A(N)(T)
3353G–FLASH–8/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
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2325 Orchard Parkway
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Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Microcontrollers
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Tel: 1(408) 441-0311
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Japan
Tel: (81) 3-3523-3551
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Fax: 1(719) 540-1759
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Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
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