AT49BV010-15JC [ATMEL]
1-Megabit 128K x 8 Single 2.7-volt Battery-Voltage Flash Memory; 1兆位128K ×8单2.7伏的电池电压闪存
| 型号： | AT49BV010-15JC |
| 厂家： | 
ATMEL |
| 描述： | 1-Megabit 128K x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| 文件： | 总11页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Supply Voltage, Range 2.7V to 3.6V
• Single Supply for Read and Write
• Fast Read Access Time - 55 ns
• Internal Program Control and Timer
• 8K bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte By Byte Programming - 30 µs/Byte typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
1-Megabit
(128K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
Description
The AT49(H)BV010 and the AT49(H)LV010 are 3-volt-only, 1-megabit Flash memo-
ries organized as 131,072 words of 8 bits each. Manufactured with Atmel’s advanced
nonvolatile CMOS technology, the devices offer access times to 55 ns with power dis-
sipation of just 90 mW over the commercial temperature range. When the devices are
deselected, the CMOS standby current is less than 50 µA.
To allow for simple in-system reprogrammability, the AT49(H)BV/(H)LV010 does not
require high input voltages for programming. Three-volt-only commands determine
the read and programming operation of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the AT49(H)BV/(H)LV010 is
performed by erasing the entire 1 megabit of memory and then programming on a
byte by byte basis. The typical byte programming time is a fast 30 µs. The end of a
program cycle can be optionally detected by the DATA polling feature. Once the end
of a byte program cycle has been detected, a new access for a read or program can
begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
AT49BV010
AT49HBV010
AT49LV010
AT49HLV010
(continued)
Pin Configurations
Pin Name
A0 - A16
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
WE
I/O0 - I/O7
NC
TSOP Top View
Type 1
PLCC Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
6
7
8
9
10
11
12
13
14
15
16
A2 10
A1 11
A0 12
I/O0 13
A6
A1
0677B-A–9/97
A5
A2
A4
A3
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS
I/O0 - I/O7
VCC
GND
OE
DATA LATCH
OE, CE AND WE
WE
LOGIC
CE
INPUT/OUTPUT
BUFFERS
Y DECODER
ADDRESS
Y-GATING
MAIN MEMORY
INPUTS
X DECODER
(120K BYTES)
01FFF
OPTIONAL BOOT
BLOCK (8K BYTES)
00000
Device Operation
READ: The AT49(H)BV/(H)LV010 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
ERASURE: Before a byte can be reprogrammed, the 128K
bytes memory array (or 120K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Com-
mand Definitions table.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP
cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
AT49(H)BV/(H)LV010
2
AT49(H)BV/(H)LV010
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
DATA POLLING: The AT49(H)BV/(H)LV010 features
DATA polling to indicate the end of a program cycle. Dur-
ing a program cycle an attempted read of the last byte
loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin.
DATA polling may begin at any time during the program
cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49(H)BV/(H)LV010 in the following ways: (a) VCC
sense: if VCC is below 1.8V (typical), the program function
is inhibited. (b) Program inhibit: holding any one of OE low,
CE high or WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
TOGGLE BIT: In addition to DATA polling the
AT49(H)BV/(H)LV010 provides another method for deter-
mining the end of a program or erase cycle. During a pro-
gram or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
4
Addr
5555
5555
Chip Erase
2AAA
2AAA
55
55
5555
5555
80
5555
Addr
AA
DIN
2AAA
2AAA
55
5555
5555
10
Byte
Program
AA
A0
Boot Block
Lockout(1)
6
3
3
1
5555
5555
5555
XXXX
AA
AA
AA
F0
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
90
F0
5555
AA
55
40
Product ID
Entry
Product ID
Exit(2)
Product ID
Exit(2)
Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias......................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground......................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground................... -0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground......................... -0.6V to +13.5V
3
DC and AC Operating Range
AT49HLV
AT49HBV/
HLV010-70
AT49HBV/
HLV010-90
AT49BV/
LV010-12
010-55
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
N/A
AT49BV010-15
0°C - 70°C
-40°C - 85°C
N/A
Operating
Com.
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
Temperature (Case)
Ind.
AT49LV010
AT49BV010
VCC Power Supply
2.7V to 3.6V
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
High Z
VIH
X
X
VIL
VIH
X
X
High Z
VIL
VIL
VIH
A1 - A16 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
A1 - A16 = VIL, A9 = VH,(3)
A0 = VIH
Device Code(4)
Software(5)
A0 = VIL, A1 - A16 = VIL
A0 = VIH, A1 - A16 = VIL
Manufacturer Code(4)
Device Code(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 17H.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
ILI
Parameter
Condition
Min
Max
10
10
50
1
Units
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC
µA
µA
µA
mA
mA
V
ILO
VI/O = 0V to VCC
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
ISB2
(1)
ICC
25
0.6
VIL
VIH
VOL
VOH
Input High Voltage
2.0
2.4
V
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
0.45
V
IOH = -100 µA; VCC = 3.0V
V
Note:
1. In the erase mode, ICC is 50 mA.
AT49(H)BV/(H)LV010
4
AT49(H)BV/(H)LV010
AC Read Characteristics
AT49HLV
010-55
AT49HBV/
HLV010-70
AT49HBV/
HLV010-90
AT49BV/
LV010-12
AT49BV010-
15
Symbol Parameter
Min
Max
Min
Max
70
Min
Max
90
Min
Max
Min
Max
150
150
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
55
55
30
25
120
120
50
(1)
tCE
tOE
tDF
70
90
ns
(2)
35
40
0
0
ns
(3, 4)
CE or OE to Output
Float
0
0
0
0
25
0
0
25
0
0
30
40
ns
tOH
Output Hold from OE,
CE or Address,
whichever occurred first
0
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
OE
tCE
tDF
tACC
tOH
OUTPUT VALID
HIGH Z
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impace on tACC
.
.
3. tDF is specified from OE or CE whichever occurs frist (CL - 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
55/70 ns
90/120/150 ns
3.0V
3.0V
2.4V
AC
AC
DRIVING
LEVELS
1.5V
MEASUREMENT
LEVEL
1.8K
1.3K
1.8K
1.3K
OUTPUT
OUTPUT
0.4V
PIN
PIN
tR, tF < 5 ns
30 pF
100 pF
Pin Capacitance (f = 1 MHz, T = 25°C)(1)
Typ
Max
6
Units
Conditions
CIN
4
8
pF
pF
VIN = 0V
COUT
Note:
12
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
5
AC Byte Load Characteristics
Symbol
AS, tOES
Parameter
Min
0
Max
Units
ns
t
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Byte Load Waveforms
WE Controlled
OE
tOES
tOEH
tCH
ADDRESS
CE
tAS
tCS
tAH
WE
tWP
tDS
tWPH
tDH
DATA IN
CE Controlled
OE
tOES
tOEH
tCH
ADDRESS
WE
tAS
tCS
tAH
CE
tWP
tDS
tWPH
tDH
DATA IN
AT49(H)BV/(H)LV010
6
AT49(H)BV/(H)LV010
Program Cycle Characteristics
Symbol
tBP
Parameter
Min
Typ
Max
Units
µs
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tWPH
tDH
tBP
WE
A0-A16
DATA
tAS
tAH
2AAA
5555
5555
ADDRESS
tDS
INPUT
DATA
AA
55
A0
Chip Erase Cycle Waveforms
OE
CE
tWP
WE
tWPH
tAS
tAH
2AAA
tDH
A0-A16
DATA
5555
5555
5555
2AAA
5555
tDS
tEC
AA
BYTE 0
55
BYTE 1
80
BYTE 2
AA
55
10
BYTE 5
BYTE 3
BYTE 4
Note:
OE must be high only when WE and CE are both low.
7
Data Polling Characteristics(1)
Symbol
tDH
Parameter
Min
0
Typ
Max
Units
ns
Data Hold Time
OE Hold Time
tOEH
tOE
10
ns
OE to Output Delay(2)
ns
tWR
Write Recovery Time
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
An
tWR
I/O7
A0-A17
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
tDH
Parameter
Min
0
Typ
Max
Units
ns
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tDH
tOEHP
OE
tOE
tWR
HIGH Z
I/O6
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49(H)BV/(H)LV010
8
AT49(H)BV/(H)LV010
Software Product
Boot Block Lockout Feature
Enable Algorithm(1)
Identification Entry(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product
LOAD DATA 55
TO
Identification Exit(1)
ADDRESS 2AAA
LOAD DATA AA
LOAD DATA F0
TO
TO
OR
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55
TO
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ADDRESS 2AAA
PAUSE 1 second(2)
LOAD DATA F0
TO
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
ADDRESS 5555
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A16 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does note remain in identification mode
if powered down.
4. The device returns to standard operation mode.
5. Manufacturers Code: 1FH
Device Code: 17H.
9
Ordering Information(1)
I
CC (mA)
Standby
tACC
(ns)
Active
Ordering Code
Package
Operation Range
70
25
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49HBV010-70JC
AT49HBV010-70TC
32J
32T
Commercial
(0°C - 70°C)
25
25
25
25
25
25
25
AT49HBV010-70JI
AT49HBV010-70TI
32J
32T
Industrial
(-40°C - 85°C)
90
AT49HBV010-90JC
AT49HBV010-90TC
32J
32T
Commercial
(0°C - 70°C)
AT49HBV010-90JI
AT49HBV010-90TI
32J
32T
Industrial
(-40°C - 85°C)
120
150
AT49BV010-12JC
AT49BV010-12TC
32J
32T
Commercial
(0°C - 70°C)
AT49BV010-12JI
AT49BV010-12TI
32J
32T
Industrial
(-40°C - 85°C)
AT49BV010-15JC
AT49BV010-15TC
32J
32T
Commercial
(0°C - 70°C)
AT49BV010-15JI
AT49BV010-15TI
32J
32T
Industrial
(-40°C - 85°C)
Note:
1. The 49(H)BV/(H)LV010 has as optional boot block feature. The part number shown in the Ordering Information table is for
devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the
higher address range should contact Atmel.
Package Type
32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC)
32-Lead, Thin Small Outline Package (TSOP)
32J
32T
AT49(H)BV/(H)LV010
10
AT49(H)BV/(H)LV010
Ordering Information (Continued)
I
CC (mA)
Standby
tACC
(ns)
Active
Ordering Code
Package
Operation Range
55
25
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
AT49HLV010-55JC
AT49HLV010-55TC
32J
32T
Commercial
(0°C - 70°C)
25
25
25
25
25
25
25
AT49HLV010-55JI
AT49HLV010-55TI
32J
32T
Industrial
(-40°C - 85°C)
70
AT49HLV010-70JC
AT49HLV010-70TC
32J
32T
Commercial
(0°C - 70°C)
AT49HLV010-70JI
AT49HLV010-70TI
32J
32T
Industrial
(-40°C - 85°C)
90
AT49HLV010-90JC
AT49HLV010-90TC
32J
32T
Commercial
(0°C - 70°C)
AT49HLV010-90JI
AT49HLV010-90TI
32J
32T
Industrial
(-40°C - 85°C)
120
AT49LV010-12JC
AT49LV010-12TC
32J
32T
Commercial
(0°C - 70°C)
AT49LV010-12JI
AT49LV010-12TI
32J
32T
Industrial
(-40°C - 85°C)
Package Type
32J
32T
32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC)
32-Lead, Thin Small Outline Package (TSOP)
11
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