AT49BV020-70JL [ATMEL]
Flash, 256KX8, 70ns, PQCC32, PLASTIC, MS-016AE, LCC-32;
| 型号： | AT49BV020-70JL |
| 厂家： | 
ATMEL |
| 描述： | Flash, 256KX8, 70ns, PQCC32, PLASTIC, MS-016AE, LCC-32 |
| 文件： | 总13页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Supply Voltage, Range 2.7V to 3.6V
• Single Supply for Read and Write
• Fast Read Access Time - 70 ns
• Internal Program Control and Timer
• 8K Bytes Boot Block with Lockout
• Fast Erase Cycle Time - 10 Seconds
• Byte-by-byte Programming - 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling For End of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
2-megabit
(256K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
Description
The AT49BV020 and the AT49LV020 are 3-volt-only, 2-megabit Flash memories
organized as 262,144 words of 8 bits each. Manufactured with Atmel's advanced non-
volatile CMOS technology, the devices offer access times to 70 ns with power dissipa-
tion of just 90 mW over the commercial temperature range. When the device is
deselected, the CMOS standby current is less than 50 µA.
To allow for simple in-system reprogrammability, the AT49BV/LV020 does not require
high input voltages for programming. Three-volt-only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV/LV020 is performed by eras-
ing the entire 2 megabits of memory and then programming on a byte by byte basis.
The typical byte programming time is a fast 30 µs. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the end of a byte program cycle
has been detected, a new access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000 cycles.
AT49BV020
AT49LV020
Not Recommended
for New Design
Contact Atmel to discuss
the latest design in trends
and options
(continued)
Pin Configuration
Pin Name
A0 - A17
CE
Function
VSOP Top View (8 x 14mm) or
Addresses
TSOP Top View (8 x 20mm)
Type 1
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
OE
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
WE
A8
3
A13
A14
A17
WE
VCC
NC
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
I/O0 - I/O7
NC
5
6
7
8
9
PLCC Top View
10
11
12
13
14
15
16
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
A6
A1
A5
A2
A4
A3
A2 10
A1 11
A0 12
I/O0 13
24 OE
23 A10
22 CE
21 I/O7
Rev. 0678E–08/99
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
3FFFF
02000
01FFF
00000
Device Operation
READ: The AT49BV/LV020 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
ERASURE: Before a byte can be reprogrammed, the 256K
bytes memory array (or 248K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
AT49BV/LV020
2
AT49BV/LV020
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49BV/LV020
in the following ways: (a) VCC sense: if VCC is below 1.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
DATA POLLING: The AT49BV/LV020 features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
TOGGLE BIT: In addition to DATA polling the
AT49BV/LV020 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
Command Definition (In Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Data
DOUT
AA
Addr
Data Addr Data Addr Data
Addr
Data Addr Data
Read
1
6
4
Addr
5555
5555
Chip Erase
Byte Program
2AAA
2AAA
55
55
5555
5555
80
A0
5555
Addr
AA
DIN
2AAA
55
55
5555
5555
10
40
AA
Boot Block
Lockout(1)
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
Product ID Entry
Product ID Exit(2)
Product ID Exit(2)
3
3
1
5555
5555
AA
AA
F0
2AAA
2AAA
55
55
5555
5555
90
F0
XXXX
Notes: 1. The 8K byte boot sector has the address range of 00000H to 01FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
3
DC and AC Operating Range
AT49BV/LV020-70
0°C - 70°C
AT49BV/LV020-90
0°C - 70°C
AT49BV/LV020-12
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
AT49LV020
VCC Power Supply
AT49BV020
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High Z
VIH
X
X
VIL
VIH
X
X
High Z
A1 - A17 = VIL, A9 = VH(3), A0 = VIL
A1 - A17 = VIL, A9 = VH,(3), A0 = VIH
A0 = VIL, A1 - A17=VIL
Manufacturer Code(4)
Device Code (4)
Hardware
VIL
VIL
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A17=VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 0BH
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
50
1
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
ISB1
VCC Standby Current CMOS CE = VCC - 0.3V to VCC
ISB2
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
CE = 2.0V to VCC
(1)
ICC
f = 5 MHz; IOUT = 0 mA
25
0.6
VIL
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
V
IOL = 2.1 mA
0.45
V
IOH = -100 µA; VCC = 3.0V
V
Note:
1. In the erase mode, ICC is 50 mA.
AT49BV/LV020
4
AT49BV/LV020
AC Read Characteristics
AT49BV/LV020
-90
-70
-12
Symbol
Parameter
Min
Max
70
Min
Max
90
Min
Max
120
120
50
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
70
90
ns
(2)
tOE
0
0
35
0
0
40
0
0
ns
(3)(4)
tDF
25
25
30
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
OE
t
CE
t
OE
t
DF
t
ACC
t
OH
HIGH Z
OUTPUT
OUTPUT VALID
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
3.0V
2.4V
AC
1.8K
AC
OUTPUT
PIN
DRIVING
LEVELS
1.5V
MEASUREMENT
LEVEL
0.4V
100 pF
1.3K
tR, tF < 5 ns
Pin Capacitance(1)
f = 1 MHz, T = 25°C
Symbol
CIN
Typ
Max
Units
Conditions
VIN = 0V
4
8
6
pF
pF
COUT
12
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Byte Load Waveforms
WE Controlled
OE
ADDRESS
CE
t
t
t
OES
OEH
CH
t
t
t
AH
AS
CS
WE
t
t
WPH
t
DH
WP
t
DS
DATA IN
CE Controlled
OE
t
t
OES
OEH
CH
ADDRESS
WE
t
t
t
AS
AH
t
CS
CE
t
t
WPH
t
DH
WP
t
DS
DATA IN
AT49BV/LV020
6
AT49BV/LV020
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width Height
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
t
t
BP
WP
WPH
DH
WE
t
t
AS
AH
A0-A17
DATA
5555
2AAA
5555
ADDRESS
DS
INPUT
DATA
AA
55
A0
Chip Erase Cycle Waveforms
OE
CE
t
t
t
WP
WPH
DH
WE
t
t
AS
AH
2AAA
A0-A17
DATA
5555
5555
5555
2AAA
5555
t
t
EC
DS
AA
BYTE 0
55
BYTE 1
80
BYTE 2
AA
55
10
BYTE 5
BYTE 3
BYTE 4
Note:
OE must be high only when WE and CE are both low.
7
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
t
OEH
OE
t
t
t
WR
DH
OE
HIGH Z
I/O7
A0-A17
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
t
t
OEH
OEHP
t
OE
t
t
WR
DH
OE
HIGH Z
I/O6
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49BV/LV020
8
AT49BV/LV020
Software Product Identification Entry(1) Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product Identification Exit(1)
OR
LOAD DATA AA
TO
LOAD DATA F0
TO
LOAD DATA 40
TO
ADDRESS 5555
ADDRESS 5555
ANY ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 1 second(2)
LOAD DATA F0
TO
ADDRESS 5555
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 0BH
9
AT49BV020 Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
25
0.05
0.05
0.05
0.05
0.05
0.05
AT49BV020-70JC
AT49BV020-70TC
AT49BV020-70VC
32J
32T
32V
Commercial
(0°C - 70°C)
25
25
25
25
25
AT49BV020-70JI
AT49BV020-70TI
AT49BV020-70VI
32J
32T
32V
Industrial
(-40°C - 85°C)
90
AT49BV020-90JC
AT49BV020-90TC
AT49BV020-90VC
32J
32T
32V
Commercial
(0°C - 70°C)
AT49BV020-90JI
AT49BV020-90TI
AT49BV020-90VI
32J
32T
32V
Industrial
(-40°C - 85°C)
120
AT49BV020-12JC
AT49BV020-12TC
AT49BV020-12VC
32J
32T
32V
Commercial
(0°C - 70°C)
AT49BV020-12JI
AT49BV020-12TI
AT49BV020-12VI
32J
32T
32V
Industrial
(-40°C - 85°C)
Note:
1. The AT49BV020 has an optional boot block feature. The part number shown in the Ordering information table is for devices
with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel
Package Type
32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
32-lead, Thin Small Outline Package (TSOP)
32J
32T
32V
32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
AT49BV/LV020
10
AT49BV/LV020
AT49LV020 Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
25
0.05
0.05
0.05
0.05
0.05
0.05
AT49LV020-70JC
AT49LV020-70TC
AT49LV020-70VC
32J
32T
32V
Commercial
(0°C - 70°C)
25
25
25
25
25
AT49LV020-70JI
AT49LV020-70TI
AT49LV020-70VI
32J
32T
32V
Industrial
(-40°C - 85°C)
90
AT49LV020-90JC
AT49LV020-90TC
AT49LV020-90VC
32J
32T
32V
Commercial
(0°C - 70°C)
AT49LV020-90JI
AT49LV020-90TI
AT49LV020-90VI
32J
32T
32V
Industrial
(-40°C - 85°C)
120
AT49LV020-12JC
AT49LV020-12TC
AT49LV020-12VC
32J
32T
32V
Commercial
(0°C - 70°C)
AT49LV020-12JI
AT49LV020-12TI
AT49LV020-12VI
32J
32T
32V
Industrial
(-40°C - 85°C)
Note:
1. The AT49LV020 has an optional boot block feature. The part number shown in the Ordering information table is for devices
with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel
.
Package Type
32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
32-lead, Thin Small Outline Package (TSOP)
32J
32T
32V
32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
11
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
32T, 32-lead Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BD
.025(.635) X 30˚ - 45˚
.045(1.14) X 45˚ PIN NO. 1
.012(.305)
INDEX
MARK
IDENTIFY
.008(.203)
.530(13.5)
.553(14.0)
.490(12.4)
18.5(.728)
18.3(.720)
20.2(.795)
19.8(.780)
.547(13.9)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.595(15.1)
.585(14.9)
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
0.50(.020)
BSC
AT CONTACT
POINTS
0.25(.010)
0.15(.006)
7.50(.295)
REF
8.20(.323)
7.80(.307)
1.20(.047) MAX
.022(.559) X 45˚ MAX (3X)
0.15(.006)
0.05(.002)
.453(11.5)
.447(11.4)
0
0.20(.008)
0.10(.004)
REF
5
.495(12.6)
.485(12.3)
0.70(.028)
0.50(.020)
* Controlling dimension: millimeters
32V, 32-lead, Plastic Thin Small Outline Package
(VSOP)
Dimensions in Inches and (Millimeters)
JEDEC OUTLINE MO-142 BA
INDEX
MARK
12.5(.492)
12.3(.484)
14.2(.559)
13.8(.543)
0.50(.020)
BSC
0.25(.010)
0.15(.006)
7.50(.295)
REF
8.10(.319)
7.90(.311)
1.20(.047) MAX
0.15(.006)
0.05(.002)
0
0.20(.008)
0.10(.004)
REF
5
0.70(.028)
0.50(.020)
AT49BV/LV020
12
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