AT49BV512-15VC [ATMEL]
512K 64K x 8 Single 2.7-volt Battery-Voltage Flash Memory; 512K 64K ×8单2.7伏的电池电压闪存型号: | AT49BV512-15VC |
厂家: | ATMEL |
描述: | 512K 64K x 8 Single 2.7-volt Battery-Voltage Flash Memory |
文件: | 总11页 (文件大小:122K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• Single Supply Voltage, Range 2.7V to 3.6V
• Single Supply for Read and Write
• Fast Read Access Time - 120 ns
• Internal Program Control and Timer
• 8K bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte By Byte Programming - 30 µs/Byte typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
512K (64K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
Description
The AT49BV512 is a 3-volt-only, 512K Flash memories organized as 65,536 words of
8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
devices offer access times to 120 ns with power dissipation of just 90 mW over the
commercial temperature range. When the devices are deselected, the CMOS standby
current is less than 50 µA.
AT49BV512
To allow for simple in-system reprogrammability, the AT49BV512 does not require
high input voltages for programming. Three-volt-only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing
the entire 1 megabit of memory and then programming on a byte by byte basis. The
(continued)
Pin Configurations
DIP Top View
Pin Name
A0 - A15
CE
Function
NC
NC
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A6
OE
A5
26 A9
A4
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A3
WE
A2 10
A1 11
I/O0 - I/O7
NC
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
PLCC Top View
2
A10
CE
A8
3
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
6
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
7
8
9
10
11
12
13
14
15
16
A2 10
A1 11
A0 12
I/O0 13
A6
A1
A5
A2
Rev. 1026C–09/98
A4
A3
typical byte programming time is a fast 30 µ
s. The end of a
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
program cycle can be optionally detected by the DATA poll-
ing feature. Once the end of a byte program cycle has
been detected, a new access for a read or program can
begin. The typical number of program and erase cycles is
in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP
cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
Block Diagram
DATA INPUTS/OUTPUTS
I/O0 - I/O7
VCC
GND
OE
WE
CE
DATA LATCH
OE, CE AND WE
LOGIC
INPUT/OUTPUT
BUFFERS
Y DECODER
X DECODER
Y-GATING
ADDRESS
INPUTS
FFFFH
MAIN MEMORY
(56K BYTES)
2000H
1FFFH
OPTIONAL BOOT
BLOCK (8K BYTES)
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Com-
mand Definitions table.
0000H
Device Operation
READ: The AT49BV512 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
ERASURE: Before a byte can be reprogrammed, the 64K
bytes memory array (or 56K bytes if the boot block featured
is used) must be erased. The erased state of the memory
bits is a logical “1”. The entire device can be erased at one
time by using a 6-byte software code. The software chip
erase code consists of 6-byte load commands to specific
address locations with a specific data pattern (please refer
to the Chip Erase Cycle Waveforms).
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
AT49BV512
2
AT49BV512
DATA POLLING: The AT49BV512 features DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49BV512 in
the following ways: (a) VCC sense: if VCC is below 1.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
TOGGLE BIT: In addition to DATA polling the AT49BV512
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any
time during a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
Command Definition (in Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
4
Addr
5555
5555
Chip Erase
2AAA
2AAA
55
55
5555
5555
80
5555
Addr
AA
DIN
2AAA
2AAA
55
5555
5555
10
Byte
Program
AA
A0
Boot Block
Lockout(1)
6
3
3
1
5555
5555
5555
XXXX
AA
AA
AA
F0
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
90
F0
5555
AA
55
40
Product ID
Entry
Product ID
Exit(2)
Product ID
Exit(2)
Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias ............................... -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
3
DC and AC Operating Range
AT49BV512-12
0°C - 70°C
AT49BV512-15
0°C - 70°C
Com.
Operating Temperature (Case)
Ind.
-40°C - 85°C
2.7V to 3.6V
-40°C - 85°C
2.7V to 3.6V
V
CC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
High Z
VIH
X
X
VIL
VIH
X
X
High Z
VIL
VIL
VIH
A1 - A15 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
Device Code(4)
A1 - A15 = VIL, A9 = VH,(3)
A0 = VIH
Software(5)
A0 = VIL, A1 - A15 = VIL
A0 = VIH, A1 - A15 = VIL
Manufacturer Code(4)
Device Code(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 03H.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol Parameter
Condition
Min
Max
10
10
50
1
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
ISB1
ISB2
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
VI/O = 0V to VCC
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
(1)
ICC
VIL
VIH
VOL
25
0.6
Input Low Voltage
Input High Voltage
2.0
2.4
V
Output Low Voltage
IOL = 2.1 mA
0.45
V
VOH
Output High Voltage
IOH = -100 µA; VCC = 3.0V
V
Note:
1. In the erase mode, ICC is 50 mA.
AT49BV512
4
AT49BV512
AC Read Characteristics
AT49BV512-12
AT49BV512-15
Symbol
Parameter
Min
Max
120
120
50
Min
Max
150
150
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
(1)
tCE
ns
(2)
tOE
OE to Output Delay
0
0
0
ns
(3, 4)
tDF
CE or OE to Output Float
Output Hold from OE, CE or Address, whichever occurred first
0
0
30
40
ns
tOH
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
OE
tCE
tDF
tACC
tOH
OUTPUT VALID
HIGH Z
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs frist (CL - 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
2.4V
Output Test Load
3.0V
AC
AC
1.8K
1.3K
DRIVING
LEVELS
1.5V
MEASUREMENT
LEVEL
OUTPUT
PIN
0.4V
tR, tF < 5 ns
100 pF
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
CIN
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Byte Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
CE
tAS
tCS
tAH
tCH
WE
tWP
tDS
tWPH
tDH
DATA IN
CE Controlled
OE
tOES
tOEH
tCH
ADDRESS
WE
tAS
tCS
tAH
CE
tWP
tDS
tWPH
tDH
DATA IN
AT49BV512
6
AT49BV512
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tAH
tWPH
tBP
WE
tAS
tDH
A0-A15
5555
2AAA
5555
ADDRESS
tDS
INPUT
DATA
DATA
AA
55
A0
Chip Erase Cycle Waveforms
OE
CE
tWP
tAH
tWPH
WE
A0-A15
DATA
tAS
tDH
5555
2AAA
5555
5555
2AAA
5555
tDS
tEC
AA
BYTE 0
55
BYTE 1
80
BYTE 2
AA
BYTE 3
55
10
BYTE 5
BYTE 4
Note:
OE must be high only when WE and CE are both low.
7
Data Polling Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
An
tWR
I/O7
A0-A15
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
0
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
ns
OE High Pulse
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tDH
tOEHP
OE
tOE
tWR
HIGH Z
I/O6
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49BV512
8
AT49BV512
Software Product
Boot Block Lockout Feature
Enable Algorithm(1)
Identification Entry(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product
LOAD DATA 55
TO
Identification Exit(1)
ADDRESS 2AAA
LOAD DATA AA
LOAD DATA F0
TO
TO
OR
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55
TO
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ADDRESS 2AAA
PAUSE 1 second(2)
LOAD DATA F0
TO
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
ADDRESS 5555
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does note remain in identification mode
if powered down.
4. The device returns to standard operation mode.
5. Manufacturers Code: 1FH
Device Code: 03H.
9
Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
25
0.05
0.05
0.05
0.05
AT49BV512-12JC
AT49BV512-12PC
AT49BV512-12TC
AT49BV512-12VC
32J
Commercial
32P6
32T
32V
(0°C - 70°C)
25
25
25
AT49BV512-12JI
AT49BV512-12PI
AT49BV512-12TI
AT49BV512-12VI
32J
Industrial
32P6
32T
32V
(-40°C - 85°C)
150
AT49BV512-15JC
AT49BV512-15PC
AT49BV512-15TC
AT49BV512-15VC
32J
Commercial
32P6
32T
32V
(0°C - 70°C)
AT49BV512-15JI
AT49BV512-15PI
AT49BV512-15TI
AT49BV512-15VI
32J
Industrial
32P6
32T
32V
(-40°C - 85°C)
Note:
1. The AT49BV512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring boot block protection to be in the
higher address range should contact Atmel.
Package Type
32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC)
32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32-Lead, Thin Small Outline Package (TSOP) (8 x 20 mm)
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
32J
32P6
32T
32V
AT49BV512
10
AT49BV512
Packaging Information
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
32P6, 32-Lead, 0.600” Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
1.67(42.4)
1.64(41.7)
.025(.635) X 30° - 45°
PIN
1
.045(1.14) X 45° PIN NO. 1
.012(.305)
IDENTIFY
.008(.203)
.530(13.5)
.566(14.4)
.530(13.5)
.553(14.0)
.490(12.4)
.547(13.9)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.595(15.1)
.585(14.9)
.090(2.29)
MAX
1.500(38.10) REF
.030(.762)
.015(3.81)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.050(1.27) TYP
.220(5.59)
MAX
.300(7.62) REF
.430(10.9)
.390(9.90)
.005(.127)
MIN
AT CONTACT
POINTS
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.065(1.65)
.041(1.04)
.022(.559) X 45° MAX (3X)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
.453(11.5)
.447(11.4)
0
15
.495(12.6)
.485(12.3)
REF
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
32T, 32-Lead, Plastic Thin Small Outline Package
(TSOP) Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 BD
32V, 32-Lead, Plastic Thin Small Outline Package
(VSOP)
Dimensions in Millimeters (Inches)
INDEX
MARK
INDEX
MARK
18.5(.728)
18.3(.720)
20.2(.795)
19.8(.780)
12.5(.492)
12.3(.484)
14.2(.559)
13.8(.543)
0.50(.020)
BSC
0.50(.020)
BSC
0.25(.010)
0.15(.006)
0.25(.010)
0.15(.006)
7.50(.295)
REF
7.50(.295)
REF
8.20(.323)
7.80(.307)
8.10(.319)
7.90(.311)
1.20(.047) MAX
1.20(.047) MAX
0.15(.006)
0.05(.002)
0.15(.006)
0.05(.002)
0
0
0.20(.008)
0.10(.004)
REF
5
0.20(.008)
0.10(.004)
REF
5
0.70(.028)
0.50(.020)
0.70(.028)
0.50(.020)
*Controlling dimensions: millimeters
11
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