AT49BV8192-20RC [ATMEL]
8-Megabit 512K x 16 CMOS Flash Memory; 8兆位512K ×16的CMOS闪存
| 型号： | AT49BV8192-20RC |
| 厂家： | 
ATMEL |
| 描述： | 8-Megabit 512K x 16 CMOS Flash Memory |
| 文件： | 总13页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low Voltage Operation
– 2.7V Read
– 5V Program/Erase
• Fast Read Access Time - 120 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 8K Words (16K bytes) Parameter Blocks
– One 488K Words (976K bytes) Main Memory Array Block
• Fast Sector Erase Time - 10 seconds
• Word-By-Word Programming - 30 µs/Word
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles
8-Megabit
(512K x 16)
CMOS Flash
Memory
Description
The AT49BV8192 and AT49LV8192 are 3-volt, 8-megabit Flash Memories organized
as 512K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile
CMOS technology, the devices offer access times to 120 ns with power dissipation of
just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than 50
AT49BV8192
AT49BV8192T
AT49LV8192
AT49LV8192T
µA.
(continued)
Pin Configurations
Pin Name
A0 - A18
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
SOIC (SOP)
RESET
VPP
A18
A17
A7
A6
A5
1
2
3
Program/Erase Power
Supply
44
RESET
VPP
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A8
A9
A10
A11
A12
Data
Inputs/Outputs
I/O0 - I/O15
NC
5
6
7
8
A4
A3
No Connect
A2
A1
A0
9
TSOP Top View
Type 1
A14
A15
A16
NC
10
11
12
13
CE
GND
A16
A15
1
3
5
7
9
48
46
44
42
40
NC
A14
A12
A10
A8
2
47
45
43
GND
GND
A13
A11
A9
I/O15
4
6
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
I/O7
I/O6
I/O5
15
16
17
18
19
20
21
22
I/O14
I/O13
I/O12
VCC
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
8
41
39
37
35
NC
NC
10
WE
11
13
38
36
I/O4
RESET
12
14
I/O11
I/O10
I/O9
VPP
NC
I/O3
I/O2
NC
15
17
34
32
A18
A7
16
18
33
31
A17
I/O1
I/O0
A6
A4
19
21
23
30
28
26
I/O8
OE
CE
VCC
29
27
25
A5
A3
A1
20
22
24
0978B-A–11/97
GND
A0
A2
The device contains a user-enabled “boot block” protection
feature. Two versions of the feature are available: the
AT49BV/LV8192 locates the boot block at lowest order
addresses (“bottom boot”); the AT49BV/LV8192T locates it
at highest order addresses (“top boot”)
main memory array block. The AT49BV/LV8192 is pro-
grammed on a word-by-word basis.
The device has the capability to protect the data in the boot
block; this feature is enabled by a command sequence.
Once the boot block programming lockout feature is
enabled, the data in the boot block cannot be changed
when input levels of 3.6 volts or less are used. The typical
number of program and erase cycles is in excess of 10,000
cycles.
To allow for simple in-system reprogrammability, the
AT49BV/LV8192 does not require high input voltages for
programming. Reading data out of the device is similar to
reading from an EPROM; it has standard CE, OE, and WE
inputs to avoid bus contention. Reprogramming the
AT49BV/LV8192 is performed by first erasing a block of
data and then programming on a word-by-word basis.
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into three blocks for erase
operations. There are two 8K word parameter block sec-
tions and one sector consisting of the boot block and the
During a chip erase, sector erase, or word programming,
the VPP pin must be at 5V ± 10%.
Block Diagram
AT49BV/LV8192
AT49BV/LV8192T
VCC
VPP
DATA INPUTS/OUTPUTS
DATA INPUTS/OUTPUTS
I/O0 - I/O15
I/O0 - I/O15
GND
OE
WE
CE
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
CONTROL
LOGIC
PROGRAM DATA
LATCHES
PROGRAM DATA
LATCHES
RESET
Y-GATING
Y-GATING
Y DECODER
X DECODER
7FFFF
7FFFF
ADDRESS
INPUTS
MAIN MEMORY
(488K WORDS)
BOOT BLOCK
8K WORDS
06000
05FFF
7E000
7DFFF
PARAMETER
BLOCK 2
8K WORDS
PARAMETER
BLOCK 1
8K WORDS
04000
03FFF
7C000
7BFFF
PARAMETER
BLOCK 1
8K WORDS
PARAMETER
BLOCK 2
8K WORDS
02000
01FFF
7A000
79FFF
BOOT BLOCK
8K WORDS
MAIN MEMORY
(488K WORDS)
00000
00000
Device Operation
READ: The AT49BV/LV8192 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
AT49BV/LV8192(T)
2
AT49BV/LV8192(T)
signal to the RESET pin the boot block array can be repro-
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the
49BV/LV8192 boot block is 00000H to 01FFFH while the
address range of the 49BV/LV8192T is 7E000H to
7FFFFH.
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of memory bits is a logical “1”.
The entire device can be erased by using the Chip Erase
command or individual sectors can be erased by using the
Sector Erase commands.
CHIP ERASE: The entire device can be erased at one
time by using the 6-byte chip erase software code. After the
chip erase has been initiated, the device will internally time
the erase operation so that no external clocks are required.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
The maximum time to erease the chip is tEC
.
If the boot block lockout has been enabled, the Chip Erase
will not erase the data in the boot block; it will erase the
main memory block and the parameter blocks only. After
the chip erase, the device will return to the read or standby
mode.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been enabled and the block cannot be pro-
grammed. The software product identification exit code
should be used to return to standard operation.
SECTOR ERASE: As an alternative to a full chip erase,
the device is organized into three sectors that can be indi-
vidually erased. There are two 8K word parameter block
sections and one sector consisting of the boot block and
the main memory array block. The Sector Erase command
is a six bus cycle operation. The sector address is latched
on the falling WE edge of the sixth cycle while the 30H data
input command is latched at the rising edge of WE. The
sector erase starts after the rising edge of WE of the sixth
cycle. The erase operation is internally controlled; it will
automatically time to completion. When the boot block pro-
gramming lockout feature is not enabled, the boot block
and the main memory block will erase together (from the
same sector erase command). Once the boot region has
been protected, only the main memory array sector will
erase when its sector erase command is issued.
BOOT BLOCK PROGRAMMING LOCKOUT OVER-
RIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12 volts during the
entire chip erase, sector erase or word programming oper-
ation. When the RESET pin is brought back to TTL levels
the boot block programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a word-by-
word basis. Programming is accomplished via the internal
device command register and is a 4 bus cycle operation.
The device will automatically generate the required internal
program pulses.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The DATA polling feature may
also be used to indicate the end of a program cycle.
DATA POLLING: The AT49BV/LV8192 features DATA
polling to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. During a chip
or sector erase operation, an attempt to read the device will
give a “0” on I/O7. Once the program or erase cycle has
completed, true data will be read from the device. DATA
polling may begin at any time during the program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
3
TOGGLE BIT: In addition to DATA polling the
AT49BV/LV8192 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
ited. (b) VCC power on delay: once VCC has reached the
VCC sense level, the device will automatically time out 10
ms (typical) before programming. (c) Program inhibit: hold-
ing any one of OE low, CE high or WE high inhibits pro-
gram cycles. (d) Noise filter: pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a program
cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs (OE,
CE, and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to VCC + 0.6V.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49BV/LV8192 in the following ways: (a) VCC sense: if
VCC is below 1.8V (typical), the program function is inhib-
AT49BV/LV8192(T)
4
AT49BV/LV8192(T)
Command Definition (in Hex)(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles Addr Data Addr Data Addr Data Addr Data Addr Data
Addr
Data
Read
1
6
6
4
6
3
3
1
Addr DOUT
Chip Erase
5555
5555
5555
5555
5555
5555
xxxx
AA
AA
AA
AA
AA
AA
F0
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
55
5555
5555
5555
5555
5555
5555
80
80
A0
80
90
F0
5555
5555
Addr
5555
AA
AA
DIN
AA
2AAA
2AAA
55
55
5555
10
30
Sector Erase
SA(4)(5)
Word Program
Boot Block Lockout(2)
Product ID Entry
Product ID Exit(3)
Product ID Exit(3)
2AAA
55
5555
40
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
2. The 8K word boot sector has the address range 00000H to 01FFFH for the AT49BV/LV8192 and 7E000H to 7FFFFH for the
AT49BV/LV8192T.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
For the AT49BV/LV8192
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 7FXXX for MAIN MEMORY ARRAY
For the AT49BV/LV8192T
SA = 7DXXX for PARAMETER BLOCK 1
SA = 7BXXX for PARAMETER BLOCK 2
SA = 79XXX for MAIN MEMORY ARRAY
5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase
together (form the same sector erase command). Once the boot region has been protected, only the main memory array
sector will erase when its sector erase command is issued.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on RESET
with Respect to Ground...................................-0.6V to +13.5V
5
DCand AC Operating Range
AT49BV/LV8192-12
0°C - 70°C
AT49BV/LV8192-15
0°C - 70°C
AT49BV/LV8192-20
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
-40°C - 85°C
3.0V to 3.6V
-40°C - 85°C
3.0V to 3.6V
-40°C - 85°C
3.0V to 3.6V
AT49LV8192
VCC Power Supply
AT49BV8192
2.7V to 3.6V
2.7V to 3.6V
2.7V to 3.6V
Operating Modes
Mode
CE
VIL
VIL
OE
VIL
VIH
WE
VIH
VIL
RESET
VIH
VPP
X
Ai
Ai
Ai
I/O
Read
DOUT
DIN
Program/Erase(2)
VIH
5V ± 10%
Standby/Program
Inhibit
VIH
X(1)
X
VIH
X
X
High Z
Program Inhibit
Program Inhibit
Output Disable
Reset
X
X
X
X
X
VIL
VIH
X
VIH
X
VIH
VIH
VIH
VIL
VIL
VIL
X
X
High Z
High Z
X
X
X
Product Identification
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIH
A0 = VIL, A1 - A18 = VIL
A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: A0H (49BV/LV8192), A3H (49BV/LV8192T).
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
50
1
Units
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC
µA
µA
µA
mA
mA
V
ILO
VI/O = 0V to VCC
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
ISB2
(1)
ICC
25
0.6
VIL
VIH
VOL
VOH
Input High Voltage
2.0
2.4
V
Output Low Voltage
IOL = 2.1 mA
0.45
V
Output High Voltage
IOH = -400 µA
V
Note:
1. In the erase mode, ICC is 50 mA.
AT49BV/LV8192(T)
6
AT49BV/LV8192(T)
AC Read Characteristics
AT49BV/LV8192-12
AT49BV/LV8192-15
AT49BV/LV8192-20
Symbol
Parameter
Min
Max
120
120
50
Min
Max
150
150
100
50
Min
Max
200
200
100
50
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
ns
(2)
tOE
0
0
0
0
0
0
ns
(3)(4)
tDF
30
ns
Output Hold from OE, CE
or Address, whichever occurred first
tOH
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
(f = 1 Mhz, T = 25°C)(1)
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
CIN
COUT
Note:
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
7
AC Word Load Characteristics
Symbol
Parameter
Min
10
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
200
100
10
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
200
ns
AC Word Load Waveforms
WE Controlled
CE Controlled
AT49BV/LV8192(T)
8
AT49BV/LV8192(T)
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Word Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
30
tAS
0
ns
tAH
100
100
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
200
200
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
BP
t
WP
WPH
WE
t
t
t
AS
AH
DH
5555
5555
5555
2AAA
ADDRESS
AO-A18
DATA
t
DS
INPUT
DATA
55
A0
AA
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
AO-A18
DATA
t
t
t
DH
AS
AH
5555
5555
5555
Note
2
2AAA
2AAA
t
t
EC
DS
55
WORD
80
55
WORD
Note 3
AA
WORD
AA
WORD
0
1
WORD
2
3
4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
9
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
10
ns
tOE
OE to Output Delay(2)
OE High Pulse
ns
tOEHP
tWR
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49BV/LV8192(T)
10
AT49BV/LV8192(T)
Software Product
Boot Block
Identification Entry(1)
Lockout Enable Algorithm(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE (2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product
Identifcation Exit(1)(6)
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA AA
TO
LOAD DATA F0
TO
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
MODE (4)
PAUSE 1 second
LOAD DATA F0
TO
ADDRESS 5555
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE (4)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A14 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if pow-
ered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: A0H (49BV/LV8192), A3H (49BV/LV8192T)
6. Either one of the Product ID Exit commands can be used.
11
Ordering Information
ICC (mA)
Active
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
120
25
25
25
25
25
25
0.05
AT49BV8192-12RC
AT49BV8192-12TC
44R
48T
Commercial
(0° to 70°C)
AT49BV8192-12RI
AT49BV8192-12TI
44R
48T
Industrial
(-40° to 85°C)
150
200
120
150
200
0.05
0.05
0.05
0.05
0.05
AT49BV8192-15RC
AT49BV8192-15TC
44R
48T
Commercial
(0° to 70°C)
AT49BV8192-15RI
AT49BV8192-15TI
44R
48T
Industrial
(-40° to 85°C)
AT49BV8192-20RC
AT49BV8192-20TC
44R
48T
Commercial
(0° to 70°C)
AT49BV8192-20RI
AT49BV8192-20TI
44R
48T
Industrial
(-40° to 85°C)
AT49LV8192-12RC
AT49LV8192-12TC
44R
48T
Commercial
(0° to 70°C)
AT49LV8192-12RI
AT49LV8192-12TI
44R
48T
Industrial
(-40° to 85°C)
AT49LV8192-15RC
AT49LV8192-15TC
44R
48T
Commercial
(0° to 70°C)
AT49LV8192-15RI
AT49LV8192-15TI
44R
48T
Industrial
(-40° to 85°C)
AT49LV8192-20RC
AT49LV8192-20TC
44R
48T
Commercial
(0° to 70°C)
AT49LV8192-20RI
AT49LV8192-20TI
44R
48T
Industrial
(-40° to 85°C)
Package Type
44R
48T
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
48-Lead, Thin Small Outline Package (TSOP)
AT49BV/LV8192(T)
12
AT49BV/LV8192(T)
Ordering Information
ICC (mA)
Active
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
120
25
25
25
25
25
25
0.05
AT49BV8192T-12RC
AT49BV8192T-12TC
44R
48T
Commercial
(0° to 70°C)
AT49BV8192T-12RI
AT49BV8192T-12TI
44R
48T
Industrial
(-40° to 85°C)
150
200
120
150
200
0.05
0.05
0.05
0.05
0.05
AT49BV8192T-15RC
AT49BV8192T-15TC
44R
48T
Commercial
(0° to 70°C)
AT49BV8192T-15RI
AT49BV8192T-15TI
44R
48T
Industrial
(-40° to 85°C)
AT49BV8192T-20RC
AT49BV8192T-20TC
44R
48T
Commercial
(0° to 70°C)
AT49BV8192T-20RI
AT49BV8192T-20TI
44R
48T
Industrial
(-40° to 85°C)
AT49LV8192T-12RC
AT49LV8192T-12TC
44R
48T
Commercial
(0° to 70°C)
AT49LV8192T-12RI
AT49LV8192T-12TI
44R
48T
Industrial
(-40° to 85°C)
AT49LV8192T-15RC
AT49LV8192T-15TC
44R
48T
Commercial
(0° to 70°C)
AT49LV8192T-15RI
AT49LV8192T-15TI
44R
48T
Industrial
(-40° to 85°C)
AT49LV8192T-20RC
AT49LV8192T-20TC
44R
48T
Commercial
(0° to 70°C)
AT49LV8192T-20RI
AT49LV8192T-20TI
44R
48T
Industrial
(-40° to 85°C)
Package Type
44R
48T
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
48-Lead, Thin Small Outline Package (TSOP)
13
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