AT49F020-55PC [ATMEL]
2-Megabit 256K x 8 5-volt Only CMOS Flash Memory; 2兆位256K ×8 5伏只有CMOS闪存型号: | AT49F020-55PC |
厂家: | ATMEL |
描述: | 2-Megabit 256K x 8 5-volt Only CMOS Flash Memory |
文件: | 总10页 (文件大小:87K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• Single Voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time - 55 ns
• Internal Program Control and Timer
• 8K bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte By Byte Programming - 50 µs/Byte
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 50 mA Active Current
– 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
2-Megabit
(256K x 8)
5-volt Only
CMOS Flash
Memory
Description
The AT49F020 is a 5-volt-only in-system Flash Memory. Its 2 megabits of memory is
organized as 262,144 words by 8 bits. Manufactured with Atmel’s advanced nonvola-
tile CMOS technology, the device offers access times to 55 ns with power dissipation
of just 275 mW over the commercial temperature range. When the device is dese-
lected, the CMOS standby current is less than 100 µA.
AT49F020
To allow for simple in-system reprogrammability, the AT49F020 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F020 is performed by erasing the
entire 2 megabits of memory and then programming on a byte by byte basis. The byte
programming time is a fast 50 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin. The typical number of pro-
gram and erase cycles is in excess of 10,000 cycles.
(continued)
DIP Top View
Pin Configurations
NC
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 WE
30 A17
29 A14
28 A13
27 A8
Pin Name
A0 - A17
CE
Function
Addresses
A6
A5
26 A9
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A4
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A3
A2 10
A1 11
OE
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
WE
I/O0 - I/O7
NC
TSOP Top View
Type 1
PLCC Top View
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
A17
WE
VCC
NC
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
6
7
8
9
10
11
12
13
14
15
16
A2 10
A1 11
A0 12
I/O0 13
0567B-A–8/97
A6
A1
A5
A2
A4
A3
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS
I/O0 - I/O7
VCC
GND
OE
DATA LATCH
OE, CE AND WE
WE
LOGIC
CE
INPUT/OUTPUT
BUFFERS
Y DECODER
ADDRESS
Y-GATING
MAIN MEMORY
(248K BYTES)
INPUTS
X DECODER
OPTIONAL BOOT
BLOCK (8K BYTES)
Device Operation
READ: The AT49F020 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
ERASURE: Before a byte can be reprogrammed, the 256K
bytes memory array (or 248K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
AT49F020
2
AT49F020
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
TOGGLE BIT: In addition to DATA polling the AT49F020
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F020 in
the following ways: (a) VCC sense: if VCC is below 3.8V (typ-
ical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits pro-
gram cycles. (c) Noise filter: pulses of less than 15 ns (typi-
cal) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: The AT49F020 features DATA polling to
indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
Command Definition (in Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
4
Addr
5555
5555
Chip Erase
2AAA
2AAA
55
55
5555
5555
80
5555
Addr
AA
DIN
2AAA
2AAA
55
5555
5555
10
Byte Program
AA
A0
Boot Block
Lockout (1)
6
3
3
1
5555
5555
5555
XXXX
AA
AA
AA
F0
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
90
F0
5555
AA
55
40
Product ID
Entry
Product ID Exit
(2)
Product ID Exit
(2)
Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
3
DC and AC Operating Range
AT49F020-55
AT49F020-70
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT49F020-90
0°C - 70°C
-40°C - 85°C
5V ± 10%
Com.
Ind.
0°C - 70°C
-40°C - 85°C
5V ± 10%
Operating
Temperature (Case)
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
DOUT
DIN
Read
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High Z
VIH
X
X
VIL
VIH
X
X
High Z
A1 - A17 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
A1 - A17 = VIL, A9 = VH,(3)
A0 = VIH
A0 = VIL, A1 - A17=VIL
A0 = VIH, A1 - A17=VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code 0BH.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
10
Com.
Ind.
100
300
3
ISB1
ISB2
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
VCC Standby Current TTL
VCC Active Current
CE = 2.0V to VCC
(1)
ICC
f = 5 MHz; IOUT = 0 mA
50
VIL
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
IOL = 2.1 mA
.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
Note:
In the erase mode, ICC is 90 mA.
AT49F020
4
AT49F020
AC Read Characteristics
AT49F020-55
AT49F020-70
AT49F020-90
Symbol
Parameter
Min
Max
55
Min
Max
70
Min
Max
90
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
55
70
90
ns
(2)
tOE
0
0
30
25
0
0
35
25
0
0
40
25
ns
(3)(4)
tDF
ns
Output Hold from OE, CE or
Address, whichever occurred first
tOH
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
OE
t
CE
t
DF
t
ACC
t
OH
HIGH Z
OUTPUT
OUTPUT VALID
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
3.0V
AC
AC
5.0V
DRIVING
LEVELS
1.5V
MEASUREMENT
LEVEL
1.8K
0.0V
OUTPUT
PIN
tR, tF < 5 ns
100 pF
1.3K
Pin Capacitance(1)
(f = 1 MHz, T = 25°C)
Typ
4
Max
6
Units
pF
Conditions
CIN
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Byte Load Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
50
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
90
50
0
ns
ns
tDS
tDH, tOEH Data, OE Hold Time
tWPH Write Pulse Width High
ns
ns
90
AC Byte Load Waveforms
WE Controlled
OE
ADDRESS
CE
t
t
t
OES
OEH
CH
t
t
t
AH
AS
CS
WE
t
t
WPH
t
DH
WP
t
DS
DATA IN
CE Controlled
OE
t
t
t
OES
OEH
CH
ADDRESS
WE
t
t
AH
AS
t
CS
CE
t
t
WPH
t
DH
WP
t
DS
DATA IN
AT49F020
6
AT49F020
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
50
tAS
0
ns
tAH
50
50
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
90
90
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
t
t
BP
WP
WPH
DH
WE
t
t
AS
AH
A0-A17
DATA
5555
2AAA
5555
ADDRESS
DS
INPUT
DATA
AA
55
A0
Chip Erase Cycle Waveforms
OE
CE
t
t
t
WP
WPH
WE
t
t
AS
AH
2AAA
DH
A0-A17
DATA
5555
5555
5555
2AAA
5555
t
t
EC
DS
AA
BYTE 0
55
BYTE 1
80
AA
BYTE 3
55
BYTE 4
10
BYTE 5
BYTE 2
Note:
OE must be high only when WE and CE are both low.
7
Data Polling Characteristics (1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay (2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics
Data Polling Waveforms
WE
CE
t
OEH
OE
t
t
t
WR
DH
OE
I/O7
A0-A17
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
t
t
OEH
OEHP
t
OE
t
t
WR
DH
OE
HIGH Z
I/O6
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49F020
8
AT49F020
Software Product
Boot Block Lockout Feature
Enable Algorithm(1)
Identification Entry(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
LOAD DATA AA
TO
ADDRESS 5555
(2)(3)(5)
MODE
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product
Identification Exit(1)
OR
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
(2)
(4)
PAUSE 1 second
MODE
LOAD DATA F0
TO
ADDRESS 5555
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturers Code: 1FH
Device Code: 0BH.
9
Ordering Information (1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
AT49F020-55JC
AT49F020-55PC
AT49F020-55TC
AT49F020-55JI
AT49F020-55PI
AT49F020-55TI
AT49F020-70JC
AT49F020-70PC
AT49F020-70TC
AT49F020-70JI
AT49F020-70PI
AT49F020-70TI
AT49F020-90JC
AT49F020-90PC
AT49F020-90TC
AT49F020-90JI
AT49F020-90PI
AT49F020-90TI
Package
32J
Operation Range
Commercial
55
70
90
50
0.1
32P6
32T
(0° to 70°C)
50
50
50
50
50
0.3
0.1
0.3
0.1
0.3
32J
Industrial
32P6
32T
(-40° to 85°C)
32J
Commercial
32P6
32T
(0° to 70°C)
32J
Industrial
32P6
32T
(-40° to 85°C)
32J
Commercial
32P6
32T
(0° to 70°C)
32J
Industrial
32P6
32T
(-40° to 85°C)
Note:
The AT49F020 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with
the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher address
range should contact Atmel.
Package Type
32 Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32 Lead, Thin Small Outline Package (TSOP)
32J
32P6
32T
AT49F020
10
相关型号:
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