AT49F080-15CI [ATMEL]
Flash, 1MX8, 150ns, PBGA42, 8 X 14 MM, 1 MM PITCH, PLASTIC, CBGA-42;
| 型号： | AT49F080-15CI |
| 厂家： | 
ATMEL |
| 描述： | Flash, 1MX8, 150ns, PBGA42, 8 X 14 MM, 1 MM PITCH, PLASTIC, CBGA-42 内存集成电路 |
| 文件： | 总16页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time - 90 ns
• Internal Program Control and Timer
• 16K Bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte-By-Byte Programming - 10 µs/Byte Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 50 mA Active Current
– 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
8-Megabit
(1M x 8)
5-volt Only
Flash Memory
Description
The AT49F080(T) is a 5-volt only in-system Flash Memory device. Its 8-megabits of
memory is organized as 1,024,576 words by 8-bits. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 90 ns with
power dissipation of just 275 mW over the commercial temperature range. When the
device is deselected, the CMOS standby current is less than 100 µA.
AT49F080
AT49F080T
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49F080 locates the boot block at lowest order
addresses (“bottom boot”); the AT49F080T locates it at highest order addresses (“top
(continued)
boot”).
SOIC
Pin Configurations
NC
RESET
A11
A10
A9
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
2
Pin Name
A0 - A19
CE
Function
3
A12
A13
A14
A15
A16
A17
A18
A19
NC
4
5
Addresses
A8
6
A7
7
A6
8
Chip Enable
Output Enable
Write Enable
Reset
A5
9
A4
10
11
12
13
14
15
16
17
18
19
20
21
22
OE
NC
NC
NC
A3
NC
WE
A2
NC
A1
WE
RESET
RDY/BUSY
I/O0 - I/O7
NC
A0
OE
I/O0
I/O1
I/O2
I/O3
GND
GND
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
Ready/Busy Output
Data Inputs/Outputs
No Connect
TSOP Top VIew
Type 1
CBGA Top View
1
2
3
4
5
6
7
A19
A18
A17
A16
A15
A14
A13
A12
CE
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
2
NC
3
WE
A
B
C
D
E
F
4
OE
A5 A8 A11 NC A12 A15 A17
A4 A7 A10 VCC A13 NC A18
A6 A9 RST CE A14 A16 A19
A3 I/O1 NC VCC I/O4 I/O7 NC
A2 A0 I/O3 GND I/O6 OE NC
A1 I/O0 I/O2 GND I/O5 RY/BY WE
5
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
GND
GND
I/O3
I/O2
I/O1
I/O0
A0
6
7
8
9
VCC
NC
10
11
12
13
14
15
16
17
18
19
20
RESET
A11
A10
A9
A8
Rev. 0584C–10/98
A7
A6
A1
A5
A2
A4
A3
To allow for simple in-system reprogrammability, the
AT49F080(T) does not require high input voltages for pro-
gramming. 5-volt-only commands determine the read and
programming operation of the device. Reading data out of
the device is similar to reading from an EPROM. Repro-
gramming the AT49F080(T) is performed by erasing the
entire 8 megabits of memory and then programming on a
byte-by-byte basis. The typical byte programming time is a
fast 10 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
AT49F080
AT49F080T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
8
8
OE
WE
CE
DATA LATCH
DATA LATCH
OE, CE, AND WE
LOGIC
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
Y DECODER
X DECODER
Y-GATING
Y-GATING
FFFFFH
FFFFFH
ADDRESS
INPUTS
MAIN MEMORY
(1008K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
04000H
03FFFH
FC000H
FBFFFH
OPTIONAL BOOT
MAIN MEMORY
(1008K BYTES)
BLOCK (16K BYTES)
00000H
00000H
Device Operation
READ: The AT49F080(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus con-
tention.
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
AT49F080(T)
2
AT49F080(T)
optional to the user. The address range of the AT49F080
boot block is 00000H to 03FFFH while the address range
of the AT49F080T boot block is FC000H to FFFFFH.
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling, the
AT49F080(T) provides another method for determining the
end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop tog-
gling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out for the AT49F080, and a read from address
location F3002H will show if programming the boot block is
locked out for the AT49F080T. If the data on I/O0 is low,
the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been activated and
the block cannot be programmed. The software product
identification exit code should be used to return to standard
operation.
RDY/BUSY: An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR - tying of several devices to the same
RDY/BUSY line.
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program
or erase operation, the operation may not be successfully
completed and the operation will have to be repeated after
a high level is applied to the RESET pin. When a high level
is reasserted on the RESET pin, the device returns to the
read or standby mode, depending upon the state of the
control inputs. By applying a 12V ± 0.5V input signal to the
RESET pin, the boot block array can be reprogrammed
even if the boot block lockout feature has been enabled
(see Boot Block Programming Lockout Override section).
BOOT BLOCK PROGRAMMING LOCKOUT OVER-
RIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12V ± 0.5V. By doing
this, protected boot block data can be altered through a
chip erase, or byte programming. When the RESET pin is
brought back to TTL levels, the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F080(T)
in the following ways: (a) VCC sense: if VCC is below 3.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F080(T) features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
3
Command Definition (in Hex)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
5555
5555
5555
5555
5555
XXXX
Data
DOUT
AA
Addr Data Addr Data Addr Data Addr Data Addr Data
Read
1
6
4
6
3
3
1
Chip Erase
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
5555
5555
5555
5555
5555
80
A0
80
90
F0
5555
Addr
5555
AA
DIN
AA
2AAA
2AAA
55
55
5555
5555
10
40
Byte Program
Boot Block Lockout(1)
Product ID Entry
Product ID Exit(2)
Product ID Exit(2)
AA
AA
AA
AA
F0
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F080 and FC000H to FFFFFH for the
AT49F080T.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
AT49F080(T)
4
AT49F080(T)
DC and AC Operating Range
AT49F080(T)-90
0°C - 70°C
AT49F080(T)-12
0°C - 70°C
AT49F080(T)-15
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
OE
VIL
VIH
WE
VIH
VIL
RESET
Ai
Ai
Ai
I/O
DOUT
DIN
RDY/BUSY
Read
VIH
VIH
VOH
VOL
Program(2)
Standby/Write
Inhibit
VIH
X(1)
X
VIH
X
High Z
VOH
Program Inhibit
Program Inhibit
Output Disable
RESET
X
X
X
X
X
VIL
VIH
X
VIH
X
VIH
VIH
VIH
VIL
VOH
VOH
VOH
X
High Z
High Z
X
X
Product Identification
VIL
VIL
VIH
VIH
A1 - A19 = VIL, A9 = VH,(3) A0 = VIL
A1 - A19 = VIL, A9 = VH,(3) A0 = VIH
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A19 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V
4. Manufacturer Code: 1FH
Device Code: 23H (AT49F080), 27H (AT49F080T)
5. See details under Software Product Identification Entry/Exit..
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
10
Com.
Ind.
100
300
3
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
ISB2
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
CE = 2.0V to VCC
(1)
ICC
f = 5 MHz; IOUT = 0 mA
50
VIL
0.8
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
V
VOL
VOH1
VOH2
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
V
Note:
1. ICC in the erase mode is 90 mA.
5
AC Read Characteristics
AT49F080(T)-90
AT49F080(T)-12
AT49F080(T)-15
Symbol
Parameter
Min
Max
90
Min
Max
120
120
50
Min
Max
150
150
70
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
90
ns
(2)
tOE
0
0
40
0
0
0
0
ns
(3)(4)
tDF
25
30
40
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
0
0
0
ns
AC Read Waveforms
ADDRESS
CE
ADDRESS VALID
tCE
tOE
OE
tDF
tOH
tACC
HIGHZ
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement level
Output Test Load
5.0V
3.0V
1.8K
1.3K
AC
AC
OUTPUT
PIN
DRIVING
1.5V
LEVELS
0.0V
MEASUREMENT
LEVEL
100 pF
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
Conditions
pF
pF
VIN = 0V
COUT
8
12
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AT49F080(T)
6
AT49F080(T)
AC Byte Load Characteristics
Symbol
Parameter
Min
0
Max
Units
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
tAH
tCS
tCH
tWP
tDS
50
0
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
0
90
50
0
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
tWPH
90
AC Byte Load Waveforms
WE Controlled
OE
ADDRESS
CE
t
t
t
OES
OEH
CH
t
t
t
AH
AS
CS
WE
t
t
WPH
t
DH
WP
t
DS
DATA IN
CE Controlled
OE
t
t
t
OES
OEH
CH
ADDRESS
WE
t
t
AH
AS
t
CS
CE
t
t
WPH
t
DH
WP
t
DS
DATA IN
7
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
50
tAS
0
ns
tAH
50
50
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
90
90
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
t
t
BP
WP
WPH
DH
WE
t
t
AS
AH
A0-A19
DATA
5555
2AAA
5555
ADDRESS
DS
INPUT
DATA
AA
55
A0
Chip Erase Cycle Waveforms
OE
CE
t
t
t
WP
WPH
WE
A0-A19
DATA
t
t
AS
AH
2AAA
DH
5555
5555
5555
2AAA
5555
t
t
EC
DS
AA
BYTE 0
55
BYTE 1
80
BYTE 2
AA
BYTE 3
55
BYTE 4
10
BYTE 5
Note:
OE must be high only when WE and CE are both low.
AT49F080(T)
8
AT49F080(T)
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
t
OEH
OE
t
t
t
WR
DH
OE
HIGH Z
An
I/O7
A0-A19
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
OE Hold Time
tOEH
tOE
tOEHP
tWR
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
t
t
OEH
OEHP
t
OE
t
t
WR
DH
OE
HIGH Z
I/O6
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
Software Product
Boot Block Lockout
Identification Entry(1)
Feature Enable Algorithm(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
LOAD DATA AA
TO
ADDRESS 5555
(2)(3)(5)
MODE
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product
Identification Exit(1)
LOAD DATA 40
TO
ADDRESS 5555
OR
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
EXIT PRODUCT
IDENTIFICATION
(2)
PAUSE 1 second
(4)
MODE
Notes: 1. Data Format: I/07 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
LOAD DATA F0
TO
2. Boot block lockout feature enabled.
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A19 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturers Code: 1FH
Device Code: 23H (AT49F080), 27H (AT49F080T)
AT49F080(T)
10
AT49F080(T)
AT49F080 Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
90
50
0.1
0.3
0.1
0.3
0.1
0.3
AT49F080-90CC
AT49F080-90RC
AT49F080-90TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
50
50
50
50
AT49F080-90CI
AT49F080-90RI
AT49F080-90TI
42C2
44R
40T
Industrial
(-40° to 85°C)
120
150
AT49F080-12CC
AT49F080-12RC
AT49F080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49F080-12CI
AT49F080-12RI
AT49F080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49F080-15CC
AT49F080-15RC
AT49F080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49F080-15TI
AT49F080-15TI
AT49F080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
(continued)
Package Type
42C2
44R
40T
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40-Lead, Thin Small Outline Package (TSOP)
11
AT49F080T Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
90
50
0.1
0.3
0.1
0.3
0.1
0.3
AT49F080T-90CC
AT49F080T-90RC
AT49F080T-90TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
50
50
50
50
AT49F080T-90CI
AT49F080T-90RI
AT49F080T-90TI
42C2
44R
40T
Industrial
(-40° to 85°C)
120
150
AT49F080T-12CC
AT49F080T-12RC
AT49F080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49F080T-12CI
AT49F080T-12RI
AT49F080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
AT49F080T-15CC
AT49F080T-15RC
AT49F080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
AT49F080T-15CI
AT49F080T-15RI
AT49F080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
42C2
44R
40T
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40-Lead, Thin Small Outline Package (TSOP)
AT49F080(T)
12
AT49F080(T)
Packaging Information
44R, 44-Lead, 0.525" Wide,
Plastic Gull Wing Small Outline (SOIC)
Dimensions in Inches and (Millimeters)
40T, 40-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches) *
*Controlling dimension: millimeters
42C2, 42-Ball, Plastic Chip-Size Ball Grid Array
Package (CBGA)
Dimensions in Millimeters and (Inches) *
8.2 (0.323)
7.8 (0.307)
14.2 (0.559)
13.8 (0.543)
0.30 (0.012)
1.40 (0.055) MAX
1.12 (0.044)
0.86 (0.034)
4.6 (0.181)
4.3 (0.169)
6.0 (0.236)
7
6
5
4
3
2
1
A
B
C
D
E
F
5.0 (0.197)
0.46 (0.018)
DIA BALL TYP
1.00 (0,039) BSC
NON-ACCUMULATIVE
13
AT49F080(T)
14
AT49F080(T)
15
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© Atmel Corporation 1998.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
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