AT49F4096-12RL [ATMEL]
Flash, 256KX16, 120ns, PDSO44, 0.525 INCH, PLASTIC, SOIC-44;
| 型号： | AT49F4096-12RL |
| 厂家： | 
ATMEL |
| 描述： | Flash, 256KX16, 120ns, PDSO44, 0.525 INCH, PLASTIC, SOIC-44 光电二极管 |
| 文件： | 总13页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time - 90 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Words (16K Bytes) Boot Block with Programming Lockout
– Two 8K Words (16K Bytes) Parameter Blocks
– One 232K Words (464K Bytes) Main Memory Array Block
• Fast Sector Erase Time - 10 seconds
• Word-By-Word Programming - 50 µs/Word
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low Power Dissipation
– 50 mA Active Current
– 300 µA CMOS Standby Current
• Typical 10,000 Write Cycles
4-Megabit
(256K x 16)
5-volt Only
Flash Memory
Description
The AT49F4096 is a 5-volt only, 4-megabit Flash Memory organized as 256K words of
16 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
device offers access times to 90 ns with power dissipation of just 275 mW. When
AT49F4096
Not Recommended
for New Design
Contact Atmel to discuss
the latest design in trends
and options
deselected, the CMOS standby current is less than 300 µA.
(continued)
Pin Configurations
Pin Name
A0 - A17
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
TSOP Top View
RESET
I/O0 - I/O15
NC
Type 1
Data Inputs/Outputs
No Connect
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
NC
3
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
SOIC (SOP)
4
5
NC
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
6
2
7
A17
A7
3
A8
A8
8
4
A9
NC
9
A6
5
A10
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A5
6
A11
WE
RESET
NC
A4
7
A12
A3
8
A13
A2
9
A14
NC
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
NC
A0
A16
NC
CE
NC
A17
A7
GND
OE
GND
I/O15
I/O7
1/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
A6
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
A5
A4
A3
GND
CE
A2
Rev. 0569F–12/98
A1
A0
To allow for simple in-system reprogrammability, the
AT49F4096 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM; it
has standard CE, OE, and WE inputs to avoid bus conten-
tion. Reprogramming the AT49F4096 is performed by first
erasing a block of data and then programming on a word-
by-word basis.
main memory array block. The AT49F4096 is programmed
on a word-by-word basis.
The device has the capability to protect the data in the boot
block; this feature is enabled by a command sequence.
Once the boot block programming lockout feature is
enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The typical
number of program and erase cycles is in excess of 10,000
cycles.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into three blocks for erase
operations. There are two 8K word parameter block sec-
tions and one sector consisting of the boot block and the
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
Block Diagram
Device Operation
READ: The AT49F4096 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin the boot block array can be repro-
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of the memory bits is a logical
AT49F4096
2
AT49F4096
“1”. The entire device can be erased at one time by using a
6-byte software code.
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
the whole chip is tEC
.
CHIP ERASE: If the boot block lockout has been enabled,
the Chip Erase function is disabled; sector erases for the
parameter blocks and main memory block will still operate.
After the full chip erase the device will return back to read
mode. Any command during chip erase will be ignored.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been enabled and the block cannot be pro-
grammed. The software product identification exit code
should be used to return to standard operation.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into three sectors that can be individu-
ally erased. There are two 8K word parameter block sec-
tions and one sector consisting of the boot block and the
main memory array block. The Sector Erase command is a
six bus cycle operation. The sector address is latched on
the falling WE edge of the sixth cycle while the 30H data
input command is latched at the rising edge of WE. The
sector erase starts after the rising edge of WE of the sixth
cycle. The erase operation is internally controlled; it will
automatically time to completion. When the boot block pro-
gramming lockout feature is not enabled, the boot block
and the main memory block will erase together (from the
same sector erase command). Once the boot region has
been protected, only the main memory array sector will
erase when its sector erase command is issued. Whenever
a parameter block is erased and reprogrammed, the other
parameter block should be erased and reprogrammed
before the first parameter block is erased again.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts. By doing this pro-
tected boot block data can be altered through a chip erase,
sector erase or word programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
WORD PROGRAMMING: Once a memory block is erased,
it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the internal device com-
mand register and is a 4 bus cycle operation. The device
will automatically generate the required internal program
pulses.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The DATA polling feature may
also be used to indicate the end of a program cycle.
DATA POLLING: The AT49F4096 features DATA polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all
outputs and the next cycle may begin. During a chip or sec-
tor erase operation, an attempt to read the device will give
a “0” on I/O7. Once the program or erase cycle has com-
pleted, true data will be read from the device. DATA polling
may begin at any time during the program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
TOGGLE BIT: In addition to DATA polling the AT49F4096
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
3
will be read. Examining the toggle bit may begin at any time
during a program cycle.
delay—once VCC has reached the VCC sense level, the
device will automatically time out 10 ms (typical) before
programming; (c) Program inhibit—holding any one of OE
low, CE high or WE high inhibits program cycles; and
(d) Noise filter—pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F4096 in
the following ways: (a) VCC sense—if VCC is below 3.8V
(typical), the program function is inhibited; (b) VCC power on
Command Definition (in Hex)(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
Addr
5555
Chip Erase
2AAA
2AAA
55
55
5555
5555
80
80
5555
5555
AA
AA
2AAA
2AAA
55
55
5555
10
30
Sector
Erase
6
4
6
3
3
1
5555
5555
5555
5555
5555
xxxx
AA
AA
AA
AA
AA
F0
SA(4)(5)
Word
Program
2AAA
2AAA
2AAA
2AAA
55
55
55
55
5555
5555
5555
5555
A0
80
90
F0
Addr
5555
DIN
AA
Boot Block
Lockout(2)
2AAA
55
5555
40
Product ID
Entry
Product ID
Exit(3)
Product ID
Exit(3)
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
2. The 8K word boot sector has the address range 00000H to 01FFFH.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 3FXXX for MAIN MEMORY ARRAY
5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase
together (from the same sector erase command). Once the boot region has been protected, only the main memory array
sector will erase when its sector erase command is issued.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
AT49F4096
4
AT49F4096
DC and AC Operating Range
AT49F4096-90
0°C - 70°C
AT49F4096-12
0°C - 70°C
Com.
Operating
Temperature (Case)
Ind.
-40°C - 85°C
5V ± 10%
-40°C - 85°C
5V ± 10%
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
RESET
VIH
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program/Erase(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Reset
VIH
VIH
High Z
VIH
X
VIH
X
VIL
VIH
X
VIH
X
X
VIH
High Z
High Z
X
X
VIL
X
Product Identification
A1 - A17 = VIL, A9 = VH,(3) A0 = VIL
A1 - A17 = VIL, A9 = VH,(3) A0 = VIH
A0 = VIL, A1 - A17 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A17 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 92H.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
10
10
300
3
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
VI/O = 0V to VCC
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
ISB2
(1)
ICC
50
0.8
VIL
Input Low Voltage
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
IOL = 2.1 mA
0.45
V
Output High Voltage
IOH = -400 µA
2.4
4.2
V
Output High Voltage CMOS
1. In the erase mode, ICC is 90 mA.
IOH = -100 µA; VCC = 4.5V
V
Note:
5
AC Read Characteristics
AT49F4096-90
AT49F4096-12
Symbol
Parameter
Min
Max
Min
Max
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
90
90
40
25
120
120
50
(1)
tCE
ns
(2)
tOE
0
0
0
0
ns
(3)(4)
tDF
30
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AT49F4096
6
AT49F4096
AC Word Load Characteristics
Symbol
Parameter
Min
10
50
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
50
10
90
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
ns
AC Word Load Waveforms
WE Controlled
CE Controlled
7
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
µs
tBP
Word Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
50
tAS
10
50
50
10
90
90
ns
tAH
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See
note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
AT49F4096
8
AT49F4096
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used by the address should not vary.
9
Software Product Identification Entry(1) Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA 55
TO
LOAD DATA AA
TO
OR
LOAD DATA F0
TO
ADDRESS 2AAA
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
LOAD DATA 55
TO
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ADDRESS 5555
ADDRESS 2AAA
PAUSE 1 second(2)
LOAD DATA F0
TO
ADDRESS 5555
Notes for boot block lockout feature enable:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex);
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
Notes for software product identification:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1FH. The Device Code is
92H.
6. Either one of the Product ID Exit commands can be
used.
AT49F4096
10
AT49F4096
Ordering Information(1)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
90
50
0.3
AT49F4096-90TC
AT49F4096-90RC
48T
44R
Commercial
(0° to 70°C)
50
50
50
0.3
0.3
0.3
AT49F4096-90TI
AT49F4096-90RI
48T
44R
Industrial
(-40° to 85°C)
120
AT49F4096-12TC
AT49F4096-12RC
48T
44R
Commercial
(0° to 70°C)
AT49F4096-12TI
AT49F4096-12RI
48T
44R
Industrial
(-40° to 85°C)
Note:
1. The AT49F4096 has an optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.
Package Type
48-Lead, Thin Small Outline Package (TSOP)
48T
44R
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC)
11
Packaging Information
44R, 44-Lead, 0.525" Wide,
48T, 48-Lead, Plastic Thin Small Outline Package
Plastic Gull Wing Small Outline (SOIC)
Dimensions in Inches and (Millimeters)
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 DD
*Controlling dimension: millimeters
AT49F4096
12
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Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
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TEL (408) 441-0311
FAX (408) 487-2600
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Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
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Zone Industrielle
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England
13106 Rousset Cedex, France
TEL (33) 4 42 53 60 00
FAX (33) 4 42 53 60 01
TEL (44) 1276-686677
FAX (44) 1276-686697
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Kowloon, Hong Kong
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FAX (852) 27221369
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© Atmel Corporation 1998.
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