AT49F4096AT-55RC [ATMEL]
4-Megabit 512K x 8/ 256K x 16 CMOS Flash Memory; 4兆位512K ×8 / 256K ×16的CMOS闪存
| 型号： | AT49F4096AT-55RC |
| 厂家： | 
ATMEL |
| 描述： | 4-Megabit 512K x 8/ 256K x 16 CMOS Flash Memory |
| 文件： | 总15页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Operation
– 5V Read
– 5V Programming
• Fast Read Access Time - 55 ns
• Internal Erase/Program Control
• Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 240K Words (480K bytes) Main Memory Array Block
• Fast Sector Erase Time - 10 seconds
• Byte-by-Byte or Word-By-Word Programming - 10 µs Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Low-Power Dissipation
– 50 mA Active Current
– 300 µA CMOS Standby Current
• Typical 10,000 Write Cycles
4-Megabit
(512K x 8/
256K x 16)
CMOS Flash
Memory
Description
The AT49F004(T) and AT49F4096A(T) are 5-volt, 4-megabit Flash Memories orga-
nized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 55 ns with power dissipation of just 275 mW. When deselected, the CMOS standby
current is less than 300 µA.
AT49F004
AT49F004T
AT49F4096A
AT49F4096AT
Preliminary
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49F004/4096A locates the boot block at lowest order
addresses (“bottom boot”); the AT49F004T/4096AT locates it at highest order
addresses (“top boot”).
To allow for simple in-system reprogrammability, the AT49F004(T)/4096A(T) does not
require high input voltages for programming. Reading data out of the device is similar
to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus con-
tention. Reprogramming the AT49F004(T)/4096A(T) is performed by first erasing a
(continued)
Pin Configurations
Pin Name
A0 - A18
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
RDY/BUSY
Ready/Busy Output
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
I/O15(A-1)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
BYTE
NC
Rev. 1167A–09/98
AT49F4096A(T) SOIC (SOP)
AT49F4096A(T) TSOP Top View
AT49F004(T) TSOP Top View
Type 1
Type 1
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A16
A15
A14
A13
A12
A11
A9
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
2
BYTE
GND
I/O15 / A-1
I/O7
2
2
3
A17
A7
3
A8
3
4
4
A9
5
4
NC
A6
5
A10
6
I/O14
I/O6
5
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
A5
6
A11
7
6
A4
7
A12
A8
8
I/O13
I/O5
7
A3
8
A13
NC
9
A8
8
A2
9
A14
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O12
I/O4
WE
9
WE
RESET
NC
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
RESET
NC
10
11
12
13
14
15
16
17
18
19
20
VCC
I/O11
I/O3
A0
A16
CE
BYTE
GND
I/O15/A-1
I/O7
NC
RDY/BUSY
A18
A7
GND
OE
NC
I/O10
I/O2
I/O3
I/O2
I/O1
I/O0
OE
NC
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
A17
A7
I/O9
A6
I/O14
I/O6
I/O1
A5
A6
I/O8
A4
A5
I/O0
I/O13
I/O5
A3
GND
CE
A4
OE
A2
A3
GND
CE
I/O12
I/O4
A2
A1
A0
A1
A0
VCC
block of data and then programming on a byte-by-byte or
word-by-word basis.
boot block cannot be changed when input levels of 5.5
volts or less are used. The boot sector is designed to con-
tain user secure code.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into four blocks for erase oper-
ations. There are two 4K word parameter block sections,
the boot block, and the main memory array block. The typi-
cal number of program and erase cycles is in excess of
10,000 cycles.
For the AT49F4096A(T), the BYTE pin controls whether
the device data I/O pins operate in the byte or word config-
uration. If the BYTE pin is set at a logic “1” or left open, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.
The 8K word boot block section includes a reprogramming
lock out feature to provide data integrity. This feature is
enabled by a command sequence. Once the boot block
programming lockout feature is enabled, the data in the
AT49F004(T)/4096A(T)
2
AT49F004(T)/4096A(T)
AT49F004(T) Block Diagram
AT49F004
AT49F004T
VCC
DATA INPUTS/OUTPUTS
I/O0 - I/O7
DATA INPUTS/OUTPUTS
I/O0 - I/O7
GND
OE
WE
CE
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
CONTROL
LOGIC
PROGRAM DATA
LATCHES
PROGRAM DATA
LATCHES
RESET
Y-GATING
Y-GATING
Y DECODER
X DECODER
7FFFF
7FFFF
ADDRESS
INPUTS
MAIN MEMORY
(480K BYTES)
BOOT BLOCK
16K BYTES
08000
07FFF
7C000
7BFFF
PARAMETER
BLOCK 2
8K BYTES
PARAMETER
BLOCK 1
8K BYTES
06000
05FFF
7A000
79FFF
PARAMETER
BLOCK 1
8K BYTES
PARAMETER
BLOCK 2
8K BYTES
04000
03FFF
78000
77FFF
BOOT BLOCK
16K BYTES
MAIN MEMORY
480K BYTES
00000
00000
AT49F4096A(T) Block Diagram
AT49F4096A
AT49F4096AT
VCC
DATA INPUTS/OUTPUTS
I/O0 - I/O15
DATA INPUTS/OUTPUTS
I/O0 - I/O15
GND
OE
WE
CE
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
CONTROL
LOGIC
PROGRAM DATA
LATCHES
PROGRAM DATA
LATCHES
RESET
Y-GATING
Y-GATING
Y DECODER
X DECODER
3FFFF
3FFFF
ADDRESS
INPUTS
MAIN MEMORY
(240K WORDS)
BOOT BLOCK
8K WORDS
04000
03FFF
3E000
3DFFF
PARAMETER
BLOCK 2
4K WORDS
PARAMETER
BLOCK 1
4K WORDS
03000
02FFF
3D000
3CFFF
PARAMETER
BLOCK 1
4K WORDS
PARAMETER
BLOCK 2
4K WORDS
02000
01FFF
3C000
3BFFF
BOOT BLOCK
8K WORDS
MAIN MEMORY
(240K WORDS)
00000
00000
Device Operation
READ: The AT49F004(T)/4096A(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
3
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin the boot block array can be repro-
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The DATA polling feature may
also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH for the AT49F004; 7C000H to 7FFFFH
for the AT49F004T; 00000H to 01FFFH for the
AT49F4096A; and 3E000H to 3FFFFH for the
AT49F4096AT.
ERASURE: Before a byte or word can be reprogrammed, it
must be erased. The erased state of memory bits is a logi-
cal “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.
CHIP ERASE: The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is tEC
.
If the boot block lockout has been enabled, the Chip Erase
will not erase the data in the boot block; it will erase the
main memory block and the parameter blocks only. After
the chip erase, the device will return to the read or standby
mode.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections,
one boot block, and the main memory array block. The
Sector Erase command is a six bus cycle operation. The
sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched at
the rising edge of WE. The sector erase starts after the ris-
ing edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and repro-
grammed, the two parameter blocks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and repro-
grammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and repro-
grammed, the main memory block and the parameter
blocks should be erased and reprogrammed before the
boot block is erased again.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from the fol-
lowing address location will show if programming the boot
block is locked out—00002H for AT49F004 and
AT49F4096A; 7C002 for the AT49F004T; and 3E002H for
the AT49F4096AT. If the data on I/O0 is low, the boot block
can be programmed; if the data on I/O0 is high, the pro-
gram lockout feature has been enabled and the block can-
not be programmed. The software product identification
exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts during the entire chip
erase, sector erase or word programming operation. When
the RESET pin is brought back to TTL levels the boot block
programming lockout feature is again active.
BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or word-by-word basis. Programming is accomplished via
the internal device command register and is a 4 bus cycle
operation. The device will automatically generate the
required internal program pulses.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
AT49F004(T)/4096A(T)
4
AT49F004(T)/4096A(T)
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
toggling and valid data will be read. Examining the toggle
bit may begin at any time during a program cycle.
READY/BUSY: For the AT49F004(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase opera-
tion. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the comple-
tion of the cycle. The open drain connection allows for OR-
tying of several devices to the same RDY/BUSY line.
DATA POLLING: The AT49F004(T)/4096A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49F004(T)/4096A(T) in the following ways: (a) VCC
sense: if VCC is below 3.8V (typical), the program function
is inhibited. (b) VCC power on delay: once VCC has reached
the VCC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
TOGGLE BIT: In addition to DATA polling the
AT49F004(T)/4096A(T) provides another method for deter-
mining the end of a program or erase cycle. During a pro-
gram or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop
5
Command Definition (in Hex)(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles Addr Data
Addr
Data Addr Data Addr Data
Addr
Data Addr Data
Read
1
6
6
4
6
3
3
1
Addr
5555
5555
5555
5555
5555
5555
xxxx
DOUT
AA
AA
AA
AA
AA
AA
F0
Chip Erase
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
55
5555
5555
5555
5555
5555
5555
80
80
A0
80
90
F0
5555
5555
Addr
5555
AA
AA
DIN
AA
2AAA
2AAA
55
55
5555
SA(4)
10
30
Sector Erase
Byte/Word Program
Boot Block Lockout(2)
Product ID Entry
Product ID Exit(3)
Product ID Exit(3)
2AAA
55
5555
40
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care)
2. The boot sector has the address range 00000H to 03FFFH for the AT49F004; 7C000H to 7FFFFH for the AT49F004T;
00000H to 01FFFH for the AT49F4096A; and 3E000H to 3FFFFH for the AT49F4096AT.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: (A18 - A0)
For the AT49F004
SA = sector addresses: (A17 - A0)
For the AT49F4096A
SA = 03XXX for BOOT BLOCK
SA = 01XXX for BOOT BLOCK
SA = 05XXX for PARAMETER BLOCK 1
SA = 07XXX for PARAMETER BLOCK 2
SA = 7FXXX for MAIN MEMORY ARRAY
SA = 02XXX for PARAMETER BLOCK 1
SA = 03XXX for PARAMETER BLOCK 2
SA = 3FXXX for MAIN MEMORY ARRAY
For the AT49F004(T)
For the AT49F4096AT
SA = 7FXXX for BOOT BLOCK
SA = 3FXXX for BOOT BLOCK
SA = 7BXXX for PARAMETER BLOCK 1
SA = 79XXX for PARAMETER BLOCK 2
SA = 77XXX for MAIN MEMORY ARRAY
SA = 3DXXX for PARAMETER BLOCK 1
SA = 3CXXX for PARAMETER BLOCK 2
SA = 3BXXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on RESET
with Respect to Ground...................................-0.6V to +13.5V
AT49F004(T)/4096A(T)
6
AT49F004(T)/4096A(T)
DC and AC Operating Range
AT49F004(T)/4096A(T)-55
AT49F004(T)/4096A(T)-70
AT49F004(T)/4096A(T)-90
0°C - 70°C
Com.
Ind.
0°C - 70°C
N/A
0°C - 70°C
-40°C - 85°C
5V ± 10%
Operating
Temperature (Case)
-40°C - 85°C
VCC Power Supply
5V ± 10%
5V ± 10%
Operating Modes
Mode
CE
VIL
VIL
OE
VIL
VIH
WE
RESET
VIH
Ai
I/O
Read
VIH
VIL
Ai
Ai
DOUT
DIN
Program/Erase(2)
VIH
Standby/Program
Inhibit
VIH
X(1)
X
VIH
X
High Z
Program Inhibit
Program Inhibit
Output Disable
Reset
X
X
X
X
X
VIL
VIH
X
VIH
X
VIH
VIH
VIH
VIL
X
High Z
High Z
X
X
Product Identification
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIH
A0 = VIL, A1 - A18 = VIL
A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
VIH
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 161FH
Device Code: 11H (AT49F004), 1692H (AT49F4096A), 10H (AT49F004T), 1690H (AT49F4096AT).
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
VIN = 0V to VCC
ILO
VI/O = 0V to VCC
10
ISB1
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA
300
3
ISB2
(1)
ICC
50
VIL
0.8
VIH
VOL
VOH
Input High Voltage
2.0
2.4
V
Output Low Voltage
IOL = 2.1 mA
0.45
V
Output High Voltage
IOH = -400 µA
V
Note:
1. In the erase mode, ICC is 90 mA.
7
AC Read Characteristics
AT49F004(T)/4096A(T)-55
AT49F004(T)/4096A(T)-70
AT49F004(T)/4096A(T)-90
Symbol
Parameter
Min
Max
55
Min
Max
70
Min
Max
90
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
55
70
90
ns
(2)
tOE
0
0
30
0
0
35
0
0
40
ns
(3)(4)
tDF
25
25
25
ns
Output Hold from OE,CE or Address,
whichever occurred first
tOH
tRO
0
0
0
ns
ns
RESET to Output Delay
800
800
800
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
OE
t
CE
t
OE
t
DF
t
t
OH
ACC
t
RO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
3.0V
55/70 ns
90 ns
5.0V
5.0V
0.0V
tR, tF < 5 ns
30
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
CIN
COUT
Note:
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49F004(T)/4096A(T)
8
AT49F004(T)/4096A(T)
AC Word Load Characteristics
Symbol Parameter
Min
10
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
100
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
100
100
10
ns
ns
t
DH, tOEH Data, OE Hold Time
ns
tWPH
Write Pulse Width High
50
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
9
Program Cycle Characteristics
Symbol Parameter
Min
Typ
Max
Units
µs
tBP
Byte/Word Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
10
50
tAS
0
ns
tAH
tDS
tDH
tWP
tWPH
tEC
100
100
0
ns
ns
Data Hold Time
ns
Write Pulse Width
100
50
ns
Write Pulse Width High
Erase Cycle Time
ns
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
WP
WPH
BP
WE
t
t
t
DH
AH
AS
A0-A18
DATA
5555
5555
5555
2AAA
ADDRESS
t
DS
55
A0
INPUT DATA
AA
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
A0-A18
DATA
t
t
t
AS
DH
AH
Note 2
5555
5555
5555
2AAA
2AAA
t
t
EC
DS
Note 3
55
80
55
AA
AA
BYTE/
WORD 0
BYTE/
BYTE/
BYTE/
BYTE/
BYTE/
WORD 1
WORD 2
WORD 3
WORD 4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
AT49F004(T)/4096A(T)
10
AT49F004(T)/4096A(T)
Data Polling Characteristics(1)
Symbol Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tWR
tOE
HIGH Z
An
I/O7
A0-A18
An
An
An
An
Toggle Bit Characteristics(1)
Symbol Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
Software Product Identification Entry(1) Boot Block
Lockout Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA AA
TO
ENTER PRODUCT
IDENTIFICATION
ADDRESS 5555
(2)(3)(5)
MODE
Software Product Identification Exit(1)(6)
LOAD DATA 55
TO
OR
LOAD DATA AA
TO
LOAD DATA F0
TO
ADDRESS 2AAA
ADDRESS 5555
ANY ADDRESS
LOAD DATA 40
TO
EXIT PRODUCT
IDENTIFICATION
LOAD DATA 55
TO
ADDRESS 5555
(4)
MODE
ADDRESS 2AAA
(2)
PAUSE 1 second
LOAD DATA F0
TO
ADDRESS 5555
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex), A-1, and A15 - A18
(Don’t Care).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex), A-1, and A15 - A18
(Don’t Care).
2. A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH
.
3. The device does not remain in identification mode if pow-
ered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 161FH
Device Code: 11H (AT49F004), 1692H (AT49F4096A),
1692H (AT49F004T), 1690H (AT49F4096AT)
6. Either one of the Product ID Exit commands can be used.
AT49F004(T)/4096A(T)
12
AT49F004(T)/4096A(T)
AT49F004(T) Ordering Information
I
CC (mA)
tACC
(ns)
Standby
Active
Ordering Code
Package
Operation Range
55
50
0.3
AT49F004-55TC
40T
Commercial
(0° to 70°C)
70
50
50
0.3
0.3
AT49F004-70TC
AT49F004-70TI
AT49F004-90TC
AT49F004-90TI
AT49F004T-55TC
AT49F004T-70TC
AT49F004T-70TI
AT49F004T-90TC
AT49F004T-90TI
40T
40T
40T
40T
40T
40T
40T
40T
40T
Commercial
(0° to 70°C)
Industrial
(-40° to 85°C)
90
Commercial
(0° to 70°C)
Industrial
(-40° to 85°C)
55
70
50
50
0.3
0.3
Commercial
(0° to 70°C)
Commercial
(0° to 70°C)
Industrial
(-40° to 85°C)
90
50
0.3
Commercial
(0° to 70°C)
Industrial
(-40° to 85°C)
Package Type
40-Lead, Plastic Thin Small Outline Package (TSOP)
40T
13
AT49F4096A(T) Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
55
50
0.3
AT49F4096A-55RC
AT49F4096A-55TC
44R
48T
Commercial
(0° to 70°C)
70
50
50
0.3
0.3
AT49F4096A-70RC
AT49F4096A-70TC
44R
48T
Commercial
(0° to 70°C)
AT49F4096A-70RI
AT49F4096A-70TI
44R
48T
Industrial
(-40° to 85°C)
90
AT49F4096A-90RC
AT49F4096A-90TC
44R
48T
Commercial
(0° to 70°C)
AT49F4096A-90RI
AT49F4096A-90TI
44R
48T
Industrial
(-40° to 85°C)
55
70
50
50
0.3
0.3
AT49F4096AT-55RC
AT49F4096AT-55TC
44R
48T
Commercial
(0° to 70°C)
AT49F4096AT-70RC
AT49F4096AT-70TC
44R
48T
Commercial
(0° to 70°C)
AT49F4096AT-70RI
AT49F4096AT-70TI
44R
48T
Industrial
(-40° to 85°C)
90
50
0.3
AT49F4096AT-90RC
AT49F4096AT-90TC
44R
48T
Commercial
(0° to 70°C)
AT49F4096AT-90RI
AT49F4096AT-90TI
44R
48T
Industrial
(-40° to 85°C)
Package Type
44R
48T
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline (SOIC)
48-Lead, Plastic Thin Small Outline Package (TSOP)
AT49F004(T)/4096A(T)
14
AT49F004(T)/4096A(T)
Packaging Information
44R, 44-Lead, 0.525" Wide, Plastic Gull Wing Small
Outline (SOIC)
40T, 40-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Inches and (Millimeters)
Dimensions in Inches and (Millimeters)
*Controlling dimension: millimeters
48T, 48-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 D
*Controlling dimension: millimeters
15
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