AT49F516-55VJ [ATMEL]
Flash, 32KX16, 55ns, PDSO40, 10 X 14 MM, PLASTIC, MO-142CA, TSOP-40;
| 型号： | AT49F516-55VJ |
| 厂家： | 
ATMEL |
| 描述： | Flash, 32KX16, 55ns, PDSO40, 10 X 14 MM, PLASTIC, MO-142CA, TSOP-40 ATM 异步传输模式 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Operation
– 5V Read
– 5V Reprogramming
• Fast Read Access Time - 55 ns
• Internal Program Control and Timer
• 8K Word Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Word-By-Word Programming - 10 µs/Word Typical
• Hardware Data Protection
• DATA Polling For End Of Program Detection
• Small 10 x 14 VSOP Package
• Typical 10,000 Write Cycles
512K (32K x 16)
5-volt Only
Description
Flash Memory
The AT49F516 is a 5-volt only in-system programmable and erasable Flash Memory.
It’s 512K of memory is organized as 32,768 words by 16 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55
ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA.
AT49F516
Not Recommended
for New Design
Contact Atmel to discuss
the latest design in trends
and options
(continued)
Pin Configurations
VSOP Top View
Type 1
10 x 14 mm
Pin Name
A0 - A14
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
A0
A1
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
2
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/07
OE
A2
3
A3
4
WE
A4
5
A5
6
I/O0 - I/O15 Data Inputs/Outputs
A6
7
NC
No Connect
A7
8
A8
9
GND
A9
10
11
12
13
14
15
16
17
18
19
20
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
NC
10 x 14 mm
A10
A11
A12
A13
A14
NC
NC
WE
VCC
PLCC Top View
I/O12
I/O11
I/O10
7
8
9
39 A13
38 A12
37 A11
36 A10
35 A9
34 GND
33 NC
32 A8
31 A7
30 A6
29 A5
CE
I/O9 10
I/O8 11
GND 12
NC 13
I/O7 14
I/O6 15
I/O5 16
I/O4 17
Rev. 1089B–10/98
To allow for simple in-system reprogrammability, the
AT49F516 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F516 is performed by erasing a
block of data (entire chip or main memory block) and then
programming on a word by word basis. The typical word
programming time is a fast 10 µs. The end of a program
cycle can be optionally detected by the DATA polling fea-
ture. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.
The optional 8K words boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being erased or reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS
I/O15 - I/O0
VCC
GND
16
OE
DATA LATCH
OE, CE, AND WE
WE
LOGIC
INPUT/OUTPUT
BUFFERS
CE
Y DECODER
ADDRESS
Y-GATING
7FFFH
MAIN MEMORY
INPUTS
X DECODER
(24K WORDS)
2000H
1FFFH
OPTIONAL BOOT
BLOCK (8K WORDS)
0000H
Device Operation
READ: The AT49F516 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
cycle waveforms. The Main Memory Erase operation is
internally controlled; it will automatically time to completion.
WORD PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
CHIP ERASE: When the boot block programming lockout
feature is not enabled, the boot block and the main memory
block will erase together from the same chip erase com-
mand (See command definitions table). If the boot block
lockout function has been enabled, data in the boot section
will not be erased. However, data in the main memory sec-
tion will be erased. After a chip erase, the device will return
to the read mode.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
MAIN MEMORY ERASE: As an alternative to the chip
erase, a main memory block erase can be performed which
will erase all bytes not located in the boot block region to an
FFH. Data located in the boot region will not be changed
during a main memory block erase. The Main Memory
Erase command is a six bus cycle operation. The address
(5555H) is latched on the falling edge of the sixth cycle
while the 30H data input is latched on the rising edge of
WE. The main memory erase starts after the rising edge of
WE of the sixth cycle. Please see Main Memory Erase
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
AT49F516
2
AT49F516
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method and can be erased using either the chip
erase or the main memory block erase command. To acti-
vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
Please refer to the Command Definitions table.
DATA POLLING: The AT49F516 features DATA polling to
indicate the end of a program or erase cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 0002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.
TOGGLE BIT: In addition to DATA polling the AT49F516
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F516 in
the following ways: (a) VCC sense: if VCC is below 3.8V (typ-
ical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Noise filter: Pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
3
Command Definition (in Hex)(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles Addr Data
Addr
Data Addr Data Addr Data
Addr
Data Addr Data
Read
1
6
6
4
6
3
3
1
Addr DOUT
Chip Erase
5555
5555
5555
5555
5555
5555
xxxx
AA
AA
AA
AA
AA
AA
F0
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
55
5555
5555
5555
5555
5555
5555
80
80
A0
80
90
F0
5555
5555
Addr
5555
AA
AA
DIN
AA
2AAA
2AAA
55
55
5555
5555
10
30
Main Memory Erase
Word Program
Boot Block Lockout(2)
Product ID Entry
Product ID Exit(3)
Product ID Exit(3)
2AAA
55
5555
40
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
2. The 8K word boot sector has the address range 00000H to 1FFFH.
3. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
AT49F516
4
AT49F516
DC and AC Operating Range
AT49F516-55
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT49F516-70
0°C - 70°C
-40°C - 85°C
5V ± 10%
AT49F516-90
Com.
0°C - 70°C
-40°C - 85°C
5V ± 10%
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
High Z
VIH
X
X
VIL
VIH
X
X
High Z
A1 - A14 = VIL, A9 = VH,(3), A0 = VIL
A1 - A14 = VIL, A9 = VH,(3), A0 = VIH
A0 = VIL, A1 - A14 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A14 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 100001XX (binary).
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
µA
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
10
Com.
Ind.
100
300
3
ISB1
ISB2
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
VCC Standby Current TTL
VCC Active Current
CE = 2.0V to VCC
(1)
ICC
f = 5 MHz; IOUT = 0 mA
50
VIL
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
V
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
IOL = 2.1 mA
0.45
V
IOH = -400 µA
2.4
4.2
V
IOH = -100 µA; VCC = 4.5V
V
Note:
1. In the erase mode, ICC is 90 mA.
5
AC Read Characteristics
AT49F516-55
Min Max
AT49F516-70
Min Max
AT49F516-90
Min Max
Symbol
Parameter
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
55
55
30
25
70
70
35
25
90
90
40
25
(1)
tCE
ns
(2)
tOE
0
0
ns
(3)(4)
tDF
0
0
0
0
ns
Output Hold from OE, CE
or Address, whichever
occurred first
tOH
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
55/70 ns
90 ns
5.0V
5.0V
1.8K
1.3K
1.8K
1.3K
OUTPUT
OUTPUT
PIN
PIN
30 pF
100 pF
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
AT49F516
6
AT49F516
AC Word Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Set-up Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
50
0
ns
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
0
ns
90
50
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
90
ns
AC Word Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
CE
tAS
tAH
tCH
tCS
WE
tWPH
tWP
tDH
tDS
DATA IN
CE Controlled
OE
tOES
tOEH
ADDRESS
WE
tAS
tAH
tCH
tCS
CE
tWPH
tWP
tDH
tDS
DATA IN
7
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Word Programming Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
50
tAS
0
ns
tAH
50
50
0
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Write Pulse Width High
Erase Cycle Time
90
90
ns
tWPH
tEC
ns
10
seconds
Program Cycle Waveforms
A0-A14
Main Memory or Chip Erase Cycle Waveforms
OE
CE
t
t
WP
WPH
WE
A0-A14
DATA
t
t
t
DH
AS
AH
5555
5555
5555
5555
2AAA
2AAA
t
t
EC
DS
55
WORD 1
80
WORD 2
55
NOTE 2
AA
WORD 0
AA
WORD 3
WORD 4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 10H. For a main memory erase the data should be 30H.
AT49F516
8
AT49F516
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
A0-A14
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
Software Product
Boot Block
Identification Entry(1)
Lockout Enable Algorithm(1)
LOAD DATA AA
LOAD DATA AA
TO
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 80
TO
LOAD DATA 90
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA AA
TO
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
ADDRESS 5555
LOAD DATA 55
TO
Software Product
Identification Exit(1)
ADDRESS 2AAA
OR
LOAD DATA AA
LOAD DATA F0
TO
LOAD DATA 40
TO
TO
ADDRESS 5555
ANY ADDRESS
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA 55
TO
PAUSE 1 second(2)
ADDRESS 2AAA
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex); Address Format: A14 - A0 (Hex).
LOAD DATA F0
TO
ADDRESS 5555
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0
(Hex); Address Format: A14 - A0 (Hex).
2. A1 - A14 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 100001XX (binary)
AT49F516
10
AT49F516
Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
55
70
90
50
0.1
AT49F516-55JC
AT49F516-55VC
44J
Commercial
40V
(0° to 70°C)
50
50
50
50
50
0.3
0.1
0.3
0.1
0.3
AT49F516-55JI
AT49F516-55VI
44J
Industrial
40V
(-40° to 85°C)
AT49F516-70JC
AT49F516-70VC
44J
Commercial
40V
(0° to 70°C)
AT49F516-70JI
AT49F516-70VI
44J
Industrial
40V
(-40° to 85°C)
AT49F516-90JC
AT49F516-90VC
44J
Commercial
40V
(0° to 70°C)
AT49F516-90JI
AT49F516-90VI
44J
Industrial
40V
(-40° to 85°C)
Note:
1. The AT49F516 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.
Package Type
44-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
40-Lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm)
44J
40V
11
Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
40V, 40-Lead, Plastic Thin Small Outline
Package (TSOP)
Dimensions in Millimeters and (Inches)*
.045(1.14) X 30° - 45°
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
.650(16.5)
SQ
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
*Controlling dimension: millimeters
AT49F516
12
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Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
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TEL (719) 576-3300
FAX (719) 540-1759
Europe
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England
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TEL (33) 4 42 53 60 00
FAX (33) 4 42 53 60 01
TEL (44) 1276-686677
FAX (44) 1276-686697
Asia
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Kowloon, Hong Kong
TEL (852) 27219778
FAX (852) 27221369
Japan
Atmel Japan K.K.
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1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1998.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
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any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
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not authorized for use as critical components in life support devices or systems.
®
™
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Printed on recycled paper.
1089B–10/98/xM
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