AT49SV322DT-80TU_技术文档

Features

•

Single Voltage Read/Write Operation: 1.65V to 1.95V

Access Time – 80 ns

Sector Erase Architecture

– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout

– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

Fast Word Program Time – 10 µs

•

Fast Sector Erase Time – 100 ms

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase

of a Different Sector

32-megabit

(2M x 16)

1.8-volt Only

Flash Memory

– Supports Reading Any Word in the Non-suspending Sectors by Suspending

Programming of Any Other Word

•

Low-power Operation

– 10 mA Active

– 15 µA Standby

•

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Write Protection and Accelerated Program Operation

RESET Input for Device Initialization

AT49SV322D

AT49SV322DT

Sector Lockdown Support

TSOP and CBGA Package Options

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

Minimum 100,000 Erase Cycles

Common Flash Interface (CFI)

1. Description

The AT49SV322D(T) is a 1.8-volt 32-megabit Flash memory organized as 2,097,152

words of 16 bits each. The memory is divided into 71 sectors for erase operations.

The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device

has CE and OE control signals to avoid any bus contention. This device can be read

or reprogrammed using a single power supply, making it ideally suited for in-system

programming.

The device powers on in the read mode. Command sequences are used to place the

device in other operation modes such as program and erase. The device has the

capability to protect the data in any sector (see “Sector Lockdown” on page 6).

To increase the flexibility of the device, it contains an Erase Suspend and Program

Suspend feature. This feature will put the erase or program on hold for any amount of

time and let the user read data from or program data to any of the remaining sectors

within the memory. The end of a program or an erase cycle is detected by the

READY/BUSY pin, Data Polling or by the toggle bit.

The VPP pin provides data protection. When the V_PPinput is below 0.4V, the program

and erase functions are inhibited. When V_PPis at 1.65V or above, normal program

and erase operations can be performed. With V_PPat 10.0V, the program (Dual-word

Program command) operation is accelerated.

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A six-word command (Enter Single Pulse Program Mode) sequence to remove the require-

ment of entering the three-word program sequence is offered to further improve programming

time. After entering the six-word code, only single pulses on the write control lines are required

for writing into the device. This mode (Single Pulse Word Program) is exited by powering

down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing

it back to V_CC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will

not work while in this mode; if entered they will result in data being programmed into the

device. It is not recommended that the six-word code reside in the software of the final product

but only exist in external programming code.

2. Pin Configurations

Pin Name

Function

A0 - A20

CE

Addresses

Chip Enable

OE

Output Enable

Write Enable

Reset

WE

RESET

RDY/BUSY

VPP

READY/BUSY Output

Write Protection

Data Inputs/Outputs

No Connect

I/O0 - I/O15

NC

2.1

TSOP Top View (Type 1)

2.2

CBGA Top View (Ball Down)

1

2

3

4

5

6

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

2

VCC

GND

I/O15

3

4

A

5

I/O7

6

I/O14

A3

A7 RDY/BUSY WE

A9

A13

A12

A14

A15

A16

NC

7

I/O6

B

A8

8

I/O13

I/O5

A4

A2

A17

A6

VPP

A18

RST

NC

A8

A19

A20

WE

9

C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

I/O12

I/O4

A10

A11

I/O7

RESET

NC

VCC

D

I/O11

A1

A5

A20

A19

I/O5

VPP

RDY/BUSY

A18

A17

A7

I/O3

E

I/O10

I/O2

A0

I/O0

I/O8

I/O9

I/O1

I/O2

I/O10

I/O11

I/O3

F

I/O9

I/O1

CE

OE

VSS

I/O12 I/O14

A6

I/O8

G

A5

I/O0

OE

VCC

I/O4

I/O13 I/015

A4

H

A3

GND

A2

CE

A0

I/O6

VSS

A1

2

AT49SV322D(T)

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AT49SV322D(T)

3. Block Diagram

I/O0 - I/O15

OUTPUT

BUFFER

INPUT

BUFFER

IDENTIFIER

REGISTER

INPUT

A0 - A20

BUFFER

STATUS

CE

REGISTER

WE

COMMAND

OE

REGISTER

RESET

ADDRESS

LATCH

DATA

RDY/BUSY

COMPARATOR

WRITE STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

VPP

Y-DECODER

X-DECODER

Y-GATING

VCC

GND

MAIN

MEMORY

4. Device Operation

4.1

Command Sequences

When the device is first powered on, it will be reset to the read or standby mode, depending

upon the state of the control line inputs. In order to perform other device functions, a series of

command sequences are entered into the device. The command sequences are shown in the

“Command Definition Table” on page 12 (I/O8 - I/O15 are don’t care inputs for the command

codes). The command sequences are written by applying a low pulse on the WE or CE input

with CE or WE low (respectively) and OE high. The address is latched on the falling edge of

CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.

Standard microprocessor write timings are used. The address locations used in the command

sequences are not affected by entering the command sequences.

4.2

Read

The AT49SV322D(T) is accessed like an EPROM. When CE and OE are low and WE is high,

the data stored at the memory location determined by the address pins are asserted on the

outputs. The outputs are put in the high impedance state whenever CE or OE is high. This

dual-line control gives designers flexibility in preventing bus contention.

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4.3

Reset

Erase

A RESET input pin is provided to ease some system applications. When RESET is at a logic

high level, the device is in its standard operating mode. A low level on the RESET input halts

the present device operation and puts the outputs of the device in a high impedance state.

When a high level is reasserted on the RESET pin, the device returns to the read or standby

mode, depending upon the state of the control inputs.

4.4

Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a

logical “1”. The entire device can be erased by using the Chip Erase command or individual

sectors can be erased by using the Sector Erase command.

4.4.1

Chip Erase

The entire device can be erased at one time by using the six-word chip erase software code.

After the chip erase has been initiated, the device will internally time the erase operation so

that no external clocks are required. The maximum time to erase the chip is t_EC

.

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

4.4.2

Sector Erase

As an alternative to a full chip erase, the device is organized into 71 sectors (SA0 - SA70) that

can be individually erased. The Sector Erase command is a six-bus cycle operation. The sec-

tor address is latched on the falling WE edge of the sixth cycle while the 30H data input

command is latched on the rising edge of WE. The sector erase starts after the rising edge of

WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to

completion. The maximum time to erase a sector is t_SEC. When the sector programming lock-

down feature is not enabled, the sector will erase (from the same Sector Erase command). An

attempt to erase a sector that has been protected will result in the operation terminating

immediately.

4.5

Word Programming

Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis.

Programming is accomplished via the internal device command register and is a four-bus

cycle operation. The device will automatically generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t_BPcycle

time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the

erase or program operation was performed successfully.

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AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

4.6

4.7

VPP Pin

The circuitry of the AT49SV322D(T) is designed so that the device cannot be programmed or

erased if the V_PPvoltage is less that 0.4V. When V_PPis at 1.65V or above, normal program

and erase operations can be performed. The VPP pin cannot be left floating.

Program/Erase Status

The device provides several bits to determine the status of a program or erase operation: I/O2,

I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11 and the following four sections

describe the function of these bits. To provide greater flexibility for system designers, the

AT49SV322D(T) contains a programmable configuration register. The configuration register

allows the user to specify the status bit operation. The configuration register can be set to one

of two different values, “00” or “01”. If the configuration register is set to “00”, the part will auto-

matically return to the read mode after a successful program or erase operation. If the

configuration register is set to a “01”, a Product ID Exit command must be given after a suc-

cessful program or erase operation before the part will return to the read mode. It is important

to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful

program or erase operation requires using the Product ID Exit command to return the device

to read mode. The default value (after power-up) for the configuration register is “00”. Using

the four-bus cycle Set Configuration Register command as shown in the “Command Definition

Table” on page 12, the value of the configuration register can be changed. Voltages applied to

the RESET pin will not alter the value of the configuration register. The value of the configura-

tion register will affect the operation of the I/O7 status bit as described below.

4.7.1

Data Polling

The AT49SV322D(T) features Data Polling to indicate the end of a program cycle. If the status

configuration register is set to a “00”, during a program cycle an attempted read of the last

word loaded will result in the complement of the loaded data on I/O7. Once the program cycle

has been completed, true data is valid on all outputs and the next cycle may begin. During a

chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the

program or erase cycle has completed, true data will be read from the device. Data Polling

may begin at any time during the program cycle. Please see “Status Bit Table” on page 11 for

more details.

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the

device is actively programming or erasing data. I/O7 will go high when the device has com-

pleted a program or erase operation. Once I/O7 has gone high, status information on the other

pins can be checked.

The Data Polling status bit must be used in conjunction with the erase/program and V_PPstatus

bit as shown in the algorithm in Figures 4-1 and 4-2 on page 9.

4.7.2

Toggle Bit

In addition to Data Polling the AT49SV322D(T) provides another method for determining the

end of a program or erase cycle. During a program or erase operation, successive attempts to

read data from the memory will result in I/O6 toggling between one and zero. Once the pro-

gram cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the

toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on

page 11 for more details.

The toggle bit status bit should be used in conjunction with the erase/program and V_PPstatus

bit as shown in the algorithm in Figures 4-3 and 4-4 on page 10.

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4.7.3

Erase/Program Status Bit

The device offers a status bit on I/O5, which indicates whether the program or erase operation

has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is

unable to verify that an erase or a word program operation has been successfully performed. If

a program (Sector Erase) command is issued to a protected sector, the protected sector will

not be programmed (erased). The device will go to a status read mode and the I/O5 status bit

will be set high, indicating the program (erase) operation did not complete as requested. Once

the erase/program status bit has been set to a “1”, the system must write the Product ID Exit

command to return to the read mode. The erase/program status bit is a “0” while the erase or

program operation is still in progress. Please see “Status Bit Table” on page 11 for more

details.

4.7.4

VPP Status Bit

The AT49SV322D(T) provides a status bit on I/O3, which provides information regarding the

voltage level of the VPP pin. During a program or erase operation, if the voltage on the VPP

pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be

a “1”. Once the V_PPstatus bit has been set to a “1”, the system must write the Product ID Exit

command to return to the read mode. On the other hand, if the voltage level is high enough to

perform a program or erase operation successfully, the V_PPstatus bit will output a “0”. Please

see “Status Bit Table” on page 11 for more details.

4.8

Sector Lockdown

Each sector has a programming lockdown feature. This feature prevents programming of data

in the designated sectors once the feature has been enabled. These sectors can contain

secure code that is used to bring up the system. Enabling the lockdown feature will allow the

boot code to stay in the device while data in the rest of the device is updated. This feature

does not have to be activated; any sector’s usage as a write-protected region is optional to the

user.

At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,

the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked

down, the contents of the sector is read-only and cannot be erased or programmed.

4.8.1

Sector Lockdown Detection

A software method is available to determine if programming of a sector is locked down. When

the device is in the software product identification mode (see “Software Product Identification

Entry/Exit” sections on page 25), a read from address location 00002H within a sector will

show if programming the sector is locked down. If the data on I/O0 is low, the sector can be

programmed; if the data on I/O0 is high, the program lockdown feature has been enabled and

the sector cannot be programmed. The software product identification exit code should be

used to return to standard operation.

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AT49SV322D(T)

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AT49SV322D(T)

4.8.2

Sector Lockdown Override

The only way to unlock a sector that is locked down is through reset or power-up cycles. After

power-up or reset, the content of a sector that is locked down can be erased and

reprogrammed.

4.9

Erase Suspend/Erase Resume

The Erase Suspend command allows the system to interrupt a sector or chip erase operation

and then program or read data from a different sector within the memory. After the Erase Sus-

pend command is given, the device requires a maximum time of 15 µs to suspend the erase

operation. After the erase operation has been suspended, the system can then read data or

program data to any other sector within the device. An address is not required during the

Erase Suspend command. During a sector erase suspend, another sector cannot be erased.

To resume the sector erase operation, the system must write the Erase Resume command.

The Erase Resume command is a one-bus cycle command. The device also supports an

erase suspend during a complete chip erase. While the chip erase is suspended, the user can

read from any sector within the memory that is protected. The command sequence for a chip

erase suspend and a sector erase suspend are the same.

4.10 Program Suspend/Program Resume

The Program Suspend command allows the system to interrupt a programming operation and

then read data from a different word within the memory. After the Program Suspend command

is given, the device requires a maximum of 10 µs to suspend the programming operation. After

the programming operation has been suspended, the system can then read data from any

other word that is not contained in the sector in which the programming operation was sus-

pended. An address is not required during the program suspend operation. To resume the

programming operation, the system must write the Program Resume command. The program

suspend and resume are one-bus cycle commands. The command sequence for the erase

suspend and program suspend are the same, and the command sequence for the erase

resume and program resume are the same.

4.11 Product Identification

The product identification mode identifies the device and manufacturer as Atmel^®. It is

accessed using a software operation.

For details, see “Operating Modes” on page 18 or “Software Product Identification Entry/Exit”

sections on page 25.

4.12 128-bit Protection Register

The AT49SV322D(T) contains a 128-bit register that can be used for security purposes in sys-

tem design. The protection register is divided into two 64-bit blocks. The two blocks are

designated as block A and block B. The data in block A is non-changeable and is programmed

at the factory with a unique number. The data in block B is programmed by the user and can

be locked out such that data in the block cannot be reprogrammed. To program block B in the

protection register, the four-bus cycle Program Protection Register command must be used as

shown in the “Command Definition Table” on page 12. To lock out block B, the four-bus cycle

Lock Protection Register command must be used as shown in the “Command Definition

Table” . Data bit D1 must be zero during the fourth bus cycle. All other data bits during the

fourth bus cycle are don’t cares. To determine whether block B is locked out, the Product ID

Entry command is given followed by a read operation from address 80H. If data bit D1 is zero,

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3623A–FLASH–7/06

block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the “Protec-

tion Register Addressing Table” on page 13 for the address locations in the protection register.

To read the protection register, the Product ID Entry command is given followed by a normal

read operation from an address within the protection register. After determining whether block

B is protected or not, or reading the protection register, the Product ID Exit command must be

given prior to performing any other operation.

4.13 RDY/BUSY

An open-drain READY/BUSY output pin provides another method of detecting the end of a

program or erase operation. RDY/BUSY is actively pulled low during the internal program and

erase cycles and is released at the completion of the cycle. The open-drain connection allows

for OR-tying of several devices to the same RDY/BUSY line. Please see “Status Bit Table” on

page 11 for more details.

4.14 Common Flash Interface (CFI)

CFI is a published, standardized data structure that may be read from a flash device. CFI

allows system software to query the installed device to determine the configurations, various

electrical and timing parameters, and functions supported by the device. CFI is used to allow

the system to learn how to interface to the flash device most optimally. The two primary bene-

fits of using CFI are ease of upgrading and second source availability. The command to enter

the CFI Query mode is a one-bus cycle command which requires writing data 98h to address

55h. The CFI Query command can be written when the device is ready to read data or can

also be written when the part is in the product ID mode. Once in the CFI Query mode, the sys-

tem can read CFI data at the addresses given in “Common Flash Interface Definition Table”

on page 26. To exit the CFI Query mode, the product ID exit command must be given.

4.15 Hardware Data Protection

The Hardware Data Protection feature protects against inadvertent programs to the

AT49SV322D(T) in the following ways: (a) V_CCsense: if V_CCis below 1.65V (typical), the pro-

gram function is inhibited. (b) V_CCpower-on delay: once V_CChas reached the V_CCsense level,

the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit:

holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit:

V

_PPis less than V_ILPP.

4.16 Input Levels

While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs

(OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of

the device. The I/O lines can only be driven from 0 to V_CC+ 0.6V.

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AT49SV322D(T)

3623A–FLASH–7/06

Figure 4-1. Data Polling Algorithm

Figure 4-2. Data Polling Algorithm

(Configuration Register = 00)

(Configuration Register = 01)

START

Read I/O7 - I/O0

Addr = VA

Read I/O7 - I/O0

Addr = VA

YES

I/O7 = Data?

NO

I/O3, I/O5 = 1?

YES

Read I/O7 - I/O0

Addr = VA

Read I/O7 - I/O0

Addr = VA

YES

I/O7 = Data?

NO

Program/Erase

Operation Not

Successful, Write

Product ID

Program/Erase

Operation Not

Successful, Write

Product ID

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

Operation

Successful,

Device in

Exit Command

Read Mode

Exit Command

Notes: 1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector

address within the sector being erased. During chip

erase, a valid address is any non-protected sector

address.

Notes: 1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector

address within the sector being erased. During chip

erase, a valid address is any non-protected sector

address.

2. I/O7 should be rechecked even if I/O5 = “1” because

I/O7 may change simultaneously with I/O5.

2. I/O7 should be rechecked even if I/O5 = “1” because

I/O7 may change simultaneously with I/O5.

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AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

Figure 4-3. Toggle Bit Algorithm

(Configuration Register = 00)

Figure 4-4. Toggle Bit Algorithm

(Configuration Register = 01)

START

Read I/O7 - I/O0

NO

Toggle Bit =

Toggle?

Toggle Bit =

Toggle?

YES

NO

I/O3, I/O5 = 1?

YES

Read I/O7 - I/O0

Twice

Read I/O7 - I/O0

Twice

Toggle Bit =

Toggle?

NO

Toggle Bit =

Toggle?

NO

YES

Program/Erase

Operation Not

Successful, Write

Product ID

Program/Erase

Operation Not

Successful, Write

Product ID

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

Program/Erase

Operation

Successful, Device

in Read Mode

Exit Command

Note:

1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

Note:

1. The system should recheck the toggle bit even if

I/O5 = “1” because the toggle bit may stop toggling

as I/O5 changes to “1”.

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AT49SV322D(T)

5. Status Bit Table

Status Bit

I/O7

00

I/O7

01

0

I/O6

I/O5⁽¹⁾

I/O3⁽²⁾

I/O2

00/01

1

RDY/BUSY

Configuration Register

Programming

00/01

I/O7

0

TOGGLE

0

Erasing

0

TOGGLE

Erase Suspended & Read

Erasing Sector

1

DATA

0

1

0

DATA

0

DATA

0

TOGGLE

DATA

1

0

Erase Suspended & Read

Non-erasing Sector

DATA

I/O7

DATA

Erase Suspended &

Program Non-erasing Sector

TOGGLE

Erase Suspended &

Program Suspended and

Reading from Non-

suspended Sectors

DATA

1

Program Suspended & Read

Programming Sector

I/O7

1

0

TOGGLE

DATA

1

Program Suspended & Read

Non-programming Sector

DATA

Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or

sector erase operation is performed on a protected sector.

2. I/O3 switches to a “1” when the V_PPlevel is not high enough to successfully perform program and erase operations.

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6. Command Definition Table

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Command

Sequence

Bus

Cycles

Addr

555

Data

D_OUT

AA

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

1

6

4

Chip Erase

Sector Erase

Word Program

AAA⁽²⁾

AAA

55

555

80

A0

555

AA

D_IN

AAA

55

555

10

30

555

AA

SA⁽³⁾

555

AA

AAA

Addr

Dual Word

Program⁽⁴⁾

5

6

555

AA

AAA

55

555

E0

80

Addr0

555

D_IN0

AA

Addr1

AAA

D_IN1

55

Enter Single Pulse

Program Mode

555

A0

60

Single Pulse Word

Program

1

6

1

Addr

555

D_IN

AA

B0

Sector Lockdown

AAA⁽²⁾

55

555

80

555

AA

AAA

55

SA⁽³⁾⁽⁵⁾

Erase/Program

Suspend

XXX

Erase/Program

Resume

1

XXX

30

Product ID Entry

Product ID Exit⁽⁶⁾

3

1

555

XXX

AA

AAA

55

555

90

F0⁽⁷⁾

Program Protection

Register

4

555

AA

AAA

55

555

C0

90

Addr⁽⁸⁾

080

D_IN

X0

Lock Protection

Register - Block B

Status of Block B

Protection

(9)

80

D_OUT

Set Configuration

Register

4

1

555

X55

AA

98

D0

XXX

00/01⁽¹⁰⁾

CFI Query⁽¹¹⁾

Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS

FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are don’t care.

2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.

3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 17 for

details).

4. This fast programming option enables the user to program two words in parallel only when V_PP= 9.5V. The Addresses,

Addr0 and Addr1, of the two words, D_IN0and D_IN1, must only differ in address A0. This command should be used during

manufacturing purposes only.

5. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or

power cycled.

6. Either one of the Product ID Exit commands can be used.

7. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.

8. Any addresses within the user programmable protection register region. Address locations are shown on “Protection Regis-

ter Addressing Table” on page 13.

9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.

10. The default state (after power-up) of the configuration register is “00”.

11. When accessing the data in the CFI table, the address format is A15 - A0 (Hex).

12

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

7. Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V_CC+ 0.6V

Voltage on V_PP

with Respect to Ground....................................-0.6V to + 9.5V

8. Protection Register Addressing Table

Address

Use

Factory

User

Block

A7

A6

A5

A4

0

A3

0

A2

0

A1

0

A0

1

81

A

B

1

0

82

1

0

1

0

83

1

0

1

84

1

0

1

0

85

1

0

1

0

1

86

User

1

0

1

0

87

User

1

0

1

88

User

1

0

1

0

Notes: 1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A20 - A8 = 0.

13

3623A–FLASH–7/06

9. AT49SV322D – Sector Address Table

Sector

Size (Bytes/Words)

Address Range (A20 - A0)

00000 - 00FFF

01000 - 01FFF

02000 - 02FFF

03000 - 03FFF

04000 - 04FFF

05000 - 05FFF

06000 - 06FFF

07000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

SA0

8K/4K

SA1

8K/4K

SA2

8K/4K

SA3

8K/4K

SA4

8K/4K

SA5

8K/4K

SA6

8K/4K

SA7

8K/4K

SA8

64K/32K

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

14

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

9. AT49SV322D – Sector Address Table (Continued)

Sector

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Size (Bytes/Words)

64K/32K

Address Range (A20 - A0)

F8000 - FFFFF

100000 - 107FFF

108000 - 10FFFF

110000 - 117FFF

118000 - 11FFFF

120000 - 127FFF

128000 - 12FFFF

130000 - 137FFF

138000 - 13FFFF

140000 - 147FFF

148000 - 14FFFF

150000 - 157FFF

158000 - 15FFFF

160000 - 167FFF

168000 - 16FFFF

170000 - 177FFF

178000 - 17FFFF

180000 - 187FFF

188000 - 18FFFF

190000 - 197FFF

198000 - 19FFFF

1A0000 - 1A7FFF

1A8000 - 1AFFFF

1B0000 - 1B7FFF

1B8000 - 1BFFFF

1C0000 - 1C7FFF

1C8000 - 1CFFFF

1D0000 - 1D7FFF

1D8000 - 1DFFFF

1E0000 - 1E7FFF

1E8000 - 1EFFFF

1F0000 -1F7FFF

1F8000 - 1FFFFF

15

3623A–FLASH–7/06

10. AT49SV322DT – Sector Address Table

Sector

Size (Bytes/Words)

64K/32K

Address Range (A20 - A0)

00000 - 07FFF

08000 - 0FFFF

10000 - 17FFF

18000 - 1FFFF

20000 - 27FFF

28000 - 2FFFF

30000 - 37FFF

38000 - 3FFFF

40000 - 47FFF

48000 - 4FFFF

50000 - 57FFF

58000 - 5FFFF

60000 - 67FFF

68000 - 6FFFF

70000 - 77FFF

78000 - 7FFFF

80000 - 87FFF

88000 - 8FFFF

90000 - 97FFF

98000 - 9FFFF

A0000 - A7FFF

A8000 - AFFFF

B0000 - B7FFF

B8000 - BFFFF

C0000 - C7FFF

C8000 - CFFFF

D0000 - D7FFF

D8000 - DFFFF

E0000 - E7FFF

E8000 - EFFFF

F0000 - F7FFF

F8000 - FFFFF

100000 - 107FFF

108000 - 10FFFF

110000 - 117FFF

118000 - 11FFFF

120000 - 127FFF

128000 - 12FFFF

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

16

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

10. AT49SV322DT – Sector Address Table (Continued)

Sector

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Size (Bytes/Words)

64K/32K

8K/4K

Address Range (A20 - A0)

130000 - 137FFF

138000 - 13FFFF

140000 - 147FFF

148000 - 14FFFF

150000 - 157FFF

158000 - 15FFFF

160000 - 167FFF

168000 - 16FFFF

170000 - 177FFF

178000 - 17FFFF

180000 - 187FFF

188000 - 18FFFF

190000 - 197FFF

198000 - 19FFFF

1A0000 - 1A7FFF

1A8000 - 1AFFFF

1B0000 - 1B7FFF

1B8000 - 1BFFFF

1C0000 - 1C7FFF

1C8000 - 1CFFFF

1D0000 - 1D7FFF

1D8000 - 1DFFFF

1E0000 - 1E7FFF

1E8000 - 1EFFFF

1F0000 - 1F7FFF

1F8000 - 1F8FFF

1F9000 - 1F9FFF

1FA000 - 1FAFFF

1FB000 - 1FBFFF

1FC000 - 1FCFFF

1FD000 - 1FDFFF

1FE000 - 1FEFFF

1FF000 - 1FFFFF

8K/4K

17

3623A–FLASH–7/06

11. DC and AC Operating Range

AT49SV322D(T)-80

-40°C - 85°C

Operating Temperature (Case)

Ind.

V

_CCPower Supply

1.65V to 1.95V

12. Operating Modes

(1)

Mode

CE

V_IL

V_IH

X

OE

V_IL

V_IH

X⁽²⁾

X

WE

V_IH

V_IL

X

RESET

V_PP

X⁽²⁾

Ai

X

I/O

Read

V_IH

V_IL

D_OUT

D_IN

Program/Erase⁽³⁾

V_IHPP

(4)

Standby/Program Inhibit

X

High-Z

V_IH

X

Program Inhibit

X

V_IL

X

(5)

X

V_ILPP

X

Output Disable

Reset

X

V_IH

X

High-Z

X

A0 = V_IL, A1 - A20 = V_IL

A0 = V_IH, A1 - A20 = V_IL

Manufacturer Code⁽⁷⁾

Device Code⁽⁷⁾

Product Identification

Software⁽⁶⁾

V_IH

Notes: 1. The VPP pin can be tied to V_CC. For faster program operations, V_PPcan be set to 9.5V 0.5V.

2. X can be V_ILor V_IH.

3. Refer to “Program Cycle Waveforms” on page 23.

4. V_IHPP(min) = 1.65V

5. V_ILPP(max) = 0.4V.

6. See details under “Software Product Identification Entry/Exit” on page 25.

7. Manufacturer Code: 001FH.

Device Code: 01DBH - AT49SV322D; 01D1H - AT49SV322DT.

18

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

13. DC Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

2

Units

µA

mA

µA

V

I_LI

Input Load Current

V_IN= 0V to V_CC

I_LO

Output Leakage Current

V_CCStandby Current CMOS

V_CCActive Read Current

V_CCProgramming Current

V_PPInput Load Current

Input Low Voltage

V_I/O= 0V to V_CC

2

I_SB

CE = V_CC- 0.3V to V_CC

f = 5 MHz; I_OUT= 0 mA

15

10

25

15

25

10

0.4

(1)

I_CC

I_CC1

I_PP1

V_IL

V_IH

Input High Voltage

V_CC- 0.2

V

V_OL1

V_OL2

V_OH1

V_OH2

Output Low Voltage

Output High Voltage

I_OL= 2.1 mA

I_OL= 1.0 mA

I_OH= -400 µA

I_OH= -100 µA

0.25

0.1

V

1.4

V

V_CC- 0.1

V

Note:

1. In the erase mode, I_CCis 25 mA.

19

3623A–FLASH–7/06

14. Input Test Waveforms and Measurement Level

9

t_R, t_F< 5 ns

15. Output Test Load

16. Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Symbol

C_IN

Typ

4

Max

6

Units

pF

Conditions

V_IN= 0V

C_OUT

8

12

pF

V_OUT= 0V

Note:

1. This parameter is characterized and is not 100% tested.

20

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

17. AC Read Characteristics

AT49SV322D(T)-80

Symbol

t_RC

Parameter

Min

Max

Units

ns

Read Cycle Time

80

t_ACC

Address to Output Delay

CE to Output Delay

OE to Output Delay

CE or OE to Output Float

80

20

25

ns

(1)

t_CE

ns

(2)

t_OE

0

ns

(3)(4)

t_DF

ns

Output Hold from OE, CE or Address,

whichever occurred first

t_OH

t_RO

0

ns

RESET to Output Delay

100

18. AC Read Waveforms^(1)(2)(3)(4)

t_RC

ADDRESS

CE

ADDRESS VALID

t_CE

t_OE

OE

t_DF

t_OH

t_ACC

t_RO

RESET

HIGH Z

OUTPUT

VALID

OUTPUT

Notes: 1. CE may be delayed up to t_ACC- t_CEafter the address transition without impact on t_ACC

2. OE may be delayed up to t_CE- t_OEafter the falling edge of CE without impact on t_CEor by t_ACC- t_OEafter an address change

without impact on t_ACC

.

3. t_DFis specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

21

3623A–FLASH–7/06

19. AC Word Load Characteristics

Symbol

t_AS, t_OES

t_AH

Parameter

Min

0

Max

Units

ns

Address, OE Setup Time

Address Hold Time

25

0

ns

t_CS

Chip Select Setup Time

Chip Select Hold Time

Write Pulse Width (WE or CE)

Write Pulse Width High

Data Setup Time

ns

t_CH

0

ns

t_WP

25

15

25

0

ns

t_WPH

ns

t_DS

ns

t_DH, t_OEH

Data, OE Hold Time

ns

20. AC Word Load Waveforms

20.1 WE Controlled

20.2 CE Controlled

22

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

21. Program Cycle Characteristics

Symbol

Parameter

Min

Typ

10

5

Max

120

60

Units

t_BP

Word Programming Time

Word Programming Time in Dual Programming Mode

Address Setup Time

µs

t_BPD

t_AS

0

25

0

ns

t_AH

Address Hold Time

ns

t_DS

Data Setup Time

ns

t_DH

Data Hold Time

ns

t_WP

Write Pulse Width

25

15

70

500

ns

t_WPH

t_WC

Write Pulse Width High

Write Cycle Time

ns

t_RP

Reset Pulse Width

ns

t_EC

Chip Erase Cycle Time

Sector Erase Cycle Time (4K Word Sectors)

Sector Erase Cycle Time (32K Word Sectors)

Erase Suspend Time

33

0.1

0.5

seconds

µs

t_SEC1

t_SEC2

t_ES

2.0

6.0

15

t_PS

Program Suspend Time

10

µs

22. Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t

BP

t

WP

WPH

WE

t

DH

AS

AH

555

AAA

555

ADDRESS

555

A0 - A20

DATA

t

WC

t

DS

INPUT

DATA

AA

55

A0

AA

23. Sector or Chip Erase Cycle Waveforms

(1)

OE

CE

t

WP

WPH

WE

A0-A20

DATA

t

DH

AS

AH

555

t

AAA

555

AAA

Note

2

WC

t

EC

DS

AA

WORD

55

WORD

80

WORD

AA

WORD

55

Note 3

0

1

2

3

WORD

4

WORD 5

Notes: 1. OE must be high only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.

(See note 3 under “Command Definition Table” on page 12.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

23

3623A–FLASH–7/06

24. Data Polling Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

Write Recovery Time

ns

t_WR

0

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 21.

25. Data Polling Waveforms

WE

CE

t_OEH

OE

t_DH

t_WR

t_OE

HIGH Z

I/O7

An

A0-A20

26. Toggle Bit Characteristics⁽¹⁾

Symbol

Parameter

Min

10

Typ

Max

Units

ns

t_DH

Data Hold Time

t_OEH

t_OE

t_OEHP

t_WR

OE Hold Time

10

ns

OE to Output Delay⁽²⁾

OE High Pulse

ns

50

0

ns

Write Recovery Time

ns

Notes: 1. These parameters are characterized and not 100% tested.

2. See t_OEspec in “AC Read Characteristics” on page 21.

27. Toggle Bit Waveforms^(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The t_OEHPspecification must be met by the toggling

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

24

AT49SV322D(T)

3623A–FLASH–7/06

28. Software Product Identification

Entry⁽¹⁾

30. Sector Lockdown Enable

Algorithm⁽¹⁾

LOAD DATA AA

TO

LOAD DATA AA

TO

ADDRESS 555

LOAD DATA 55

TO

LOAD DATA 55

TO

ADDRESS AAA

LOAD DATA 90

TO

LOAD DATA 80

TO

ADDRESS 555

ENTER PRODUCT

IDENTIFICATION

(2)(3)(5)

MODE

LOAD DATA AA

TO

ADDRESS 555

29. Software Product Identification

Exit⁽¹⁾⁽⁶⁾

LOAD DATA 55

TO

OR

LOAD DATA AA

TO

LOAD DATA F0

TO

ADDRESS 555

ANY ADDRESS

ADDRESS AAA

EXIT PRODUCT

IDENTIFICATION

MODE⁽⁴⁾

LOAD DATA 55

TO

LOAD DATA 60

TO

ADDRESS AAA

SECTOR ADDRESS

LOAD DATA F0

TO

ADDRESS 555

(2)

PAUSE 200 µs

EXIT PRODUCT

IDENTIFICATION

MODE⁽⁴⁾

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), and A11 - A20

(Don’t Care).

Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)

Address Format: A11 - A0 (Hex), and A11 - A20

(Don’t Care).

2. Sector Lockdown feature enabled.

2. A1 - A20 = V_IL. Manufacturer Code is read for A0 = V_IL;

Device Code is read for A0 = V_IH. Additional Device Code is

read from address 0003H.

3. The device does not remain in identification mode if

powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 001FH

Device Code: 01DBH – AT49SV322D;

01D1H – AT49SV322DT.

Additional Device Code: 0001H – AT49SV322D(T)

6. Either one of the Product ID Exit commands can be used.

25

AT49SV322D(T)

3623A–FLASH–7/06

31. Common Flash Interface Definition Table

Address

AT49SV322D(T)

10h

Data

AT49SV322D(T)

0051h

0052h

0059h

0002h

0000h

0041h

0000h

0017h

0019h

0090h

00A0h

0004h

0002h

0009h

000Fh

0004h

0016h

0001h

0000h

0002h

0000h

0002h

0007h

0000h

0020h

0000h

003Eh

0000h

0001h

Comments

“Q”

“R”

“Y”

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

VCC min write/erase

VCC max write/erase

VPP min voltage

VPP max voltage

Typ word write – 10 µs

Typ dual word program time – 5 µs

Typ sector erase, 500 ms

Typ chip erase, 33,000 ms

Max word write/typ time

Max dual word program time/typ time

Max sector erase/typ sector erase

Max chip erase/ typ chip erase

Device size

20h

21h

22h

23h

24h

25h

26h

27h

28h

x16 device

29h

x16 device

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

Maximum number of bytes in multiple byte write = 4

2 regions, x = 2

8K bytes, Y = 7

8K bytes, Z = 32

30h

8K bytes, Z = 32

31h

64K bytes, Y = 62

32h

64K bytes, Y = 62

33h

64K bytes, Z = 256

34h

64K bytes, Z = 256

26

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

31. Common Flash Interface Definition Table (Continued)

Address

Data

AT49SV322D(T)

Comments

VENDOR SPECIFIC EXTENDED QUERY

41h

42h

43h

44h

45h

0050h

0052h

0049h

0031h

0030h

“P”

“R”

“I”

Major version number, ASCII

Minor version number, ASCII

Bit 0 – chip erase supported, 0 – no, 1 – yes

Bit 1 – erase suspend supported, 0 – no, 1 – yes

Bit 2 – program suspend supported, 0 – no, 1 – yes

Bit 3 – simultaneous operations supported,

0 – no, 1 – yes

46h

0087h

Bit 4 – burst mode read supported, 0 – no, 1 – yes

Bit 5 – page mode read supported, 0 – no, 1 – yes

Bit 6 – queued erase supported, 0 – no, 1 – yes

Bit 7 – protection bits supported, 0 – no, 1 – yes

0000h (top)

or

0001h (bottom)

47h

48h

Bit 0 – top (“0”) or bottom (“1”) boot block device, undefined bits are “0”

Bit 0 – 4 word linear burst with wrap around,

0 – no, 1 – yes

Bit 1 – 8 word linear burst with wrap around,

0 – no, 1 – yes

0000h

Bit 2 – continuos burst, 0 - no, 1 - yes

Undefined bits are “0”

Bit 0 – 4 word page, 0 – no, 1 – yes

Bit 1 – 8 word page, 0 – no, 1 – yes

Undefined bits are “0”

49h

0000h

4Ah

4Bh

4Ch

0080h

0003h

Location of protection register lock byte, the section’s first byte

# of bytes in the factory prog section of prot register – 2*n

# of bytes in the user prog section of prot register – 2*n

27

3623A–FLASH–7/06

32. Ordering Information

32.1 Green Package (Pb/Halide-free)

I

_CC(mA)

t_ACC

(ns)

Active

Standby

Ordering Code

Package

Operation Range

AT49SV322D-80CU

AT49SV322D-80TU

48C17

48T

80

15

0.025

Industrial

(-40° to 85°C)

AT49SV322DT-80CU

AT49SV322DT-80TU

48C17

48T

15

Package Type

48C17

48T

48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)

48-lead, Plastic Thin Small Outline Package (TSOP)

28

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

33. Packaging Information

33.1 48C17 – CBGA

E

A1 Ball ID

D

A1

Top View

A

Side View

1.50 REF

E1

A1 Ball Corner

e

2.20 REF

A

COMMON DIMENSIONS

(Unit of Measure = mm)

B

C

D

E

F

MIN

MAX

NOM

7.0

NOTE

SYMBOL

D1

E

6.9

7.1

E1

D

4.0 TYP

10.0

G

H

9.9

10.1

D1

A

5.6 TYP

–

e

–

1.0

–

6

5

4

3

2

1

A1

e

0.20

–

Øb

0.80 BSC

0.35 TYP

Bottom View

Øb

10/26/05

DRAWING NO. REV.

48C17

TITLE

2325 Orchard Parkway

San Jose, CA 95131

48C17, 48-ball (6 x 8 Array), 0.80 mm Pitch,

7.0 x 10.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA)

B

R

29

3623A–FLASH–7/06

33.2 48T – TSOP

PIN 1

0º ~ 8º

c

Pin 1 Identifier

D1

D

L

b

L1

e

A2

E

GAGE PLANE

A

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

A1

MIN

–

MAX

1.20

0.15

1.05

20.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

19.80

18.30

11.90

0.50

–

1.00

Notes:

1. This package conforms to JEDEC reference MO-142, Variation DD.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

20.00

18.40

12.00

0.60

D1

E

18.50 Note 2

12.10 Note 2

0.70

L

L1

b

0.25 BASIC

0.22

0.17

0.10

0.27

0.21

c

–

e

0.50 BASIC

10/18/01

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP)

48T

B

R

30

AT49SV322D(T)

3623A–FLASH–7/06

AT49SV322D(T)

34. Revision History

Revision No.

History

• Initial Release

Revision A – July 2006

31

3623A–FLASH–7/06

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Microcontrollers

Regional Headquarters

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High-Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

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TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

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marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

3623A–FLASH–7/06


型号：	AT49SV322DT-80TU
厂家：	ATMEL
描述：	32-megabit (2M x 16) 1.8-volt Only Flash Memory 32兆位（ 2M ×16 ） 1.8伏只快闪记忆体闪存存储内存集成电路光电二极管异步传输模式 ATM
文件：	总32页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT49SV322DT-80TU [ATMEL]

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