AT49SV802A-80CI [ATMEL]
Flash, 512KX16, 80ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CBGA-48;
| 型号： | AT49SV802A-80CI |
| 厂家： | 
ATMEL |
| 描述： | Flash, 512KX16, 80ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CBGA-48 内存集成电路 |
| 文件： | 总28页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Voltage Read/Write Operation: 1.65V to 1.95V
• Access Time – 80 ns
• Sector Erase Architecture
– Fifteen 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Byte/Word Program Time – 12 µs
• Fast Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending
Programming of Any Other Byte/Word
• Low-power Operation
8-megabit
(512K x 16/
1M x 8)
1.8-volt Only
Flash Memory
– 12 mA Active
– 13 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
AT49SV802A
AT49SV802AT
Description
The AT49SV802A(T) is a 1.8-volt 8-megabit Flash memory organized as 524,288
words of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data appears on
I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 23 sec-
tors for erase operations. The AT49SV802A(T) is offered in a 48-lead TSOP and a
48-ball CBGA package. The device has CE and OE control signals to avoid any bus
contention. This device can be read or reprogrammed using a single power supply,
making it ideally suited for in-system programming.
Preliminary
Pin Configurations
Pin Name
A0 - A18
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
OE
WE
RESET
RDY/BUSY
I/O0 - I/O14
I/O15 (A-1)
READY/BUSY Output
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
NC
Selects Byte or Word Mode
No Connect
Rev. 3522A–FLASH–10/04
TSOP Top View
Type 1
CBGA Top View
(Ball Down)
1
2
3
4
5
6
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
BYTE
GND
I/O15/A-1
I/O7
3
4
A
B
C
D
E
F
5
6
I/O14
I/O6
A3
A7 RDY/BUSY WE
A9
A13
A12
A14
A15
A16
7
A8
8
I/O13
I/O5
A4
A2
A17
A6
NC
A18
RST
NC
A8
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O12
I/O4
A10
A11
I/O7
WE
RESET
NC
VCC
I/O11
I/O3
A1
A5
NC
NC
NC
RDY/BUSY
A18
A17
A7
I/O10
I/O2
A0
I/O0
I/O8
I/O9
I/O1
I/O2
I/O10
I/O11
I/O3
I/O5
I/O9
I/O1
CE
OE
VSS
I/O12 I/O14 BYTE
G
H
A6
I/O8
A5
I/O0
VCC
I/O4
I/O13 I/015/A-1
A4
OE
A3
GND
CE
I/O6
VSS
A2
A1
A0
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector (see “Sector Lockdown” section).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by
the toggle bit.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering
down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing
it back to VCC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will
not work while in this mode; if entered they will result in data being programmed into the
device. It is not recommended that the six-byte code reside in the software of the final product
but only exist in external programming code.
The BYTE pin controls whether the device data I/O pins operate in the byte or word configura-
tion. If the BYTE pin is set at logic “1”, the device is in word configuration, I/O0 - I/O15 are
active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins
I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-
stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.
2
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
Block Diagram
I/O0 - I/O15/A-1
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
INPUT
A0 - A18
BUFFER
STATUS
CE
REGISTER
WE
COMMAND
REGISTER
OE
RESET
BYTE
ADDRESS
LATCH
DATA
RDY/BUSY
COMPARATOR
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
Y-DECODER
X-DECODER
Y-GATING
VCC
GND
MAIN
MEMORY
Device
Operation
READ: The AT49SV802A(T) is accessed like an EPROM. When CE and OE are low and WE
is high, the data stored at the memory location determined by the address pins are asserted
on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition in Hex” table on page 11 (I/O8 - I/O15 are
don’t care inputs for the command codes). The command sequences are written by applying a
low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address
is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Standard microprocessor write timings are used. The address
locations used in the command sequences are not affected by entering the command
sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
3
3522A–FLASH–10/04
ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC
.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 23 sec-
tors (SA0 - SA22) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a sector is tSEC. When the sec-
tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the oper-
ation terminating immediately.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-
cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the
internal device command register and is a four-bus cycle operation. The device will automati-
cally generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 10 and
the following four sections describe the function of these bits. To provide greater flexibility for
system designers, the AT49SV802A(T) contains a programmable configuration register. The
configuration register allows the user to specify the status bit operation. The configuration reg-
ister can be set to one of two different values, “00” or “01”. If the configuration register is set to
“00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be
given after a successful program or erase operation before the part will return to the read
mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration regis-
ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 11, the value of the configuration register can be
changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-
ter. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
4
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
DATA POLLING: The AT49SV802A(T) features Data Polling to indicate the end of a program
cycle. If the status configuration register is set to a “00”, during a program cycle an attempted
read of the last byte/word loaded will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is valid on all outputs and the next
cycle may begin. During a chip or sector erase operation, an attempt to read the device will
give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from
the device. Data Polling may begin at any time during the program cycle. Please see “Status
Bit Table” on page 10 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has com-
pleted a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 1 and 2 on page 8.
TOGGLE BIT: In addition to Data Polling the AT49SV802A(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the memory will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle. Please see “Sta-
tus Bit Table” on page 10 for more details.
The toggle bit status bit should be used in conjunction with the erase/program status bit as
shown in the algorithm in Figures 3 and 4 on page 9.
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates
whether the program or erase operation has exceeded a specified internal pulse count limit. If
the status bit is a “1”, the device is unable to verify that an erase or a byte/word program oper-
ation has been successfully performed. If a program (Sector Erase) command is issued to a
protected sector, the protected sector will not be programmed (erased). The device will go to a
status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera-
tion did not complete as requested. Once the erase/program status bit has been set to a “1”,
the system must write the Product ID Exit command to return to the read mode. The
erase/program status bit is a “0” while the erase or program operation is still in progress.
Please see “Status Bit Table” on page 10 for more details.
SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-
vents programming of data in the designated sectors once the feature has been enabled.
These sectors can contain secure code that is used to bring up the system. Enabling the lock-
down feature will allow the boot code to stay in the device while data in the rest of the device is
updated. This feature does not have to be activated; any sector’s usage as a write-protected
region is optional to the user.
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.
SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-
ming of a sector is locked down. When the device is in the software product identification
mode (see “Software Product Identification Entry/Exit” sections on page 22), a read from
address location 00002H within a sector will show if programming the sector is locked down. If
the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program
lockdown feature has been enabled and the sector cannot be programmed. The software
product identification exit code should be used to return to standard operation.
5
3522A–FLASH–10/04
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is
through reset or power-up cycles. After power-up or reset, the content of a sector that is
locked down can be erased and reprogrammed.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector or chip erase operation and then program or read data from a different sector
within the memory. After the Erase Suspend command is given, the device requires a
maximum time of 15 µs to suspend the erase operation. After the erase operation has been
suspended, the system can then read data or program data to any other sector within the
device. An address is not required during the Erase Suspend command. During a sector erase
suspend, another sector cannot be erased. To resume the sector erase operation, the system
must write the Erase Resume command. The Erase Resume command is a one-bus cycle
command. The device also supports an erase suspend during a complete chip erase. While
the chip erase is suspended, the user can read from any sector within the memory that is pro-
tected. The command sequence for a chip erase suspend and a sector erase suspend are the
same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the
system to interrupt a programming operation and then read data from a different byte/word
within the memory. After the Program Suspend command is given, the device requires a max-
imum of 20 µs to suspend the programming operation. After the programming operation has
been suspended, the system can then read data from any other byte/word that is not con-
tained in the sector in which the programming operation was suspended. An address is not
required during the program suspend operation. To resume the programming operation, the
system must write the Program Resume command. The program suspend and resume are
one-bus cycle commands. The command sequence for the erase suspend and program
suspend are the same, and the command sequence for the erase resume and program
resume are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see “Operating Modes” on page 15 (for hardware operation) or “Software Product
Identification Entry/Exit” sections on page 22. The manufacturer and device codes are the
same for both modes.
128-BIT PROTECTION REGISTER: The AT49SV802A(T) contains a 128-bit register that can
be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be repro-
grammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the “Command Definition in Hex”
table on page 11. To lock out block B, the four-bus cycle Lock Protection Register command
must be used as shown in the “Command Definition in Hex” table. Data bit D1 must be zero
during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To
determine whether block B is locked out, the Product ID Entry command is given followed by a
read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one,
block B can be reprogrammed. Please see the “Protection Register Addressing Table” on
page 12 for the address locations in the protection register. To read the protection register, the
Product ID Entry command is given followed by a normal read operation from an address
within the protection register. After determining whether block B is protected or not, or reading
the protection register, the Product ID Exit command must be given prior to performing any
other operation.
6
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
RDY/BUSY: An open-drain READY/BUSY output pin provides another method of detecting
the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal
program and erase cycles and is released at the completion of the cycle. The open-drain con-
nection allows for OR-tying of several devices to the same RDY/BUSY line. Please see
“Status Bit Table” on page 10 for more details.
CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be
read from a flash device. CFI allows system software to query the installed device to deter-
mine the configurations, various electrical and timing parameters, and functions supported by
the device. CFI is used to allow the system to learn how to interface to the flash device most
optimally. The two primary benefits of using CFI are ease of upgrading and second source
availability. The command to enter the CFI Query mode is a one-bus cycle command which
requires writing data 98h to address 55h. The CFI Query command can be written when the
device is ready to read data or can also be written when the part is in the product ID mode.
Once in the CFI Query mode, the system can read CFI data at the addresses given in Table 1
on page 23. To exit the CFI Query mode, the product ID exit command must be given.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the AT49SV802A(T) in the following ways: (a) VCC sense: if VCC is
below 1.65V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has
reached the VCC sense level, the device will automatically time out 10 ms (typical) before pro-
gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits
program cycles.
INPUT LEVELS: While operating with a 1.65V to 1.95V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
7
3522A–FLASH–10/04
Figure 1. Data Polling Algorithm
Figure 2. Data Polling Algorithm
(Configuration Register = 00)
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Addr = VA
YES
I/O7 = Data?
NO
NO
Toggle Bit =
Toggle?
YES
NO
I/O5 = 1?
NO
I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Twice
YES
I/O7 = Data?
NO
Toggle Bit =
Toggle?
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Program/Erase
Operation
Successful,
Write Product
ID Exit Command
Program/Erase
Operation Not
Successful, Write
Product ID
Operation
Successful,
Device in
Exit Command
Read Mode
Exit Command
Note:
1. VA = Valid address for programming. During a sec-
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
Notes: 1. VA = Valid address for programming. During a sec-
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
2. I/O7 should be rechecked even if I/O5 = “1”
because I/O7 may change simultaneously with
I/O5.
8
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
Figure 3. Toggle Bit Algorithm
Figure 4. Toggle Bit Algorithm
(Configuration Register = 00)
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
NO
NO
Toggle Bit =
Toggle?
Toggle Bit =
Toggle?
YES
YES
NO
NO
I/O5 = 1?
I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Twice
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
Toggle Bit =
Toggle?
NO
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Operation
Successful,
Device in
Exit Command
Read Mode
Exit Command
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
9
3522A–FLASH–10/04
Status Bit Table
Status Bit
I/O7
00
I/O7
01
0
I/O6
I/O5(1)
I/O2
00/01
1
RDY/BUSY
Configuration Register
Programming
00/01
00/01
00/01
I/O7
0
TOGGLE
TOGGLE
0
0
0
0
Erasing
0
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
DATA
0
1
0
DATA
0
TOGGLE
DATA
1
1
0
Erase Suspended & Read
Non-erasing Sector
DATA
I/O7
DATA
Erase Suspended & Program
Non-erasing Sector
TOGGLE
TOGGLE
Erase Suspended & Program
Suspended and Reading from
Non-suspended Sectors
DATA
DATA
DATA
DATA
DATA
1
Program Suspended & Read
Programming Sector
I/O7
1
1
0
TOGGLE
DATA
1
1
Program Suspended & Read
Non-programming Sector
DATA
DATA
DATA
DATA
Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
10
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
Command Definition in Hex(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
555
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
6
4
Chip Erase
AAA(2)
AAA
55
55
55
555
555
555
80
80
A0
555
555
AA
AA
DIN
AAA
AAA
55
55
555
10
30
Sector Erase
Byte/Word Program
555
AA
SA(3)(4)
555
AA
AAA
Addr
Enter Single Pulse
Program Mode
6
555
AA
AAA
55
555
80
555
555
AA
AAA
AAA
55
55
555
A0
60
Single Pulse
Byte/Word Program
1
6
1
Addr
555
DIN
AA
B0
Sector Lockdown
AAA(2)
55
555
80
AA
SA(3)(4)
Erase/Program
Suspend
XXX
Erase/Program
Resume
1
XXX
30
Product ID Entry
Product ID Exit(5)
Product ID Exit(5)
3
3
1
555
555
XXX
AA
AA
AAA
AAA
55
55
555
555
90
F0(8)
F0(8)
Program Protection
Register
4
4
4
555
555
555
AA
AA
AA
AAA
AAA
AAA
AAA
55
55
55
55
555
555
555
555
C0
C0
90
Addr
080
80
DIN
X0
Lock Protection
Register - Block B
Status of Block B
Protection
(6)
DOUT
Set Configuration
Register
4
1
555
X55
AA
98
D0
XXX
00/01(7)
CFI Query
Notes:
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8
are don’t care. The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A18 through A11 are don’t care in
the word mode. Address A18 through A11 and A-1 are don’t care in the byte mode.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any byte/word address within a sector can be used to designate the sector address (see pages 13 - 14 for details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power cycled.
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on VPP
with Respect to Ground...................................-0.6V to +13.0V
11
3522A–FLASH–10/04
Protection Register Addressing Table
Word
Use
Factory
Factory
Factory
Factory
User
Block
A7
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
1
0
1
2
3
4
5
6
7
A
A
A
A
B
B
B
B
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
User
1
0
0
0
0
1
1
0
User
1
0
0
0
0
1
1
1
User
1
0
0
0
1
0
0
0
Note:
All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A18 - A8 = 0.
12
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
AT49SV802A – Sector Address Table
x8
x16
Sector
SA0
Size (Bytes/Words)
8K/4K
Address Range (A18 - A-1)
Address Range (A18 - A0)
000000 - 001FFF
002000 - 003FFF
004000 - 005FFF
006000 - 007FFF
008000 - 009FFF
00A000 - 00BFFF
00C000 - 00DFFF
00E000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0FFFFF
00000 - 00FFF
01000 - 01FFF
02000 - 02FFF
03000 - 03FFF
04000 - 04FFF
05000 - 05FFF
06000 - 06FFF
07000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
SA1
8K/4K
SA2
8K/4K
SA3
8K/4K
SA4
8K/4K
SA5
8K/4K
SA6
8K/4K
SA7
8K/4K
SA8
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
13
3522A–FLASH–10/04
AT49SV802AT – Sector Address Table
x8
x16
Sector
SA0
Size (Bytes/Words)
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
64K/32K
8K/4K
Address Range (A18 - A-1)
000000 - 00FFFF
010000 - 01FFFF
020000 - 02FFFF
030000 - 03FFFF
040000 - 04FFFF
050000 - 05FFFF
060000 - 06FFFF
070000 - 07FFFF
080000 - 08FFFF
090000 - 09FFFF
0A0000 - 0AFFFF
0B0000 - 0BFFFF
0C0000 - 0CFFFF
0D0000 - 0DFFFF
0E0000 - 0EFFFF
0F0000 - 0F1FFF
F20000 - F3FFFF
F40000 - F5FFFF
F60000 - F7FFFF
F80000 - F9FFFF
FA0000 - FBFFFF
FC0000 - FDFFFF
FE0000 - FFFFFF
Address Range (A18 - A0)
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 78FFF
79000 - 79FFF
7A000 - 7AFFF
7B000 - 7BFFF
7C000 - 7CFFF
7D000 - 7DFFF
7E000 - 7EFFF
7F000 - 7FFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
8K/4K
14
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
DC and AC Operating Range
AT49SV802A(T)-80
-40°C - 85°C
Operating Temperature (Case)
Ind.
VCC Power Supply
1.65V to 1.95V
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
RESET
VIH
Ai
Ai
Ai
X
I/O
Read
VIH
VIL
X
DOUT
DIN
Program/Erase(2)
VIH
Standby/Program Inhibit
VIH
High-Z
VIH
X
VIH
Program Inhibit
X
VIL
VIH
X
VIH
Output Disable
Reset
X
X
VIH
High-Z
High-Z
X
X
VIL
X
Product Identification
A1 - A18 = VIL, A9 = VH(3), A0 = VIL
A1 - A18 = VIL, A9 = VH(3), A0 = VIH
A0 = VIL, A1 - A18 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A18 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms on page 20.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 1FH (x8); 001FH (x16), Device Code: 00C4H - AT49SV802A;
00C6H - AT49SV802AT.
5. See details under “Software Product Identification Entry/Exit” on page 22.
15
3522A–FLASH–10/04
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
2
Units
µA
µA
µA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Active Read Current
VCC Programming Current
Input Low Voltage
VI/O = 0V to VCC
10
25
25
40
0.4
ISB
CE = VCC - 0.3V to VCC
f = 5 MHz; IOUT = 0 mA
13
12
(1)
ICC
ICC1
VIL
VIH
Input High Voltage
VCC – 2.0
V
VOL1
VOL2
VOH1
VOH2
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
IOL = 2.1 mA
IOL = 100 µA
IOH = -400 µA
IOH = -100 µA
0.25
0.10
V
V
1.4
V
VCC – 0.1
V
Note:
1. In the erase mode, ICC is 45 mA.
16
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
AC Read Characteristics
AT49SV802A(T)-80
Symbol
tRC
Parameter
Min
Max
Units
ns
Read Cycle Time
80
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
80
80
80
25
ns
(1)
tCE
ns
(2)
tOE
0
0
ns
(3)(4)
tDF
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
tRO
0
ns
ns
RESET to Output Delay
100
AC Read Waveforms(1)(2)(3)(4)
tRC
ADDRESS
CE
ADDRESS VALID
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
17
3522A–FLASH–10/04
Input Test Waveforms and Measurement Level
0.9
tR, tF < 5 ns
Output Test Load
VCC
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
This parameter is characterized and is not 100% tested.
18
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
AC Byte/Word Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Setup Time
Address Hold Time
tAH
35
0
ns
tCS
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
ns
tCH
0
ns
tWP
35
35
0
ns
tDS
ns
tDH, tOEH
tWPH
Data, OE Hold Time
Write Pulse Width High
ns
35
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
19
3522A–FLASH–10/04
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
µs
tBP
Byte/Word Programming Time
Address Setup Time
12
200
tAS
0
35
35
0
ns
tAH
Address Hold Time
ns
tDS
Data Setup Time
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
35
35
70
500
ns
tWPH
tWC
tRP
Write Pulse Width High
Write Cycle Time
ns
ns
Reset Pulse Width
ns
tEC
Chip Erase Cycle Time
Sector Erase Cycle Time (4K Word Sectors)
Sector Erase Cycle Time (32K Word Sectors)
Erase Suspend Time
13
0.3
1.0
seconds
seconds
seconds
µs
tSEC1
tSEC2
tES
3.0
5.0
15
tPS
Program Suspend Time
10
µs
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
WP
BP
WPH
WE
t
t
t
DH
AS
AH
555
t
AAA
555
ADDRESS
555
A0 - A18
DATA
WC
t
DS
INPUT
DATA
AA
55
A0
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
A0-A18
DATA
t
t
t
DH
AS
AH
555
t
AAA
555
555
AAA
Note
2
WC
t
t
EC
DS
AA
WORD
55
WORD
80
WORD
AA
WORD
55
WORD
Note 3
0
1
2
3
4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under “Command Definitions in Hex” on page 11.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
20
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 17.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tWR
tOE
HIGH Z
I/O7
An
An
An
An
An
A0-A18
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
50
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 17.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
21
3522A–FLASH–10/04
Software Product Identification Entry(1)
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 555
ADDRESS 555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS AAA
ADDRESS AAA
LOAD DATA 80
TO
LOAD DATA 90
TO
ADDRESS 555
ADDRESS 555
LOAD DATA AA
TO
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
ADDRESS 555
LOAD DATA 55
TO
Software Product Identification Exit(1)(6)
ADDRESS AAA
OR
LOAD DATA AA
LOAD DATA F0
TO
TO
ADDRESS 555
ANY ADDRESS
LOAD DATA 60
TO
SECTOR ADDRESS
EXIT PRODUCT
IDENTIFICATION
LOAD DATA 55
TO
(4)
MODE
ADDRESS AAA
(2)
PAUSE 200 µs
LOAD DATA F0
TO
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), A-1, and A11 - A18
(Don’t Care).
ADDRESS 555
2. Sector Lockdown feature enabled.
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), A-1, and A11 - A18 (Don’t
Care).
2. A1 - A18 = VIL. Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH
.
3. The device does not remain in identification mode if powered
down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH(x8); 001FH(x16)
Device Code: 00C4H - AT49SV802A;
00C6H - AT49SV802AT.
6. Either one of the Product ID Exit commands can be used.
22
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
Table 1. Common Flash Interface Definition for AT49SV802A(T)
Address [x16 Mode]
10h
Address [x8 Mode]
20h
Data
0051h
0052h
0059h
0002h
0000h
0041h
0000h
0000h
0000h
0000h
0000h
0017h
0019h
0000h
0000h
0004h
0000h
000Ah
000Eh
0004h
0000h
0002h
0002h
0014h
0002h
0000h
0000h
0000h
0002h
000Eh
0000h
0000h
0001h
0007h
0000h
0020h
0000h
Comments
“Q”
“R”
“Y”
11h
22h
12h
24h
13h
26h
14h
28h
15h
2Ah
2Ch
2Eh
30h
16h
17h
18h
19h
32h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
34h
36h
VCC min write/erase
38h
VCC max write/erase
3Ah
3Ch
3Eh
40h
VPP min voltage – No VPP
VPP max voltage – No VPP
Typ word write – 12 µs
20h
21h
42h
Typ block erase: 1,000 ms
Typ chip erase: 13,000 ms
Max word write/typ time
N/A
22h
44h
23h
46h
24h
48h
25h
4Ah
4Ch
4Eh
50h
Max block erase/typ block erase
Max chip erase/typ chip erase
Device size
26h
27h
28h
x8/x16 device
29h
52h
x8/x16 device
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
54h
Multiple byte write not supported
Multiple byte write not supported
2 regions, X = 2
56h
58h
5Ah
5Ch
5Eh
60h
64K bytes, Y = 14
64K bytes, Y = 14
64K bytes, Z = 256
64K bytes, Z = 256
8K bytes, Y = 7
30h
31h
62h
32h
64h
8K bytes, Y = 7
33h
66h
8K bytes, Z = 32
34h
68h
8K bytes, Z = 32
23
3522A–FLASH–10/04
Table 1. Common Flash Interface Definition for AT49SV802A(T) (Continued)
Address [x16 Mode]
Address [x8 Mode]
Data
Comments
Vendor Specific Extended Query
41h
42h
43h
44h
45h
46h
82h
84h
86h
88h
8Ah
8Ch
0050h
0052h
0049h
0031h
0030h
0087h
“P”
“R”
“I”
Major version number, ASCII
Minor version number, ASCII
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported,
0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
47h
48h
8Eh
90h
0000h (top) or
0001h (bottom)
Bit 8 – top (“0”) or bottom (“1”) boot block device undefined
bits are “0”
0000h
Bit 0 – 4-word linear burst with wrap around,
0 – no, 1 – yes
Bit 1 – 8-word linear burst with wrap around,
0 – no, 1 – yes
Bit 2 – continuos burst, 0 – no, 1 – yes
Undefined bits are “0”
49h
92h
0000h
Bit 0 – 4-word page, 0 – no, 1 – yes
Bit 1 – 8-word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
4Bh
94h
96h
0080h
0003h
Location of protection register lock byte, the section’s first byte
# of bytes in the factory prog section
of prot register – 2*n
4Ch
98h
0003h
# of bytes in the user prog section of prot
register – 2*n
24
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
AT49SV802A(T) Ordering Information
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
Industrial
AT49SV802A-80CI
AT49SV802A-80TI
48C19
48T
80
80
25
0.025
0.025
(-40° to 85°C)
Industrial
AT49SV802AT-80CI
AT49SV802AT-80TI
48C19
48T
25
(-40° to 85°C)
Package Type
48C19
48T
48-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
48-lead, Plastic Thin Small Outline Package (TSOP)
25
3522A–FLASH–10/04
Packaging Information
48C19 – CBGA
E
A1 Ball ID
D
A1
Top View
A
Side View
1.0 REF
E1
A1 Ball Corner
e
1.20 REF
A
COMMON DIMENSIONS
(Unit of Measure = mm)
B
C
D
E
F
MIN
MAX
NOM
6.00
NOTE
SYMBOL
D1
E
5.90
6.10
E1
D
4.0 TYP
8.00
G
H
7.90
8.10
D1
A
5.6 TYP
–
e
–
1.0
–
6
5
4
3
2
1
A1
e
0.22
–
Øb
0.80 BSC
0.40 TYP
Bottom View
Øb
7/2/03
DRAWING NO. REV.
48C19
TITLE
2325 Orchard Parkway
San Jose, CA 95131
48C19, 48-ball (6 x 8 Array), 0.80 mm Pitch,
6.0 x 8.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA)
A
R
26
AT49SV802A(T) [Preliminary]
3522A–FLASH–10/04
AT49SV802A(T) [Preliminary]
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
11.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
12.00
0.60
D1
E
18.50 Note 2
12.10 Note 2
0.70
L
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
48T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
27
3522A–FLASH–10/04
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3522A–FLASH–10/04
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相关型号：
AT49SV802AT-80CI
Flash, 512KX16, 80ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CBGA-48
ATMEL
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