AT75C140(256PBGA) [ATMEL]
Micro Peripheral IC,;
| 型号： | AT75C140(256PBGA) |
| 厂家： | 
ATMEL |
| 描述： | Micro Peripheral IC, ATM 异步传输模式 |
| 文件： | 总18页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– Embedded ICE (In-circuit Emulation)
• On-chip SDRAM Controller for Embedded ARM7TDMI
• Multi-layer AMBA™ Architecture
• Dual Ethernet 10/100 Mbps MAC Interface
• Two USARTs with Modem Control Lines
• Industry-standard Serial Peripheral Interface (SPI)
• Flexible External Bus Interface with Programmable Chip Selects
• Multi-level Priority, Individually-maskable, Vectored Interrupt Controller
• Three 16-bit Timer/Counters
• Additional Watchdog Timer
• Up to 48 General-purpose I/O Pins
Smart Internet
Appliance
Processor
(SIAP™)
• JTAG Debug Interface
• Software Development Tools Available for ARM7TDMI
• Supported by a Wide Range of Ready-to-use Application Software, Including Multi-
tasking Operating System and Networking Functions
• 2.5V Power Supply for the Core and PLL Pins, 3.3V for Other I/O Pins
• Available in 208-lead PQFP and in 256-ball PBGA Packages
• Supports Commercial and Industrial Temperature Range
AT75C140
Advance
Information
Description
The AT75C140 Smart Internet Appliance Processor (SIAP™) is a high-performance
processor specially designed for network-enabling consumer and industrial applica-
tions, such as printers, fax machines, industrial automation, data acquisition
equipment and test equipment.
The AT75C140 is built around an ARM7TDMI microcontroller core running at 40 MHz
with a dual Ethernet 10/100 Mbps MAC interface. The specific architecture of the
AT75C140 delivers unmatched performance for low power consumption.
On top of the AT75C140 hardware platform, Atmel provides a special port of the Linux
kernel as the proposed operating system with device drivers for the peripherals.
Rev. 2659A–INTAP–09/02
AT75C140 Pin Configuration
Table 1. AT75C140 Pinout in 208-lead PQFP Package
Pin
1
Signal
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Signal
MB_TXCLK
MB_RXD0
MB_RXD1
MB_RXD2
MB_RXD3
MB_RXER
MB_RXCLK
MB_RXDV
MB_MDC
VDD3V3
GND
Pin
85
Signal
D4
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Signal
NCE0
NCE1
NCE2
VDD3V3
NCE3
NWE0
NWE1
NWE2
VDD3V3
GND
Pin
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal
PA11
PA10
PA9
GND
2
GND
86
VDD3V3
D5
3
VDD3V3
GND
87
4
88
D6
PA8
5
NC
89
D7
PA7
6
GND
90
D8
PA6
7
NTRST
91
D9
VDD3V3
NC
8
MA_COL
MA_CRS
MA_TXER
MA_TXD0
MA_TXD1
MA_TXD2
MA_TXD3
MA_TXEN
VDD3V3
MA_TXCLK
GND
92
D10
9
93
D11
PA5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Note:
94
D12
PA4
95
D13
NWE3
NWR
PA3
MB_MDIO
MB_LINK
A0
96
D14
PA2
97
VDD2V5
GND
NSOE
GND
PA1
98
PA0
A1
99
D15
VDD2V5
NWAIT
MISO
MOSI
SPCK
NPCSS
VDD3V3
GND
GND
RXDA
TXDA
NRTSA
NCTSA
NDTRA
NDSRA
NDCDA
RXDB
TXDB
GND
PB0
A2
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VDD3V3
GND
A3
A4
NREQ
NGNT
VDD3V3
GND
MA_RXD0
MA_RXD1
MA_RXD2
MA_RXD3
MA_RXER
MA_RXCLK
GND
A5
A6
A7
A8
DCK
A9
NCS
NRESET
FIQ
A10
A10
A11
NRAS
NCAS
NC
IRQ0
VDD2V5
MA_RXDV
MA_MDC
MA_MDIO
MA_LINK
MB_COL
MB_CRS
GND
A12
TST
VDD3V3
GND
GND
PB1
NWE
VDD2V5
NC
PB2
A13
DQM0
DQM1
DQM2
GND
PB3
A14
VDD3V3
GND
PB4
A15
PB5
A16
VDD3V3
TDO
PB6
A17
DQM3
VDD2V5
GND
PB7
VDD2V5
VDD3V3
MB_TXER
MB_TXD0
MB_TXD1
MB_TXD2
GND
A18
TDI
PB8
A19
TMS
PB9
A20
PLL_VDD
XREF240
PLL_GND
GND
TCK
VDD3V3
DBW32
GND
BO256
VDD3V3
A21
PA19
D0
VDD2V5
GND
D1
D2
XTALOUT
XTALIN
VDD2V5
PA12
MB_TXD3
MB_TXEN
NC: Not connected
D3
GND
GND
VDD3V3
2
AT75C140
2659A–INTAP–09/02
AT75C140
Table 2. AT75C140 Pinout in 256-ball PBGA Package
Pin
Signal
GND
PB9
Pin
Signal
DBW32
PB6
Pin
Signal
PA30
Pin
Signal
Pin
Signal
MB_TXD2
MB_TXCLK
MB_RXD1
MB_RXER
D28
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
E02
E03
E04
E17
E18
E19
E20
F01
F02
F03
F04
F17
F18
F19
F20
G01
G02
G03
G04
G17
G18
G19
G20
H01
H02
H03
H04
H17
H18
H19
H20
J01
J02
J03
J04
J17
J18
J19
J20
K01
K02
K03
K04
K17
K18
K19
K20
L01
L02
L03
L04
L17
L18
L19
L20
M01
M02
M03
M04
M17
M18
M19
M20
N01
N02
N03
N04
N17
N18
N19
N20
P01
P02
P03
P04
P17
P18
P19
P20
R01
R02
R03
R04
R17
R18
R19
R20
NCE3
T01
T02
T03
T04
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
TST
NCE2
PB4
PB2
IRQ0
MA_RXD1
MA_RXD2
MA_RXD3
MA_RXER
VDD3V3
NCE0
PB1
NRIB
NCTSB
NRIA
NCTSA
PA0
NC
NDSRB
NRTSB
RXDB
NDSRA
TXDA
PA2
PB13
PB12
D31
GND
DCLK
NCS
VDD3V3
VDD3V3
FIQ
PA4
VDD2V5
NCE1
MB_RXD0
MB_RXD2
MB_RXCLK
GND
PA8
PA3
PA12
PA14
PA18
PA21
TCK
NC
MA_RXCLK
VDD3V3
MA_RXDV
MA_MDC
XREF240
PLL_GND
XTALOUT
XTALIN
PA6
SPCK
PA10
PA13
PA15
PA19
PA22
PA23
TDO
MA_COL
PB15
A1
VDD3V3
A8
PB14
NC
NTRST
NRESET
NPCSS
MOSI
GND
NC
A17
PA31
PB11
PA27
PA26
GND
VDD3V3
D3
MA_MDIO
MA_LINK
MB_COL
GND
NC
MISO
D7
BO256
PB8
MA_TXD0
MA_TXER
MA_CRS
GND
GND
D16
PB7
PB5
GND
VDD3V3
D22
PB3
VDD3V3
NDCDB
GND
DQM3
PB0
GND
VDD3V3
PLL_VDD
MB_CRS
VDD2V5
MB_TXD0
MB_TXD3
NRAS
GND
NDTRB
TXDB
NDCDA
NRTSA
PA1
NWAIT
VDD3V3
NSOE
MA_TXEN
MA_TXD3
MA_TXD2
MA_TXD1
NWR
D27
NDTRA
RXDA
VDD3V3
PA9
NC
D30
MB_RXD3
MB_RXDV
NC
PA5
GND
PA7
PA17
VDD3V3
PA24
GND
DQM0
A0
PA11
VDD3V3
PA16
PA20
TMS
DQM1
A4
NWE3
NC
DQM2
A7
MB_TXER
MB_TXD1
MB_TXEN
VDD3V3
VDD3V3
A10
A11
PA29
VDD3V3
IRQ1
NC
NWE2
MA_RXD0
MA_TXCLK
NC
A14
A18
TDI
A22
NC
D2
NC
GND
VDD3V3
NWE1
NWE0
D6
PB10
PA28
GND
NCAS
D10
PA25
NWE
D14
3
2659A–INTAP–09/02
Table 2. AT75C140 Pinout in 256-ball PBGA Package (Continued)
Pin
V15
Signal
Pin
Signal
A5
Pin
Signal
VDD3V3
D17
Pin
Signal
A6
Pin
Signal
D13
NC
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
V16
D19
A9
A10
A13
A16
A20
A23
D0
D15
V17
D23
A12
A15
A19
A21
D1
D20
D18
V18
D26
D24
D21
V19
NC
NREQ
NC
D25
V20
D29
NGNT
W01
W02
W03
W04
Note:
MB_MDC
NC
NC
D5
MB_MDIO
A2
D4
NC
D9
D8
MB_LINK
D12
A3
D11
NC: Not connected
Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package
Pin Name in Package Type
Active
Level
Block
256-ball PBGA
A[23:0]
D[31:0]
NREQ
208-lead PQFP
A[21:0]
D[15:0]
NREQ
Function
Type
Common Bus
Address Bus
-
Output, TS(1)
I/O(2)
Data Bus
-
Bus Request
Low
Low
-
Input
NGNT
NGNT
Bus Grant
Output
Output
Output
Output
Output
Output
Output
Output
Output, TS
Output
Output, TS
Output
Input
Synchronous Dynamic
Memory Controller
DCLK
DCLK
SDRAM Clock
DQM[3:0]
NCS
DQM[1:0]
NCS
SDRAM Byte Masks
SDRAM Chip Select
SDRAM Auto Precharge
Row Address Strobes
Column Address Strobes
SDRAM Write Enable
Chip Select
-
Low
-
A10
A10
NRAS
NRAS
Low
Low
Low
Low
Low
Low
Low
Low
NCAS
NCAS
NWE
NWE
Static Memory Controller
NCE[3:0]
NWE[3:0]
NSOE
NCE[3:0]
NWE[3:0]
NSOE
Byte Select/Write Enable
Output Enable
NWR
NWR
Memory Block Write Enable
Enable Wait States
NWAIT
NWAIT
I/O Port A
I/O Port B
PA[12:0]
PA[19]
PA[12:0]
PA[19]
I/O
General-purpose I/O lines.
Multiplexed with peripheral I/Os
-
-
PA[18:13]
PA[31:20]
-
I/O, PD(3)
I/O
PB[9:0]
PB[9:0]
-
General-purpose I/O lines.
Multiplexed with peripheral I/Os
PB[15:10]
I/O,PD
4
AT75C140
2659A–INTAP–09/02
AT75C140
Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package (Continued)
Pin Name in Package Type
Active
Level
Block
256-ball PBGA
TCLK0
TIOA0
TIOB0
TCLK1
TIOA1
TIOB1
NWDOVF
MISO
208-lead PQFP
Function
Type
Input
Timer/Counter 0
TCLK0
TIOA0
TIOB0
TCLK1
TIOA1
TIOB1
NWDOVF
MISO
MOSI
SPCK
NPCSS
NPCS1
RXDA
TXDA
NRTSA
NCTSA
NDTRA
NDSRA
NDCDA
-
Timer 0 External Clock
Timer 0 Signal A
Timer 0 Signal B
Timer 1 External Clock
Timer 1 Signal A
Timer 1 Signal B
Watchdog Overflow
Master In/Slave Out
Master Out/Slave In
Serial Clock
-
-
I/O
-
I/O
Timer/Counter 1
-
-
Input
I/O
-
I/O
Watchdog
Low
-
Output
I/O
Serial Peripheral Interface
MOSI
-
I/O
SPCK
-
I/O
NPCSS
NPCS1
RXDA
Peripheral Chip Select/Slave Select
Optional SPI Chip Select 1
Receive Data
Low
Low
-
I/O
Output
Input
USART A
TXDA
Transmit Data
-
Output
Output
Input
NRTSA
NCTSA
NDTRA
NDSRA
NDCDA
NRIA
Ready to Send
Low
Low
Low
Low
Low
Low
-
Clear to Send
Data Terminal Ready
Data Set Ready
Data Carrier Detect
Ring Indicator
Output
Input
Input
Input, PU(4)
Input
USART B
RXDB
RXDB
TXDB
-
Receive Data
TXDB
Transmit Data
-
Output
Output
Input, PU
Output
Input, PU
Input, PU
Input, PU
Input
NRTSB
NCTSB
NDTRB
NDSRB
NDCDB
NRIB
Ready to Send
Low
Low
Low
Low
Low
Low
Low
-
-
Clear to Send
-
Data Terminal Ready
Data Set Ready
Data Carrier Detect
Ring Indicator
-
-
-
JTAG Interface
NTRST
TCK
NTRST
TCK
Test Reset
Test Clock
Input
TMS
TMS
Test Mode Select
Test Data Input
-
Input
TDI
TDI
-
Input
TDO
TDO
Test Data Output
-
Output
5
2659A–INTAP–09/02
Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package (Continued)
Pin Name in Package Type
Active
Block
256-ball PBGA
208-lead PQFP
Function
Level
Type
Input
MAC A Interface
MA_COL
MA_COL
MAC A Collision Detect
MAC A Carrier Sense
MAC A Transmit Error
MAC A Transmit Data Bus
MAC A Transmit Enable
MAC A Transmit Clock
MAC A Receive Data Bus
MAC A Receive Error
MAC A Receive Clock
MAC A Receive Data Valid
MAC A Management Data Clock
MAC A Management Data Bus
MAC A Link Interrupt
MAC B Collision Detect
MAC B Carrier Sense
MAC B Transmit Error
MAC B Transmit Data Bus
MAC B Transmit Enable
MAC B Transmit Clock
MAC B Receive Data Bus
MAC B Receive Error
MAC B Receive Clock
MAC B Receive Data Valid
MAC B Management Data Clock
MAC B Management Data Bus
MAC B Link Interrupt
Ground
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MA_CRS
MA_CRS
Input
MA_TXER
MA_TXD[3:0]
MA_TXEN
MA_TXCLK
MA_RXD[3:0]
MA_RXER
MA_RXCLK
MA_RXDV
MA_MDC
MA_MDIO
MA_LINK
MA_TXER
MA_TXD[3:0]
MA_TXEN
MA_TXCLK
MA_RXD[3:0]
MA_RXER
MA_RXCLK
MA_RXDV
MA_MDC
MA_MDIO
MA_LINK
Output, TS
Output, TS
Output, TS
Input
Input
Input
Input
Input
Output, TS
I/O, PD
Input
MAC B Interface
MB_COL
MB_COL
Input
MB_CRS
MB_CRS
Input
MB_TXER
MB_TXD[3:0]
MB_TXEN
MB_TXCLK
MB_RXD[3:0]
MB_RXER
MB_RXCLK
MB_RXDV
MB_MDC
MB_MDIO
MB_LINK
MB_TXER
MB_TXD[3:0]
MB_TXEN
MB_TXCLK
MB_RXD[3:0]
MB_RXER
MB_RXCLK
MB_RXDV
MB_MDC
MB_MDIO
MB_LINK
Output, TS
Output, TS
Output, TS
Input
Input
Input
Input
Input
Output, TS
I/O, PD
Input
Power
GND
GND
Ground
Ground
Power
PLL_GND
PLL_VDD
VDD2V5
PLL_GND
PLL_VDD
VDD2V5
PLL Ground
PLL Power
2.5V Nominal Supply
3.3V Nominal Supply
Power
VDD3V3
VDD3V3
Power
6
AT75C140
2659A–INTAP–09/02
AT75C140
Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package (Continued)
Pin Name in Package Type
Active
Level
Block
256-ball PBGA
BO256
208-lead PQFP
Function
Type
Input
Miscellaneous
BO256
DBW32
FIQ/LOWP
IRQ0
Package Size Option
External Data Bus Width for NCS
Fast Interrupt/Low Power
-
-
-
DBW32
FIQ/LOWP
IRQ0
Input
Input
Input
External Interrupt Requests
-
IRQ1
-
Input, PD
Input
NRESET
TST
NRESET
TST
Power on Reset
Low
Test Mode
High
Input
XREF240
XTALIN
XREF240
XTALIN
XTALOUT
External PLL loop filter
External Crystal Input
External Crystal Output
-
-
-
Input
Input, PD
Output
XTALOUT
Notes: 1. TS: Three-state
2. I/O: Input/Output
3. PD: Internal Pull-down Resistor
4. PU: Internal Pull-up Resistor
7
2659A–INTAP–09/02
Block Diagram
Figure 1. AT75C140 Block Diagram
Dual Ethernet
10/100 Mbps
MAC Interface
ASB
Reset
Clocks
JTAG
SDRAM
Controller
External Bus
Interface
Embedded
ICE
SRAM
Controller
ARM7TDMI Core
Peripheral Data
Controller
AMBA Bridge
SPI
Advanced
Interrupt
Controller
USART A
USART B
PIO A
PIO B
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Watchdog
Timer
APB
8
AT75C140
2659A–INTAP–09/02
AT75C140
Application Example
Figure 2. Process Control
Keyboard Screen
Ethernet
Network
10/100 Mbps PHY
Dual-port
Ethernet
10/100 Mbps
MAC
SDRAM
SDRAM
Controller
Ethernet
PC
10/100 Mbps PHY
Interface
External Bus
Interface
ARM7TDMI Core
SRAM
Controller
Flash
USART
Test
Equipment
or
AT75C140
Industrial
Control
9
2659A–INTAP–09/02
Functional Description
ARM7TDMI Core
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor archi-
tecture is Von Neumann load/store architecture, characterized by a single data and
address bus for instructions and data. The CPU has two instruction sets: the ARM and
the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and pro-
vides maximum performance. Thumb instructions are 16-bit wide and give maximum
code density.
Instructions operate on 8-bit, 16-bit and 32-bit data types.
The CPU has seven operating modes. Each operating mode has dedicated banked reg-
isters for fast exception handling. The processor has a total of 37 32-bit registers,
including six status registers.
Ethernet MAC
The AT75C140 contains an Ethernet subsystem mainly composed of three independent
parts: two identical independent Ethernet MACs and a packet buffer of 32K bytes, con-
nected together with a local bus.
The Ethernet MACs exhibit the following features:
•
•
•
•
•
•
•
•
•
Support for 10 and 100 Mbps operation
Support for full- and half-duplex
Standard MII interface
Broadcast, multicast and four unicast address filters
Automatic CRC generation
Automatic zero padding
Pause and jamming support
Transmit and receive FIFOs
Integrated DMA
The local packet buffer is filled/emptied by the MACs’ DMA. This memory is used to
store the received/transmitted packets temporarily. Its size allows it to hold enough
packets to cope with most situations. Should an overflow occur, a part of the external
system memory can be used as an overflow buffer to avoid data loss.
The main benefit of having a local bus is that the majority of packets can be received
from one MAC and transmitted through the other with minor software intervention.
EBI: External Bus
Interface
The EBI generates the signals which control access to external memory or memory-
mapped peripherals. The EBI is fully programmable. The interface to external devices is
composed of common address and data buses and separate control lines to allow the
connection of static or dynamic devices.
The main common features of the EBI are:
•
•
•
External memory mapping
32- or 16-bit data bus width
Support for both static and SDRAM-type memories
10
AT75C140
2659A–INTAP–09/02
AT75C140
Various features specific to static memories or SDRAM memories are listed below.
Static Memories
SDRAM Memories
Up to four chip select lines
Byte write or byte select lines
Two different read protocols
Programmable wait state generation
Programmable data float time
Byte, half-word and word access supported
CAS latency of two clock cycles supported
Auto-precharge command
Programmable refresh rate
Supports two or four internal banks
From 256 up to 2048 columns supported
From 2048 up to 8192 rows supported
AIC: Advanced Interrupt The AT75C140 has an 8-level priority interrupt controller. The interrupt controller out-
puts are connected to the fast interrupt request (NFIQ) and the normal interrupt request
Controller
(NIRQ) of the ARM7TDMI core. The processor’s NFIQ can only be asserted by the
external fast interrupt request input (FIQ). The NIRQ line can be asserted by the inter-
rupts generated by the on-chip peripherals or by the external interrupt request line IRQ0.
An 8-level priority encoder allows the application to define the priority between the differ-
ent interrupt sources. Internal sources are programmed to be level sensitive or edge
sensitive. External sources can be programmed to be positive- or negative-edge trig-
gered, or low- or high-level sensitive.
PIO: Parallel I/O
Controller
The AT75C140 has up to 48 programmable I/O lines. They can all be programmed as
inputs or outputs. To optimize the use of available package pins, most of them are multi-
plexed with external signals of on-chip peripherals.
The PIO lines are controlled by two separate and identical PIO controllers called PIOA
and PIOB.
The PIO controllers enable the generation of an interrupt on input change on each PIO
line. Some I/O lines have enough drive capability to power a LED.
USART: Universal
Synchronous/
Asynchronous Receiver/
Transmitter
The AT75C140 provides two identical full-duplex, universal synchronous/asynchronous
receiver/transmitters that interface to the APB and are connected to the Peripheral Data
Controller.
The main features are:
•
•
•
•
•
•
•
•
Programmable baud rate generator
Parity, framing and overrun error detection
Line break generation and detection
Automatic echo, local loopback and remote loopback channel modes
Multi-drop mode: address detection and generation
Interrupt generation
Four dedicated peripheral data controller channels
6-, 7- and 8-bit character length (9 bits in multi-drop mode)
11
2659A–INTAP–09/02
SPI: Serial Peripheral
Interface
The AT75C140 includes an SPI which provides communication with external devices in
master or slave mode.
The SPI contains two dedicated peripheral data controller channels and one external
chip select which can be connected to up to 2 devices. The data length is programmable
from 8 to 16 bits.
Timer/Counter
The AT75C140 features three identical 16-bit timer/counters. They can be indepen-
dently programmed to perform a wide range of functions, including frequency
measurement, event counting, interval measurement, pulse generation, delay timing
and pulse-width modulation.
The triple timer/counter block provides three external clock inputs, five internal clock
inputs and two multi-purpose signals which can be configured by the user. Each timer
drives an internal interrupt signal which can be programmed to generate processor
interrupts via the Advanced Interrupt Controller.
Watchdog Timer
The AT75C140 is equipped with an internal Watchdog Timer that can be used to pre-
vent system lock-up if the software becomes trapped in a deadlock.
PDC: Peripheral Data
Controller
The AT75C140 is furnished with a six-channel peripheral data controller (PDC) dedi-
cated to the two on-chip USARTs and the SPI. One PDC channel is connected to the
receiver and one to the transmitter of each peripheral requiring a high data throughput.
The user interface of a PDC channel is integrated in the memory space of each USART
or SPI channel. It contains a 32-bit address pointer register and a 16-bit transfer counter
register. When the programmed number of bytes is transferred, an end-of-transfer inter-
rupt is generated by either the corresponding USART or the SPI.
Special Functions
The AT75C140 provides registers which implement the following special functions:
•
•
•
•
Chip identification
Reset status
Power management
Temperature range selection
Application Software
The AT75C140 is supported by a comprehensive range of software modules. As a result
of the widespread use of the ARM7TDMI, a wide range is available directly from Atmel,
from Atmel’s qualified software partner or from other third parties.
The application software modules are OS level.
The AT75C140 is supplied with a customized port of the Linux kernel. It features device
drivers for all the on-chip peripherals and supports file system usage. It also supports
the native TCP/IP facilities which have made Linux a success in Internet applications.
This kernel is available in source code under the terms of the Gnu Public License.
Development Tools
The ARM7TDMI is an industry-standard core. It is supported by a comprehensive range
of state-of-the-art development tools, including assemblers, C-compilers, source level
debuggers and hardware emulators.
12
AT75C140
2659A–INTAP–09/02
AT75C140
Packaging
The AT75C140 is supplied in a 208-lead PQFP package. This provides the best com-
promise between external connectivity and cost.
An alternative 256-ball PBGA package is also available. It provides the application
developer with a larger I/O capability and improved CPU performance.
Although this 256-ball PBGA package is primarily dedicated to development, it can also
be used in production for systems which require a high level of connectivity. It offers up
to 48 general-purpose I/Os and a full-width system bus (24 address bits and 32 data
bits).
13
2659A–INTAP–09/02
Package Details
Figure 3. PQFP Package Drawing
C
C1
For package data, see Table 4, Table 5 and Table 6 below.
14
AT75C140
2659A–INTAP–09/02
AT75C140
Table 4. PQFP Package Dimensions (mm)
Symbol
Min
0.11
0.11
0.65
Nom
Max
0.23
0.19
1.03
c
c1
0.15
0.88
L
L1
1.60 REF
R2
0.13
0.13
0.4
0.3
R1
S
Tolerances of Form and Position
aaa
ccc
0.25
0.10
Table 5. Dimensions specific to 208-lead PQFP Package (mm)
A
A1
A2
b
b1
D
D1
E
E1
e
ddd
BSC
0.10
Max
4.10
Min
0.25
Min
Nom
3.40
Max
Min
Max
Min
Nom
0.20
Max
BSC
31.20
BSC
BSC
31.20
BSC
28.00
BSC
0.50
3.20
3.60
0.17
0.27
0.17
0.23
28.00
Table 6. 208-lead PQFP Package Electrical Characteristics
R (mΩ)
Cs (pF)
Cm (pF)
Ls (nH)
Lm (nH)
Body
Size
Min
Max
Min
Max
Min
Max
0.73
Min
6.7
Max
Min
3.9
Max
5.1
28 x 28
53
71
1.4
1.7
0.56
8.4
15
2659A–INTAP–09/02
Figure 4. PBGA Package Drawing
b
For package data, see Table 7, Table 8 and Table 9 below.
16
AT75C140
2659A–INTAP–09/02
AT75C140
Table 7. PBGA Package Dimensions (mm)
Symbol
A1
Min
0.50
0.60
Nom
0.60
0.75
0.30
0.25
0.35
0.30
0.15
Max
0.70
0.90
Diameter B
aaa
bbb
ccc
ddd
eee
Table 8. Dimensions depending on Layer Number of the Package Board (mm)
A
Dim B
Nom
0.32
Layer
Min
1.92
2.12
Nom
2.13
2.33
Max
2.34
2.56
Min
Max
0.38
0.60
2
4
0.28
0.44
0.52
Table 9. Dimensions specific to 256-ball PBGA Package (mm)
D/E
D1/E1
e REF
Body Row Array
Min
Nom
Max
Min
Nom
Max
24.7
f REF
J/L REF
1.27
P4R
26.8
27.0
27.2
24.0
8.05
1.44
17
2659A–INTAP–09/02
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© Atmel Corporation 2002.
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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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