AT7913EKB-SV 概述
SpaceWire-Remote Terminal Controller (RTC) SpaceWire的-远程终端控制器( RTC ) 其他 uPs/uCs/外围集成电路
AT7913EKB-SV 规格参数
生命周期: | Obsolete | 零件包装代码: | CGA |
包装说明: | BGA, | 针数: | 349 |
Reach Compliance Code: | unknown | HTS代码: | 8542.31.00.01 |
风险等级: | 5.63 | Is Samacsys: | N |
JESD-30 代码: | S-PBGA-B349 | 长度: | 25 mm |
端子数量: | 349 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | BGA | 封装形状: | SQUARE |
封装形式: | GRID ARRAY | 认证状态: | Not Qualified |
座面最大高度: | 5.9 mm | 最大供电电压: | 1.95 V |
最小供电电压: | 1.65 V | 标称供电电压: | 1.8 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | MILITARY | 端子形式: | BALL |
端子节距: | 1.27 mm | 端子位置: | BOTTOM |
宽度: | 25 mm | uPs/uCs/外围集成电路类型: | MICROPROCESSOR CIRCUIT |
Base Number Matches: | 1 |
AT7913EKB-SV 数据手册
通过下载AT7913EKB-SV数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Features
• LEON2-FT Sparc V8 Processor
– 5 stage pipeline
– 4K instruction caches / 4K data caches
– Meiko FPU
– Interrupt Controller
– Uart serial links
– 32-bit Timers
– Memory interface
SpaceWire -
Remote
Terminal
– General purpose IO
– Debug Support Unit (DSU)
• FIFO interface
• ADC/DAC interface
– 24 channels
– 8bit/16bit wide data bus
• Two CAN interface
Controller (RTC)
• Two Bidirectional SpaceWire links
– Full duplex communication
– Transmit rate from 1.25 up to 200 Mbit/s in each direction
• SpaceWire Link Performance
– At 3.3V : 200Mbit/s full duplex communication
• JTAG Interface
AT7913E
ADVANCED
INFORMATION
• Operating range
– Voltages
• 1.65V to 1.95V - core
• 3V to 3.6V - I/O
– Temperature
• - 55°C to +125°C
• Maximum Power consumption
– At 3.6V with a yyyMHz clock: 150mW
• Radiation Performance
– Tested up to a total dose of 300 Krad (Si) according to the MIL-STD883 method
1019
– No single event latchup below a LET of 80 MeV/mg/cm2
• ESD better than 2000V
• Quality Grades
– QML-Q or V with SMD
• Package: 349pins MCGA
• Mass: 9grams
7833B–AERO–05/09
1
AT7913E Advanced Information
1. Description
The SpaceWire Remote Terminal Controller (RTC) device is a bridge between the
SpaceWire network and the CAN bus, providing a fully integrated system. Additional
features are provided to carter for autonomy of remote terminals and to relieve the cen-
tral processing chain of repetitive standard acquisitions and management duties. The
SpaceWire-RTC device can be used both in non-intelligent nodes and in nodes with
local intelligence.
The SpaceWire-RTC device includes an embedded microprocessor, a CAN bus control-
ler, ADC/DAC interfaces for analogue acquisition/conversion, standard interfaces and
resources (UARTs, timers, general purpose input output).
The SpaceWire-RTC device can be operated stand-alone or with a number of external
devices such as SRAM, PROM and FIFO memories, ADC and DAC converters. The
device can be managed locally by the on-chip processor, or remotely via its SpaceWire
link interfaces. SpaceWire-RTC device can operate as a single-chip system, with soft-
ware being uploaded to its on-chip memory via the SpaceWire link interface, forming a
compact solution for remotely controlled applications. Or it can operate in a full-size sys-
tem, with software being decompressed from local PROM and executed from multiple
fast and wide SRAM memory banks. The device provides scalability in terms of use of
external devices and operating frequency.
Figure 1-1. AT7913E SpaceWre RTC Block Diagram
2
7833B–AERO–05/09
2. Pin Configuration
Table 1. Pin assignment
Signal
ADAddr_0
ADAddr_1
ADAddr_2
ADAddr_3
ADAddr_4
ADAddr_5
ADAddr_6
ADAddr_7
ADCs
Pin
K5
L5
Signal
FifoP_0
FifoP_1
FifoRdN
FifoWrN
Gpio_0
Gpio_1
Gpio_2
Gpio_3
Gpio_4
Gpio_5
Gpio_6
Gpio_7
Gpio_8
Gpio_9
Gpio_10
Gpio_11
Gpio_12
Gpio_13
Gpio_14
Gpio_15
Gpio_16
Gpio_17
Gpio_18
Gpio_19
Gpio_20
Gpio_21
Gpio_22
Gpio_23
IoBrdyN
IoCsN
Pin
F6
Signal
LeonPio_15
LeonWDN
LvdsRef0
LvdsRef1
MemA_0
MemA_1
MemA_2
MemA_3
MemA_4
MemA_5
MemA_6
MemA_7
MemA_8
MemA_9
MemA_10
MemA_11
MemA_12
MemA_13
MemA_14
MemA_15
MemA_16
MemA_17
MemA_18
MemA_19
MemA_20
MemA_21
MemA_22
Pin
M9
Signal
MemD_14
MemD_15
MemD_16
MemD_17
MemD_18
MemD_19
MemD_20
MemD_21
MemD_22
MemD_23
MemD_24
MemD_25
MemD_26
MemD_27
MemD_28
MemD_29
MemD_30
MemD_31
MemOeN_0
MemOeN_1
MemOeN_2
MemOeN_3
MemWrN_0
MemWrN_1
MemWrN_2
MemWrN_3
PVDDPLL
PVSSPLL
Pin
K17
K15
K13
J19
H17
J18
J17
K11
H15
H19
J12
H18
G17
J13
H14
F15
G18
J11
Signal
Pin Signal
Pin
J15
J16
G15
F17
F18
D17
V18
V4
SpwSOut_P_0 A12 VDB22
SpwSOut_P_1 M19 VDB23
F4
N7
K2
K7
L1
F2
D11
L16
P9
SysClk
SysResetN
TapTck
TapTdi
TapTdo
TapTms
TapTrstN
VSB31
VSB32
TimeClk
TimeTrig_1
TimeTrig_2
VDA0
R1
R4
VDB24
VDB25
E4
A9
B9
C9
D9
F9
E10 VDB26
G10 VDB30
M3
L2
R8
N9
B10
C10
E9
VSA0
VSA1
VSA2
VSA3
VSA4
VSA5
VSA6
VSA7
VSA8
VSA9
L3
V9
P2
K9
M5
M1
L8
U9
W4
B18
A4
ADData_0
ADData_1
ADData_2
ADData_3
ADData_4
ADData_5
ADData_6
ADData_7
ADData_8
ADData_9
ADData_10
ADData_11
ADData_12
ADData_13
ADData_14
ADData_15
ADRc
J10
E8
B8
E7
D8
C7
G9
F8
P10
M10
W10
R9
H8
H3
J5
A16
B2
K4
M4
N3
L7
T10
R11
V10
N10
W11
U12
T11
P11
L10
R12
W12
R13
T12
U13
K3
B16
C3
V17
V16
VDA1
C17
D1
M6
N1
P5
N2
P3
N4
L9
VDA2
W3 VSA10
B17 VSA11
A7
E6
B7
C6
D7
J9
VDA3
D19
T1
P13
V14
U16
W15
V13
U14
T13
L11
VDA4
A3
VSA12
VDA5
A17 VSA13
T19
U3
VDA6
B3
B4
VSA14
VSA15
VSA16
VSA17
VSB0
VSB1
VSB2
VSB3
VSB4
VSB5
VSB6
VDA7
U17
V2
VDA8
C1
T2
P4
N6
L4
A6
F7
VDA9
C2
W16
D12
H10
H9
VDA10
VDA11
VDA12
VDA13
VDA14
VDA15
VDA16
VDA17
VDB0
C18
C19
U1
D6
C5
B6
D16
C16
B14
D15
A15
ADRdy
A14
F14
N11
P12
A10
E11
D10
ADTrig
L6
MemBExcN D14
U2
B5
ADWr
R3
E2
D4
D5
G8
MemCB_0
MemCB_1
MemCB_2
MemCB_3
MemCB_4
F19
D18
F16
RomCsN_0
RomCsN_1
SpwClk10Mbit_0
U18
U19
V3
D2
CanEn_0
CanEn_1
CanRx_0
CanRx_1
H7
IoOeN
J6
IoRead
IoWrN
E17 SpwClk10Mbit_1
E19 SpwClk10Mbit_2
W17 VSB7
G12 VSB8
K8
N5
3
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
CanTx_0
CanTx_1
FifoD_0
FifoD_1
FifoD_2
FifoD_3
FifoD_4
FifoD_5
FifoD_6
FifoD_7
FifoD_8
FifoD_9
FifoD_10
FifoD_11
FifoD_12
FifoD_13
FifoD_14
FifoD_15
FifoEmpN
FifoFullN
FifoHalfN
C4 LeonDsuAct
R7
MemCB_5
MemCB_6
MemCB_7
E16
H13
G13
SpwClkMult_0
SpwClkMult_1
SpwClkMuxSel
D13
H12
H11
VDB1
VDB2
F10
A8
G7
F1
VSB9
VSB10
VSB11
VSB12
VSB13
VSB14
VSB15
VSB16
VSB17
T3
A5 LeonDsuBre V8
P8
G4 LeonDsuEn
G2 LeonDsuRx
N8
U7
T8
M7
P7
T4
W5
T5
V6
U4
T6
W6
P6
T7
M8
V7
U6
VDB3
U8
MemCsN_0 T15 SpwClkPllCnfg_0 C14
VDB4
R10
U11
V12
R14
U15
R18
P14
N18
M16
K12
K18
J14
H16
G16
G14
F13
F3
LeonDsuTx
MemCsN_1 N12 SpwClkPllCnfg_1
MemCsN_2 T16 SpwClkPllCnfg_2
A13
E14
B13
C11
L17
B11
L18
E13
N15
B12
M18
C12
M17
A11
L19
F12
M14
VDB5
J8
G1 LeonErrorN
VDB6
H6
K6
M2
V5
F5
H4
G3
H2
G5
H1
H5
J7
LeonPio_0
LeonPio_1
LeonPio_2
LeonPio_3
LeonPio_4
LeonPio_5
LeonPio_6
LeonPio_7
LeonPio_8
LeonPio_9
LeonPio_10
MemCsN_3 N14
SpwClkSrc
SpwDIn_N_0
SpwDIn_N_1
SpwDIn_P_0
SpwDIn_P_1
SpwDOut_N_0
SpwDOut_N_1
SpwDOut_P_0
SpwDOut_P_1
SpwSIn_N_0
SpwSIn_N_1
SpwSIn_P_0
SpwSIn_P_1
SpwSOut_N_0
SpwSOut_N_1
VDB7
MemD_0
MemD_1
MemD_2
MemD_3
MemD_4
MemD_5
MemD_6
MemD_7
MemD_8
MemD_9
MemD_10
MemD_11
MemD_12
MemD_13
T17
R19
R16
P16
P19
T18
N16
P17
N19
P15
L12
K19
L15
K16
VDB8
VDB9
VDB10
VDB11
VDB12
VDB13
VDB14
VDB15
VDB16
VDB17
VDB18
VDB19
VDB20
VDB21
W8 VSB18
W9 VSB19
U10 VSB20
V11 VSB21
M11 VSB22
W13 VSB23
T14 VSB24
N13 VSB25
P18 VSB26
M12 VSB30
M13
J2
J3
J1
K1 LeonPio_11
D3 LeonPio_12
G6 LeonPio_13 W7
E1 LeonPio_14 R6
K14
4
7833B–AERO–05/09
3. Pin Description
Table 2. Pin description
Signal Name
Type
POWER
POWER
POWER
I
Function
VDB
VDA, PVDDPLL
VSA, VSB, PVSSPLL
SysClk
3.3V Power for the device
1.8V Power for the device
Ground for the device
System Clock
SysResetN
I
System Reset
LEON Error - This active low output is asserted when the
processor has entered error state and is halted. This happens
when traps are disabled and an synchronous (un-maskable)
trap occurs.
IO, open-
drain,
output
LeonErrorN
IO, open-
drain,
output
LEON watchdog - This active low output is asserted when the
watchdog times-out.
LeonWDN
DSU enable - The active high input enables the DSU unit. If
de-asserted, the DSU trace buffer will continue to operate but
the processor will not enter debug mode.
LeonDsuEn
I
DSU UART transmit - This active high output provides the
data from the DSU communication link transmitter
LeonDsuTx
LeonDsuRx
O
I
DSU UART receive - This active high input provides the data
to the DSU communication link receiver.
DSU break - A low-to-high transition on this active high input
will generate break condition and put the processor in debug
mode
LeonDsuBre
I
DSU active - This active high output is asserted when the
processor is in debug mode and controlled by the DSU.
LeonDsuAct
O
LEON Parallel Input / Output - These bi-directional signals can
be used as inputs or outputs to control external devices.
LeonPio[15:0]
IO
Gpio[23:0]
TimeClk
IO
I
General Purpose Input / Output
External timer clock
TimeTrig[2:1]
CanTx[1:0]
CanRx[1:0]
CanEn[1:0]
ADData[15:0]
ADAddr[7:0]
O
O
I
External timer trigger - Asserted for 8 system clock periods
CAN transmit
CAN receive
O
IO
IO
CAN transmit enable
ADC/DAC data
ADC/DAC address
5
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
ADWr
ADCs
O
O
O
I
DAC write strobe
ADC chip select
ADC read/convert
ADC ready
ADRc
ADRdy
ADTrig
I
ADC trigger
Memory interface address - These active high outputs carry
the address during accesses on the memory bus. When no
access is performed, the address of the last access is driven
(also internal cycles).
MemA[22:0]
MemD[31:0]
MemCB[7:0]
O
Memory interface data - MemD[31:0] carries the data during
transfers on the memory bus. The processor only drives the
bus during write cycles. During accesses to 8-bit areas, only
MemD[31:24] are used.
IO
IO
Memory interface checkbitsMemCB[6:0] carries the EDAC
checkbits, MemCB[7] takes the value of TB[7] in the error
control register. The processor only drive MemCB[7:0] during
write cycles to areas programmed to be EDAC protected
SRAM chip select - These active low signals provide an
individual output enable for each SRAM bank.
MemCsN[3:0]
MemOeN[3:0]
O
O
SRAM output enable -These active low outputs provide the
chip-select signals for each SRAM bank.
SRAM byte write strobe - These active low outputs provide
individual write strobes for each byte lane. MemWrN[0]
controls MemD[31:24], MemWrN[1] controls MemD[23:16],
etc.
MemWrN[3:0]
RomCsN[1:0]
O
O
PROM chip select - These active low outputs provide the chip-
select signal for the PROM area. RomCsN[0] is asserted when
the lower half of the PROM area is accessed (0 -
0x10000000), while RomCsN[1] is asserted for the upper half.
I/O area chip select - This active low output is the chip-select
signal for the memory mapped I/O area.
IoCsN
IoOeN
IoRead
O
O
O
I/O area output enable - This active low output is asserted
during read cycles on the memory bus.
I/O area read - This active high output is asserted during read
cycles on the memory bus.
I/O area write - This active low output provides a write strobe
during write cycles on the
IoWrN
O
I
memory bus.
I/O area ready - This active low input indicates that the access
to a memory mapped I/O area can be terminated on the next
rising clock edge.
IoBrdyN
6
7833B–AERO–05/09
Memory exception - This active low input is sampled
simultaneously with the data during
MemBExcN
I
accesses on the memory bus. If asserted,
a memory error will be generated.
FifoD[15:0]
FifoP[1:0]
IO
IO
O
O
I
FIFO data
FIFO parity
FifoRdN
FIFO read strobe
FifoWrN
FIFO write strobe
FifoFullN
FIFO full
FifoEmpN
I
FIFO empty
FifoHalfN
I
FIFO half-full, half-empty
SpaceWire transmitter clock source
SpaceWire clock configuration
SpaceWire clock configuration
SpaceWire clock configuration
SpwClkSrc
I
SpwClkMult[1:0]
SpwClk10Mbit[2:0]
SpwClkPllCnfg[2:0]
I
I
I
SpaceWire clock configuration - configuration External clock
when 1, internal PLL when 0.
SpwClkMuxSel
SpwDIn_P[1:0]
SpwDIn_N[1:0]
SpwSIn_P[1:0]
SpwSIn_N[1:0]
SpwDOut_P[1:0]
SpwDOut_N[1:0]
SpwSOut_P[1:0]
I
I, LVDS
positive
SpaceWire Data input, positive
SpaceWire Data input, negative
SpaceWire Strobe input, positive
SpaceWire Strobe input, negative
SpaceWire Data output, positive
SpaceWire Data output, negative
SpaceWire Strobe output, positive
I, LVDS
negative
I, LVDS
positive
I, LVDS
negative
O, LVDS
positive
O, LVDS
negative
O, LVDS
positive
O, LVDS
negative
SpwSOut_N[1:0]
LvdsRef[0:1]
SpaceWire Strobe output, negative
Power
LVDS reference voltage for SpaceWire channels
7
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
TAP clock - Used to clock serial data into boundary scan
latches and control sequence of the test state machine. TCK
can be asynchronous with CLK.
TapTck
I
TAP data input - Serial input data to the boundary scan
latches. Synchronous with TCK
TapTdi
I
Tap data output - Serial output data from the boundary scan
latches. Synchronous with TCK
TapTdo
O
Tap Mode select - Resets the test state machine. Can be
asynchronous with TCK. Shall be grounded for end
application.
TapTms
TapTrst
I
I
Tap Reset - Resets the test state machine. Can be
asynchronous with TCK. Shall be grounded for end
application.
8
7833B–AERO–05/09
4. Functions and Interfaces
The AT7913E SpaceWire Remote Terminal Controller (RTC) is a bridge between the
SpaceWire network and the CAN bus. The AT7913E is based on a LEON2-FT SPARC
v8 processor core together with a wide range of interfaces including :
• Debug Support Unit
• LEON2-FT Peripherals
– Interrupt Controller
– 32-bit Timer
– UART Serial Links
– 16-bit General Purpose Input Output
– Memory Interface
• On-Chip Memory
• FIFO Interface
• ADC/DAC Interface.
• 32-bit Timers
• 24-bit General Purpose Input Output
• CAN Interface
• SpaceWire Link Interface
• JTAG Interface
4.1
LEON2-FT processor
The SpaceWire-RTC ASIC includes the LEON2-FT Integer Unit (IU) and the MEIKO
Floating Point Unit (FPU). The LEON2-FT IU implements the SPARC integer instruction
set as defined in the SPARC Architecture Manual Version 8.
The LEON2-FT IU has the following features:
• 5-stage instruction pipeline
• Separate instruction and data cache interface
• Support for 8 register windows
• Multiplier 16x16
• Radix-2 divider (non-restoring)
To allow for software compatibility with existing devices such as the AT697E from Atmel,
the AT7913E SpaceWire-RTC includes all standard LEON2-FT peripherals and the
debug support unit.
The programming model of the SpaceWire-RTC device is thus compatible with the
existing devices, only requiring support for the additional functions and interfaces to be
added to the existing software development tools and operating systems.
The SpaceWire-RTC includes a LEON2-FT core with 4kbyte Instruction and Data
caches. It also includes a MEIKO FPU (the same one as included in the Atmel
AT697device).
9
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
4.2
Debug Support Unit
The AT7913E SpaceWire RTC includes a hardware debug support to aid software
debugging on target hardware. The support is provided through two modules:
• a debug support unit (DSU)
• a debug communication link
4.2.1
Debug Support Unit
The DSU can put the processor in debug mode, allowing read/write access to all pro-
cessor registers and cache memories. The DSU also contains a trace buffer which
stores executed instructions and/or data transfers on the AMBA AHB bus.
The debug support unit is used to control the trace buffer and the processor debug
mode. The DSU is attached to the AHB bus as slave, occupying a 2 Mbyte address
space. Through this address space, any AHB master can access the processor regis-
ters and the contents of the trace buffer.
The DSU control registers can be accessed at any time, while the processor registers
and caches can only be accessed when the processor has entered debug mode. The
trace buffer can be accessed only when tracing is disabled/completed. In debug mode,
the processor pipeline is held and the processor state can be accessed by the DSU.
4.2.2
Debug communication link
The SpaceWire-RTC device includes a debug support unit communication link that con-
sists of a UART connected to the AHB bus as a master. The debug communications link
implements a simple read/write protocol and uses standard asynchronous UART com-
munications. The simple communication protocol is supported to transmit access
parameters and data.
A link command consists of a control byte, followed by a 32-bit address, followed by
optional write data.
4.3
LEON2-FT Peripherals
The AT7913E SpaceWire-RTC includes all the standard LEON2-FT peripherals.
4.3.1
Interrupt Controller
The Interrupt Controller is used to priorities and propagate interrupt requests from inter-
nal or external devices to the integer unit. 15 interrupts are handled, divided on two
priority levels.
A Secondary Interrupt Controller is included to support the 32 additional interrupts used
by the additional on-chip peripherals of the AT7913E device.
4.3.2
32-bit Timer
The timer unit implements two 32-bit timers, one 32-bit watchdog and one 10-bit shared
prescaler. The functionality of the timers has not been modified with respect to existing
implementations, to allow for software compatibility.
The watchdog functionality is used for overall software timeout handling and is the basis
for error management.
10
7833B–AERO–05/09
4.3.3
4.3.4
UART Serial Links
Two identical UARTs are provided for serial communications. The UARTs support data
frames with 8 data bits, one optional parity bit and one stop bit. To generate the bit-rate,
each UART has a programmable 12-bits clock divider. Hardware flow-control is sup-
ported through handshake signals.
16-bit General Purpose Input Output
The 16-bit general purpose input output port can be individually programmed as output
or input. Two registers are associated with the operation of the port; the combined
input/output register, and direction register. When read, the input/output register will
return the current value of the port; when written, the value will be driven on the port sig-
nals. The direction register defines the direction for each individual port.
4.3.5
Memory Interface
The SpaceWire-RTC memory interface is implemented using the LEON2-FT Memory
Controller that supports the following:
• 8-bit PROM with sequential EDAC,
• 8-bit SRAM with sequential EDAC
• 32-bit PROM/SRAM with parallel-EDAC
• 8, 16, 32 bit I/O without-EDAC (wait-state and/or ready handshake)
• 16 bit GPIO (byte-wise) when less than 32 bit memory used
4.4
On-Chip Memory
The SpaceWire-RTC device includes a fault tolerant on-chip SRAM with embedded
Error Detection And Correction (EDAC) and AMBA AHB slave interface.
One error is corrected and two errors are detected, which is done by using a (32, 7)
BCH code. Some of the features available are single error counter, diagnostic reads and
writes and auto-scrubbing (automatic correction of single errors during reads).
The on-chip memory comprises a 32-bit wide memory bank of 64 kbytes of data.
4.5
4.6
FIFO Interface
This FIFO memory can be accessed as an on-chip memory or as an external interface
of the chip via the Memory Interface.
The FIFO interface supports transmission and reception of blocks of data by use of cir-
cular buffers located in memory external to the core. Separate transmit and receive
buffers are assumed. Reception and transmission of data can be ongoing
simultaneously.
ADC/DAC Interface
The SpaceWire-RTC includes a combined analogue-to-digital converter (ADC) and digi-
tal-to-analogue converter (DAC) interface.
The ADC/DAC interface provides a combined signal interface to parallel ADC and DAC
devices. The two interfaces are merged both at the pin/pad level as well as at the inter-
face towards the AMBA bus. The interface supports simultaneously one ADC device
11
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
and one DAC device in parallel. Address and data signals unused by the ADC and the
DAC can be use for general purpose input output, providing 0, 8, 16 or 24 channels.
The ADC interface supports 8 and 16 bit data widths. It provides chip select, read/con-
vert and ready signals. The timing is programmable. It also provides an 8-bit address
output. The ADC conversion can be initiated either via the AMBA interface or by internal
or external triggers. An interrupt is generated when a conversion is completed.
The DAC interface supports 8 and 16 bit data widths. It provides a write strobe signal.
The timing is programmable. It also provides an 8-bit address output.
4.7
4.8
32-bit Timers
The SpaceWire-RTC includes a General Purpose Timer Unit that implements one pres-
caler and two 32-bit decrementing timers.
24-bit General Purpose Input Output
The SpaceWire-RTC includes a 24-bit General Purpose Input Output core. The AMBA
APB bus is used for control and status handling.
The core provides 24 channels. Each channel is individually programmed as input or
output. Additionally, 8 of the channels are also programmable as pulse command out-
puts. The default reset configuration for each channel is as input. The default reset
value each channel is logical zero.
The pulse command outputs have a common 20-bit counter for establishing the pulse
command length. The pulse command length defines the logical one (active) part of the
pulse. It is possible to select which of the channels shall generate a pulse command.
The pulse command outputs are generated simultaneously in phase with each other,
and with the same length (or duration). It is not possible to generate pulse commands
out of phase with each other.
4.9
CAN Interface
The SpaceWire-RTC includes a CAN controller. The CAN protocol is based on the ESA
HurriCANe CAN Controller VHDL core.
The controller uses the AMBA APB bus for configuration, control and status handling.
The AMBA AHB bus is used for retrieving and storing CAN messages in memory exter-
nal to the CAN controller. This memory can be located on-chip or external to the chip.
The CAN controller supports transmission and reception of sets of messages by use of
circular buffers located in memory external to the core. Separate transmit and receive
buffers are assumed. Reception and transmission of sets of messages can be ongoing
simultaneously.
4.10 SpaceWire Link Interface
The SpaceWire (SPW2) Module is used for transmitting and receiving data over a
SpaceWire link. It provides support for transmitting any type of protocol or data structure
using SpaceWire packets.
12
7833B–AERO–05/09
It provides hardware support for receiving two types of SpaceWire Transfer Protocols,
and can relay packets of other protocols to software. The SpaceWire Virtual Channel
Transfer Protocol (VCTP) implements multiple virtual channels (only one implemented
in SpaceWire-RTC) on a single SpaceWire link. The Remote Memory Access Protocol
(RMAP) implements remote memory access to resources in the node via
the SpaceWire link.
Data received over the link by the SpaceWire CODEC are temporarily stored in an
RxFIFO. Data are then stored to memory by the SpaceWire Module via direct memory-
access. Multiple Virtual Receive Channels (RxVC) can be used, each with its private
memory area to which data are written. In SpaceWire-RTC one channel (RxVC(1)) is
used for storing VCTP packets, and one channel (RxVC(0)) is used for storing RMAP
responses, RMAP commands not supported by hardware and packets of other types of
Transfer Protocols.
All RxVC share the same link. The SpaceWire Module implements hardware support for
the RMAP. RMAP is used for remotely accessing resources on the local AMBA bus. The
RMAP implementation can receive commands and generate responses, utilizing the
aforementioned RxFIFO and the TxFIFO.
Data to be sent are read by the SpaceWire Module from memory via direct memory
access. Data are then temporarily stored in a TxFIFO when forwarded to the SpaceWire
CODEC for transmission over the link. Multiple Virtual Transmit Channels (TxVC) can
be used, each with its private send list stored in memory from which data are read. In
SpaceWire-RTC one channel (TxVC(0)) is used for automatic RMAP responses, and
another channel (TxVC(1)) is used for transmissions set up by the user. All TxVC share
the same link. RMAP responses have priority over transmissions set up by the user. The
arbitration is performed for each packet sent.
4.11 JTAG Interface
The JTAG interface (compliant with IEEE-Std-1149.1) is used for the purpose of bound-
ary scan testing during manufacture and test of printed circuit boards hosting the ASIC.
13
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
5. Typical Applications
The capabilities of the SpaceWire-RTC device are not limited to support the CAN bus in
the instrument controller unit (ICU), but also allows it to be used in an on-board com-
puter (OBC).
The AT7913E SpaceWire RTC is perfectly suited for application requiring cost optimiza-
tions as it can be used in both payload and avionics.
5.1
5.2
AT7913E in ICU
AT7913E in OBC
The SpaceWire-RTC device can be integrated in the instrument controller Unit (ICU)
that acts as the payload data processor and mainly receives payload data from instru-
ments and produces processed data to be down linked. The main data communication
is performed via the SpaceWire network. The ICU is however controlled and monitored
via the CAN network from the On-Board Computer (OBC).
The CAN controller in the SpaceWire-RTC device acts as a remote terminal that is
being managed by the OBC. Alternatively, the SpaceWire-RTC device can be integrated
in the On-Board Computer (OBC). Since the OBC acts as the network manager on the
CAN network, the CAN controller carters capability such as node management and time
distribution. The OBC also communicates or manages the SpaceWire network via
SpaceWire links.
5.3
AT7913E on payload
The main application of the SpaceWire-RTC device is however in instruments or individ-
ual experiments of the payload. It provides an abundance of interfaces, each with a high
degree of programmability and configurability. It is able to acquire analogue and digital
data, generated by connected peripherals and to generate discrete commands towards
the same peripherals.
14
7833B–AERO–05/09
6. Electrical Characteristics
6.1
Absolute Maximum Ratings
Table 6-1.
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply Voltage - 1.8V Core Voltage
VDA
-0.3 to +2.0
V
Supply Voltage - 3.3V I/O Voltage
I/O Input Voltage
VDB
Tstg
-0.3 to +4.0
-0.3 to 4.0
-55 to +125
-65 to +150
>1000
V
V
Operating Temperature Range
Storage Temperature Range
ESD for PLL
°C
°C
V
ESD for I/O
>2000
V
Stresses above those listed may cause permanent damage to the device.
6.2
DC Electrical Characteristics
Table 6-2.
3.3V operating range DC Characteristics.
Parameter
Symbol
VCA
VCB
VIH
Min.
1.65
Max.
1.95
Unit
Conditions
Operating Voltage
V
3.0
2.0
3.6
0.8
0.4
V
V
V
V
V
Input HIGH Voltage
Input LOW Voltage
VIL
Output HIGH Voltage
Output LOW Voltage
Output Short circuit current
VOH
VOL
IOS
2.4
IOL = 3, 6, 12mA / VCC = VCC(min)
IOH = 3, 6, 12mA / VCC = VCC(min)
50
mA
mA
VOUT = VCC
VOUT = GND
100
6.3
AC Electrical Characteristics
The following table gives the worst case timings measured by Atmel on the 3.0V to 3.6V
operating range
Table 6-3.
3.3V operating range timings
Parameter
Symbol
Min.
Max.
Unit
Propagation delay, SysClk rising to MemCsN_0
falling
Tp0
18
ns
Propagation delay, SysClk rising to CanTx_0
rising
Tp1
Tp2
29
25
ns
ns
Propagation delay, SysClk rising to Gpio_22 rising
15
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
Propagation delay, SysClk rising to FifoD_1 rising
Tp3
Tp4
16
14
ns
ns
Propagation delay, SpwClkSrc rising to
SpwDout_P_0 falling
Propagation delay, SpwClkSrc rising to
SpwDout_N_0 rising
Tp5
14
ns
For guaranteed timings on the two operating voltage ranges, refer to the section XXX of
the ‘SpaceWire-RTC (SpwRtc) Datasheet’
16
7833B–AERO–05/09
7. Package Drawings
7.1
MCGA349
Here is a presentation of the mechanical outline of the 349 pins Ceramic Quad Flat Pack
(MCGA 349) package used for the AT7913E
Figure 7-1. MCGA349 package
17
AT7913E Advanced Information
7833B–AERO–05/09
AT7913E Advanced Information
8. Ordering Information
Part-number
Temperature Range
Package
Quality Flow
AT7913EKB-E
25°C
MCGA349
Engineering sample
AT7913EKB-MQ
AT7913EKB-SV
-55°C to +125°C
-55°C to +125°C
MCGA349
MCGA349
Mil Level B (*)
Space Level B (*)
(*) according to Atmel Quality flow document 4288, see Atmel web site.
18
7833B–AERO–05/09
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