AT83C24-TISIM [ATMEL]
Smart Card Reader Interface with Power Management; 与电源管理智能卡读卡器接口
| 型号： | AT83C24-TISIM |
| 厂家： | 
ATMEL |
| 描述： | Smart Card Reader Interface with Power Management |
| 文件： | 总42页 (文件大小：726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Smart Card Interface
– Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL Standards
Card Clock Stop High or Low for Card Power-down Modes
Support Synchronous Cards with C4 and C8 Contacts
Card Detection and Automatic de-activation Sequence
Programmable Activation Sequence
– Direct Connection to the Smart Card
Logic Level Shifters
Short Circuit Current Limitation (see electrical characteristics)
8kV+ ESD Protection (MIL/STD 883 Class 3)
– Programmable Voltage
Smart Card
Reader
5V ±5% at 65 mA (Class A)
3V ±0.2V at 65 mA (Class B)
1.8V ±0.14V at 40 mA
Interface with
Power
– Low Ripple Noise: < 200 mV
• Versatile Host Interface
– ICAM (Conditional Access) Compatible
– Two Wire Interface (TWI) Link
Programmable Address Allow up to 8 Devices
– Programmable Interrupt Output
Management
– Automatic Level Shifter (1.6V to VCC
)
• Reset Output Includes
– Power-On Reset (POR)
– Power-Fail Detector (PFD)
AT83C24
• High-efficiency Step-up Converter: 80 to 98% Efficiency
• Extended Voltage Operation: 3V to 5.5V
• Low Power Consumption
AT83C24NDS
– 180 mA Maximum In-rush Current
– 30 µA Typical Power-down Current (without Smart Card)
• 4 to 48 MHz Clock Input, 7 MHz Min for Step-up Converter (for AT83C24)
• 18 to 48MHz Clock input (for AT83C24NDS)
• Industrial Temperature Range: -40 to +85°C
• Packages: SO28 and QFN28
Description
The AT83C24 is a smart card reader interface IC for smart card reader/writer applica-
tions such as EFT/POS terminals and set top boxes. It enables the management of
any type of smart card from any kind of host. Up to 8 AT83C24 can be connected in
parallel using the programmable TWI address.
Its high efficiency DC/DC converter, low quiescent current in standby mode makes it
particularly suited to low power and portable applications. The reduced bill of material
allows reducing significantly the system cost. A sophisticated protection system guar-
antees timely and controlled shutdown upon error conditions.
The AT83C24NDS is a dedicated version approved by NDS for use with NDS Video-
Guard conditional access software in set-top boxes. All AT83C24 datasheet is
applicable to AT83C24NDS. The main differences between AT83C24 and
AT83C24NDS are listed below:
1/ CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS,
CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24
2/ 18MHz minimum on input clock for AT83C24NDS
3/ Up to 10µF for capacitor connected on CVCC pin for AT83C24,
3.3µF mandatory for AT83C24NDS
4234E–SCR–09/04
1
Acronyms
TWI: Two-wire Interface
POR: Power On Reset
PFD: Power Fail Detect
ART: Automatic Reset Transition
ATR: Answer To Reset
MSB: Most Significant Bit
LSB: Least Significant bit
SCIB: Smart Card Interface Bus
Block Diagram
VCC
VSS
CVSS
LI
DVCC
CVCC
Voltage
supervisor
POR/PFD
DC/DC
Converter
CVCCIN
EVCC
RESET
PRES/ INT
A2/CK, A1/RST, A0/3V, CMDVCC
Main
Control
& Logic Unit
TWI
Controller
Timer
16 Bits
SCL
SDA
Clocks Controller
Analog
Drivers
CPRES
CRST
CLK
CIO, CC4, CC8
CCLK
I/O, C4, C8
2
AT83C24
4234E–SCR–09/04
AT83C24
Pin Description
Pinouts (Top View)
28-pin SOIC Pinout
QFN28 pinout
CLK
C8
28
1
2
DVCC
27
26
25
PRES/INT
C4
RESET
3
4
24
25
26
23 22
21
27
28
EVCC
1
I/O
CMDVCC
CMDVCC
VSS
20
19
18
EVCC
2
3
4
24
23
22
21
20
19
18
17
VSS
VCC
5
6
A2
A1
/CK
/RST
/3V
/CK
A2
VCC
CVSS
LI
QFN 28
/RST
/3V
A1
A0
7
8
CVSS
LI
A0
TOP VIEW
17
16
5
6
7
SCL
SDA
NC
9
SCL
SDA
CVCC
CVCC
10
CVCCin
15
CVCCin
8
9
14
12 13
11
11
12
13
NC
CIO
10
CRST
CCLK
NC
CC8
16
15
CPRES
14
CC4
Note:
1. NC = Not Connected
2. SOIC and QFN packages are available for AT83C24 and for AT83C24NDS
Signals
Table 1. Ports Description
Pad Name
Pad Internal
ESD
Pad
Power Supply
Limits
Type
Description
Microcontroller Interface Function:
TWI bus slave address selection input.
A2/CK and A1/RST pins are respectively connected to CCLK and CRST signals in
“transparent mode” (see page 18 ).
A2/CK-
A1/RST-
A0/3V
EVCC
3 kV
I
A0/3V is used for hardware activation to select CVCC voltage (3V or 5V).
The slave address of the device is based on the value present on A2, A1, A0 on the
rising edge of RESET pin (see Table 2). In fact, the address is taken internally at the 11th
CLK rising edge.
Microcontroller Interface Function:
Depending on IT_SEL value (see CONFIG4 register),
PRES/INT outputs card presence status or interruptions (page 9)
O
3 kV
PRES/INT
EVCC
open-
drain
An internal Pull-up (typ 330kΩ,see Table 18)to EVCC can be activated in the pad if
necessary using INT_PULLUP bit (CONFIG4 register).
Remark: during power up and before registers configuration, the PRES/INT signal must
be ignored.
Microcontroller Interface Function:
•
•
Power-on reset
A low level on this pin keeps the AT83C24 under reset even if applied on power-on.
It also resets the AT83C24 if applied when the AT83C24 is running (see Power
monitoring §).
I/O
3 kV
open-
drain
RESET
VCC
•
•
Asserting RESET when the chip is in Shut-down mode returns the chip to normal
operation.
AT83C24 is driving the Reset pin Low on power-on-reset or if power fail on VCC or
DVCC (see POWERMON bit in CONFIG4 register), this can be used to reset or
interrupt other devices. After reset, AT83C24 needs to be reconfigured before
starting a new card session.
3
4234E–SCR–09/04
Table 1. Ports Description (Continued)
Pad Name
Pad Internal
ESD
Pad
Power Supply
Limits
Type
Description
I/O
3 kV
3 kV
Microcontroller Interface Function
TWI serial data
SDA
SCL
VCC
VCC
open-
drain
I/O
Microcontroller Interface Function
TWI serial clock
open-
drain
Microcontroller Interface Function
Copy of CIO pin and high level reference for EVCC.
An external pull up to EVCC is needed on IO pin.
I/O is the reference level for EVCC if EVCC is connected to a capacitor.
This feature is unused if EVCC is connected to VCC.
3 kV
I/O
EVCC
I/O
I/O
3 kV
3 kV
3 kV
Microcontroller Interface Function
C4
C8
EVCC
EVCC
EVCC
CVCC
CVCC
CVCC
(pull-up) Copy of Card CC4.
I/O
Microcontroller Interface Function
(pull-up) Copy of Card CC8.
Microcontroller Interface Function
CLK
CIO
CC4
CC8
I
Master Clock
I/O
Smart card interface function
8 kV+
8 kV+
8 kV+
(pull-up) Card I/O
I/O
Smart card interface function
(pull-up) Card C4
I/O
Smart card interface function
(pull-up) Card C8
Smart card interface function
I
Card presence
CPRES
VCC
8 kV+
(pull-up)
An internal Pull-up to VCC can be activated in the pad if necessary using PULLUP bit
(CONFIG1 register).
Smart card interface function
Card clock
CCLK
CRST
CVCC
CVCC
8 kV+
8 kV+
3 kV+
O
O
Smart card interface function
Card reset
I
Microcontroller Interface Function:
CMDVCC
VCC
EVCC
(pull-up)
Activation/Shutdown of the smart card Interface.
Supply Voltage
3 kV+
3 kV+
PWR
PWR
VCC is used to power the internal voltage regulators and I/O buffers.
DC/DC Input
LI must be tied to VCC pin through an external coil (typically 4.7 µH) and provides the
current for the charge pump of the DC/DC converter.
LI
It may be directly connected to VCC if the step-up converter is not used (see STEPREG
bit in CONFIG4 register and see minimum VCC values in Table 20 (class A) and
Table 21 (class B)).
4
AT83C24
4234E–SCR–09/04
AT83C24
Table 1. Ports Description (Continued)
Pad Name
Pad Internal
ESD
Pad
Power Supply
Limits
Type
Description
Card Supply Voltage
CVCC
8 kV+
8 kV+
PWR
PWR
CVCC is the programmable voltage output for the Card interface.
It must be connected to external decoupling capacitors (see page 35 and page 36).
Card Supply Voltage
CVCCin
This pin must be connected to CVCC.
Digital Supply Voltage
Is internally generated and used to supply the digital core.
DVCC
EVCC
3 kV+
PWR
PWR
This pin has to be connected to an external capacitor of 100 nF and should not be
connected to other devices.
Extra Supply Voltage (Microcontroller power supply)
EVCC is used to supply the internal level shifters of host interface pins.
EVCC voltage can be supplied from the external EVCC pin connected to the host power
supply.
3 kV+
If EVCC cannot be connected to the host power supply, it must be tied to an external
capacitor. EVCC voltage can be generated internally by an automatic follow up of the
logic high level on the I/O pin. In this configuration, connect a 100 nF + 100kOhms in
parallel between EVCC pin and VSS pin.
DC/DC Ground
CVSS
VSS
8 kV+
Note:
GND
GND
CVSS is used to sink high shunt currents from the external coil.
Ground
ESD Test conditions: 3 positive and 3 negative pulses on each pin versus GND. Pulses
generated according to Mil/STD 883 Class3. Recommended capacitors soldered on
CVCC and VCC pins.
5
4234E–SCR–09/04
Operational Modes
TWI Bus Control
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 Kbits per sec-
ond, based on a byte-oriented transfer format.
The TWI-bus interface can be used:
–
–
–
–
–
–
–
To configure the AT83C24
To select the operating mode of the card: 1.8V, 3V or 5V
To configure the automatic activation sequence
To start or stop sessions (activation and de-activation sequences)
To initiate a warm reset
To control the clock to the card in active mode
To control the clock to the card in stand-by mode (stop LOW, stop HIGH or
running)
–
–
–
To enter or leave the card stand-by or power-down modes
To select the interface (connection to the host I/O / C4/ C8)
To request the status (card present or not, over-current and out of range
supply voltage occurrence)
–
–
To drive and monitor the card contacts by software
To accurately measure the ATR delay when automatic activation is used
TWI Commands
Frame Structure
The structure of the TWI bus data frames is made of one or a series of write and read
commands completed by STOP.
Write commands to the AT83C24 have the structure:
ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S)
Read commands to the AT83C24 have the structure:
ADDRESS BYTE + DATA BYTE(S)
The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each reset
(hard/soft/general call) but A2/CK, A1/RST, A0/3V can be used for transparent mode
after the reset.
Figure 1. Data transfer on TWI bus
acknowledgement
from slave
SDA
SCL
Adresse byte
command
and/or data
5
7
8
1
2
3
4
6
9
start condition
stop condition
6
AT83C24
4234E–SCR–09/04
AT83C24
Address Byte
The first byte to send to the device is the address byte. The device controls if the hard-
ware address (A2/CK, A1/RST, A0/3V pins on reset) corresponds to the address given
in the address byte (A2, A1, A0 bits).
If the level is not stable on A2/CK pin (or A1/RST pin, or A0/3V pin) at reset, the user
has to send the commands to the possible address taken by the device.
If A2/CK to A0/3V are tied to the host microcontroller and their reset values are
unknown, a general call on the TWI bus allows to reset all the AT83C24 devices and set
their address after A2/CK to A0/3V are fixed.
Figure 2. Address Byte
b4
0
b0
b7
0
b6
1
b5
0
b3
b2
b1
A1
R/W
A2
A0
Slave Address on 7 Bits
1 for READ Command
0 for WRITE Command
Up to 8 devices can be connected on the same TWI bus. Each device is configured with
a different combination on A2/CK, A1/RST, A0/3V pins. The corresponding address
byte values for read/write operations are listed below.
Table 2. Address Byte Values
Address Byte
for
Address Byte
for
A2
A1
A0
(A2/CK pin)
(A1/RST pin)
(A0/3V pin)
Read
Write
Command
Command
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0x41
0x43
0x45
0x47
0x49
0x4B
0x4D
0x4F
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
7
4234E–SCR–09/04
Write Commands
The write commands are:
1. Reset:
Initializes all the logic and the TWI interface as after a power-up or power-fail reset.
If a smart card is active when RESET falls, a deactivation sequence is performed.
This is a one-byte command.
2. Write Config:
Configures the device according to the last six bits in the CONFIG0 register and to
the following four bytes in CONFIG1, CONFIG2, CONFIG3 then CONFIG4 regis-
ters. This is a five bytes command.
Figure 3. Command byte format for Write CONFIG0 command
b7
1
b6
0
b5
X
b4
X
b3
X
b2
X
b1
X
b0
X
CONFIG0 on 6 Bits
3. Write Timer:
Program the 16-bit automatic reset transition timer with the following two bytes. This
is a three bytes command.
4. Write Interface:
Program the interface. This is a one-byte command. The MSB of the command byte
is fixed at 0.
5. General Call Reset:
A general call followed by the value 06h has the same effect as a Reset command.
Table 3. Write Commands Description
Address Byte
Data Byte Data Byte Data Byte Data Byte
(See Table 2) Command Byte
1
2
3
4
1. Reset
0100 A2A1A00 1111 1111
(10 + CONFIG0 6
0100 A2A1A00
bits)
CONFIG1 CONFIG2 CONFIG3 CONFIG4
TIMER1 TIMER0
2. Write config
3. Write Timer
0100 A2A1A00 1111 1100
(0+INTERFACE 7
0100 A2A1A00
bits)
4. Write Interface
5. General Call
Reset
0000 0000
0000 0110
8
AT83C24
4234E–SCR–09/04
AT83C24
Read Command
After the slave address has been configured, the read command allows to read one or
several bytes in the following order:
•
STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1,
TIMER0, CAPTURE1, CAPTURE0
•
FFh is completing the transfer if the microcontroller attempts to read beyond the last
byte.
Note:
Flags are only reset after the corresponding byte read has been acknowledged by the
master.
Table 4. Read Command Description
Byte Description
Address byte
Data byte 1
Data byte 2
Data byte 3
Data byte 4
Data byte 5
Data byte 6
Data byte 7
Data byte 8
Data byte 9
Data byte 10
Data byte 11
Data byte 12
Byte Value
0100 A2A1A01
STATUS
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
INTERFACE
TIMER 1 (MSB)
TIMER 0 (LSB)
CAPTURE 1 (MSB)
CAPTURE 0 (LSB)
0xFF
Interrupts
The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register).
•
If IT_SEL= 0, the PRES/INT output is High by default (on chip pull up or open drain).
PRES/INT is driven Low by any of the following event:
–
INSERT bit set in CONFIG0 register (card insertion/extraction or bit set by
software )
–
VCARD_INT bit set in STATUS register (the DC/DC output voltage has
settled)
–
–
over-current detection on CVCC
VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or
bit set by software)
–
ATRERR bit set in CONFIG0 register (no ATR before the card clock counter
overflows or bit set by software).This control of ATR timing is only available if
ART bit =1.
If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will
release PRES/INT pin to high level.
Several AT83C24 devices can share the same interrupt and the microcontroller can
identify the interrupt sources by polling the status of the AT83C24 devices using
TWI commands.
9
4234E–SCR–09/04
•
If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with
existing devices) the PRES/INT output is High to indicate a card is present and none
of the following event has occured:
–
–
over-current detection on CVCC
VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or
bit set by software)
Card Presence Detection
The card presence is provided by the CPRES pin. The polarity of card presence contact
is selected with the CARDDET bit (see CONFIG1 register). A programmable filtering is
controlled with the CDS[2-0] bits (see CONFIG1 register).
An internal pull-up on the CPRES pin can be disconnected in order to reduce the con-
sumption, an external pull-up must then be connected to VCC. The PULLUP bit (see
CONFIG1 register) controls this feature.
The card presence switch is usually connected to Vss (card present if CPRES=1). The
CARDDET bit must be set. The internal pull up can be connected.
If the card presence contact is connected to Vcc (card present if CPRES=0), the internal
pull-up must be disconnected (see PULLUP bit) and an external pull-down must be con-
nected to the CPRES pin.
An interrupt can be generated if a card is inserted or extracted (see interrupts §).
Figure 4. Card Presence Input
VCC
External
Pull-up
VCC
(See Table 18)
Card
Internal
Pull-up
Contact
PULLUP Bit
CARDDET Bit
Presence
= 1 No Card if CPRES = 0
= 0 No Card if CPRES = 1
= 1 Closed
= 0 Open
VSS
CPRES
FILTERING
VCC
EVCC
= 1 Closed
= 0 Open
CDS[2-0]
Card
CARDIN bit
INT_PULLUP Bit
Contact
IT_SEL Bit
Presence
= 1 Card Inserted
= 0 No Card
PRES/INT
External
Pull-down
IT Controller
VSS
10
AT83C24
4234E–SCR–09/04
AT83C24
CIO, CC4, CC8 Controller
The CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4,
CARDC8 bits values or by I/O, C4, C8 signal pins. This selection depends of the IODIS
bit value. If IODIS is reset, data are bidirectional between respectively I/O, C4, C8 pins
and CIO, CC4, CC8 pins.
Figure 5. CIO, CC4, CC8 Block Diagram
CVCC
I/O
0
CIO
EVCC
EVCC
1
CARDIO bit
CVCC
CVCC
C4
C8
0
CC4
CC8
1
CARDC4 bit
CARDC8 bit
0
1
IODIS bit
IO and CIO pins are linked together through the on chip level shifters if IODIS bit=0 in
INTERFACE register. This is done automatically during an hardware activation.
Their iddle level are 1. With IO high, CIO is pulled up.
The same behavior is applicable on C4/ CC4 and C8/ CC8 pins.
The maximum frequency on those lines depends on CLK frequency (3 clock rising
edges to transfer). With CLK=27MHz, the maximum frequency on this line is 1.5MHz.
Due to the minimum transfer delay allowed for NDS applications, the CLK minimum fre-
quency is 18MHz.
Clock Controller
The clock controller generates two clocks (as shown in Figure 6 and Figure 7):
1. a clock for the CCLK: Four different sources can be used: CLK pin, DCCLK sig-
nal, CARDCK bit or A2/CK pin (in transparent mode).
2. a clock for DC/DC converter.
11
4234E–SCR–09/04
Figure 6. Clock Block Diagram with Software Activation (see page 14)
DCCLK
CLK
DCK[2:0]
DC/DC
CKS[2:0]
0
A2/CK
CCLK
1
CARDCK bit
CKSTOP bit
Figure 7. Clock Block Diagram with Hardware Activation (see page 14)
DCCLK
CLK
DCK[2:0]
DC/DC
CKS[2:0]
0
A2/CK
CCLK
1
CARDCK bit
CMDVCC
A1/RST
Hardware
activation
CKSTOP bit
CRST_SEL bit
CRST Controller
The CRST output pin is driven by the A1/RST pin signal pin or by the CARDRST bit
value. This selection depends of the CRST_SEL bit value (see CONFIG4 register).
If the CRST pin signal is driven by the CARDRST bit value, two modes are available:
•
•
If the ART bit is reset, CRST pin is driven by CARDRST bit.
If the ART bit is set, CRST pin is controlled and follows the “Automatic Reset
Transition” (page 15).
12
AT83C24
4234E–SCR–09/04
AT83C24
Figure 8. CRST Block Diagram with soft activation
0
1
CARDRST bit
tb delay
see Fig 12
0
1
CRST
ART bit
CRST_SEL bit = 0
Figure 9. CRST Block Diagram with Hardware Activation (CMDVCC pin used)
0
CARDRST bit
1
0
CRST
ART bit
A1/RST
1
CMDVCC
Hardware
activation
CRST_SEL bit = 1
CMDVCC
deactivation
activation
13
4234E–SCR–09/04
Activation Sequence
Hardware Activation (DC/DC started with CMDVCC)
Initial conditions:
CARDDET bit must be configured in accordance to the smart card connector polarity.
IT_SEL bit, CRST_SEL bit (see CONFIG4 register) must be set and CARDRST bit (see
INTERFACE register) must be cleared. A smart card must be detected to enable to start
the DC/DC (CVCC= 3V or 5V).
The hardware activation sequence is started by hardware with CMDVCC pin going high
to low. It follows this automatic sequence:
•
•
•
CIO / CC4 / CC8 and IO / C4 / C8 are respectively linked together (IODIS bit is
cleared).
The DC/DC is started and CVCC is set according to the A0/3V pin: 5V (Class A) if
A0/3V is High and 3V (Class B) is A0/3V is Low.
CCLK signal is enabled (CKSTOP bit cleared) when CVCC has settled to the
programmed voltage (see Electrical Characteristics) and the level on A1/RST is 0.
The CCLK source can be DCCLK signal, CLK signal , A2/CK signals or CARDCK bit
(see Figures 5).
•
CRST signal is linked with A1/RST pin as soon as A1/RST pin level is 0. A rising
edge on A1/RST pin set the CRST pin.
Note:
1. The card must be deactivated to change the voltage.
Figure 10. Activation sequence with CMDVCC
CMDVCC
A1/RST
CCLK
CVCC
CRST
CIO
Note:
For NDS applications, the host usually starts activation with A1/RST = 0.
14
AT83C24
4234E–SCR–09/04
AT83C24
Software Activation (DC/DC Started With Writing in VCARD[1:0] bits) and ART bit = 1
Initial conditions: CARDRST bit = 0, CKSTOP bit =1, IODIS bit = 1.
The following sequence can be applied:
1. Card Voltage is set by software to the required value (VCARD[1:0] bits in
CONFIG0 register). This writing starts the DC/DC.
2. Wait the end of the DC/DC init with a polling on VCARDOK bit (STATUS reg-
ister) or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in
CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit
should be set by software.
3. CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have
the clock running. IODIS is reset to drive the I/O, C4, C8 pins and the
CIO,CC4, CC8 pins according to each other.
4. CARDRST bit (see INTERFACE register) is set by software.
Automatic Reset Transition description:
A 16-bit counter starts when CARDRST bit is set. It counts card clock cycles. The CRST
signal is set when the counter reaches the TIMER[1-0] value which corresponds to the
“tb” time (Figure 11).The counter is reseted when the CRST pin is released and it is
stopped at the first start bit of the Answer To Request (ATR) on CIO pin.
The CIO pin is not checked during the first 200 clock cycles (ta on Figure 11). If the ATR
arrives before the counter reaches Timer[1-0] value, the activation sequence fails, the
CRST signal is not set and the Capture[1-0] register contains the value of the counter at
the arrival of the ATR.
If the ATR arrives after the rising edge on CRST pin and before the card clock counter
overflows (65535 clock cycles), the activation sequence completes. The Capture[1-0]
register contains the value of the counter at the arrival of the ATR (tc time on Figure 11).
15
4234E–SCR–09/04
Figure 11. Software activation with ART bit = 1
CARDRST bit set
CVCC
4
3
1
CRST
CCLK
CIO
ta
2
tb
tc
ISO 7816 constraints: ta = 200 card clock cycles
400 card clock cycles< = tb
400 card clock cycles< = tc < = 40000 card clock cycles
Timer[1-0] reset value is 400.
Note:
Software Activation (DC/DC Started by Writing in VCARD[1:0] bits) and ART bit = 0
The activation sequence is controlled by software using TWI commands, depending on
the cards to support. For ISO 7816 cards, the following sequence can be applied:
1. Card Voltage is set by software to the required value (VCARD[1:0] bits in
CONFIG0 register). This writing starts the DC/DC.
2. Wait of the end of the DC/DC init with a polling on VCARDOK bit (STATUS
register) or wait for PRES/INT to go Low if enabled (if IT_SEL bit = 0 in
CONFIG4 register). When VCARDOK bit is set (by hardware), CARDIO bit
should be set by software.
3. CKSTOP, IODIS are programmed by software. CKSTOP bit is reset to have
the clock running. IODIS is reset to drive the I/O, C4, C8 pins and the
CIO,CC4, CC8 pins according to each other.
4. CRST pin is controlled by software using CARDRST bit (see INTERFACE
register).
16
AT83C24
4234E–SCR–09/04
AT83C24
Figure 12. Software activation without automatic control (ART bit = 0)
CVCC
4
1
CRST
CCLK
CIO
3
ATR
2
Note:
Note:
It is assumed that initially VCARD[1:0], CARDCK, CARDIO and CARDRST bits are
cleared, CKSTOP and IODIS are set (those bits are further explained in the registers
description)
The user should check the AT83C24 status and possibly resume the activation sequence
if one TWI transfer is not acknowledged during the activation sequence.
Deactivation Sequence
The card automatic deactivation is triggered when one the following condition occurs:
•
•
•
•
•
•
•
ICARDERR bit is set by hardware
VCARDERR bit is set by hardware (or by software)
INSERT is set and CARDIN is cleared (card extraction)
SHUTDOWN is set by software
CMDVCC goes from Low to High
Power fail on VCC (see POWERMON bit in CONFIG4 register)
Reset pin going low
It is a self-timed sequence which cannot be interrupted when started (see Figure 13).
Each step is separated by a delay based on Td equal to 8 periods of the DC/DC clock,
typically 2 µs:
1. T0: CARDRST is cleared, SHUTDOWN bit set.
2. T0 + 5 x Td:CARDCK is cleared, CKSTOP, CARDIO and IODIS are set.
3. T0 + 6 x Td: CARDIO is cleared.
4. T0 + 7 x Td: VCARD[1-0] = 00.
17
4234E–SCR–09/04
Figure 13. Deactivation Sequence
CVCC
CRST
CCLK
CIO,
CC4,
CC8
t1
t2
Td
Notes: 1. Setting ICARDERR by software does not trigger a deactivation. VCARDERR can be
used to deactivate the card by software.
2. t1=5 to 5.5*Td, and t2=0.5*Td to Td.
Transparent Mode
If the microcontroller outputs ISO 7816 signals, a transparent mode allows to connect
RST/CLK and I/O/C4/C8 signals after an electrical level control. The AT83C24 level
shifters adapt the card signals to the smart card voltage selection.
The CRST and CCLK microcontroller signals can be respectively connected to the
A1/RST and A2/CK pins.
The CRST_SEL bit (in CONFIG4 register) selects standard or transparent configuration
for the CRST pin. CKS in CONFIG2 allows to select standard or transparent configura-
tion for the CCLK pin. So CCLK and CRST are independent. A2/CK to A0/3V inputs
always give the TWI address at reset. The A0/3V pin can be used for TWI addressing
and easily connect two AT83C24 devices on the same TWI bus.
Figure 14. Transparent Mode Description
Microcontroller
AT83C24
CCLK
CRST
CIO
A2/CK
CCLK
A1/RST
I/O
CRST
CIO
SMART CARD
CC4
CC8
C4
CC4
CC8
C8
18
AT83C24
4234E–SCR–09/04
AT83C24
Power Modes
Two power-down modes are available to reduce the AT83C24 power consumption (see
STUTDOWN bit in CONFIG1 register and LP bits in CONFIG3 register).
To enter in the mode number 4 (see Table 5), the sequence is the following:
–
–
First select the Low-power mode by setting the LP bit
The activation of the SHUTDOWN bit can then be done.
The AT83C24 exits Power-down if a software/hardware reset is done or if SHUTDOWN
bit is cleared. The AT83C24 is then active immediately.
Either a hardware reset or a TWI command clearing the SHUTDOWN bit can cause an
exit from Power-down. The internal registers retain their value during the shutdown
mode.
In Power-down mode, the device is sleeping and waiting for a wake up condition.
To reduce power consumption, the User should stop the clock on the CLK input after
setting the SHUTDOWN bit. The clock can be enabled again just before exiting SHUT-
DOWN (at least 10 µs before a START bit on SDA).
Table 5. Power Modes Description
Typical
Supply
Current
Shutdown
Bit
LP
Bit
STEPREG
VCARD[1:0]
Description
Mode
Number
1
0
X
0
11
Step up mode: VCC = 3V, CVCC = 5V,
160 mA
30 mA
Icard = 65mA
Icard = 0
2
0
X
1
11
70 mA
Regulator mode: VCC = 5.25V, CVCC = 5V,
Icvcc = 65mA
3
4
0
1
X
0
X
X
00
00
3 mA
DC/DC off, CLK = 10MHz, VCC=3V to 5V
90 µA
The TWI interface of the AT83C24 is active
but its analog blocs are switched off to reduce
the consumption
5
1
1
X
00
30 µA
Pulsed mode of the internal 3V logic regulator
Power Monitoring
The AT83C24 needs only one power supply to run: VCC.
If the microcontroller outputs signals with a different electrical level, the host positive
supply is connected to EVCC.
EVCC and VCC pins can be connected together if they have the same voltage.
•
If EVCC and VCC have different electrical levels:
The EVCC pin and RESET pin should be connected with a resistor bridge. RESET
pin high level must be higher than VIH (see Table 19). When EVCC drops, RESET
pin level drops too. A deactivation sequence starts if a card was active.
19
4234E–SCR–09/04
Then the AT83C24 resets if RESET pin stays low.
•
If EVCC and VCC have the same value, then they should be connected:
The AT83C24 integrates an internal 3V regulator to feed its logic from the VCC sup-
ply. The bit powermon allows the user to select if the internal PFD monitors VCC or
the internal regulated 3V. If the PFD monitors VCC (POWERMON bit=0), a deacti-
vation is performed if VCC falls below VPFDP (see VPFDP value in the datasheet).
Same deactivation is performed if the internal 3V falls below VPFDP and POWER-
MON bit = 1.
20
AT83C24
4234E–SCR–09/04
AT83C24
Registers
Table 6. CONFIG0 (Config Byte 0)
7
1
6
0
5
4
3
2
1
0
ATRERR
INSERT
ICARDERR VCARDERR
VCARD1
VCARD0
Bit
Number
Bit Mnemonic Description
7-6
1-0
These bits cannot be programmed and are read as 1-0.
Answer to Reset Interrupt
This bit is set when the card clock counter overflows (no falling edge on CIO
is received before the overflow of the card clock counter).
5
ATRERR
This bit is cleared by hardware when this register is read. It can be set by
software for test purpose. The reset value is 0.
Card Insertion Interrupt
This bit is set when a card is inserted or extracted: a change in CARDIN value
filtered according to CDS[2-0]. After power up, if the level on CPRES pin is 0,
then INSERT bit is set.
4
INSERT
It can be set by software for test purpose.
This bit is cleared by hardware when this register is read. It cannot be cleared
by software.
The reset value is 0.
Card Over Current Interrupt
This bit is set when an over current is detected on CVCC. It can be set by
software for test purpose (no card deactivation is performed, no IT is
performed).
3
ICARDERR
This bit is cleared by hardware when this register is read. It cannot be cleared
by software.
The reset value is 0.
Card Out of Range Voltage Interrupt
This bit is set when the output voltage goes out of the voltage range specified
by VCARD field. It can be set by software for test purpose and deactivate the
card.
2
VCARDERR
This bit is cleared by hardware when this register is read. It cannot be cleared
by software.
The reset value is 0.
Card Voltage Selection
VCARD[1:0] = 00: 0V
VCARD[1:0] = 01: 1.8V (see STEPREG bit)
VCARD[1:0] = 10: 3V
VCARD[1:0] = 11: 5V
1-0
VCARD[1:0]
VCARD[1:0] writing to 1.8V, 3V, 5V starts the DC/DC if a card is detected.
VCARD[1:0] writing to 0 stops the DC/DC.
No card deactivation is performed when the voltage is changed between
1.8V, 3V or 5V. The microcontroller should deactivate the card before
changing the voltage.
The reset value is 00.
21
4234E–SCR–09/04
Table 7. CONFIG 1 (Config Byte 1)
7
X
6
5
4
3
2
1
0
ART
SHUTDOWN
CARDDET
PULLUP
CDS2
CDS1
CDS0
Bit
Bit
Number
Mnemonic Description
7
X
This bit should not be set.
Automatic Reset Transition
Set this bit to have the CRST pin changed according to activation sequence.
6
ART
Clear this bit to have the CRST pin immediately following the value programmed
in CARDRST.
The reset value is 0.
Shutdown
Set this bit to reduce the power consumption. An automatic de-activation
sequence will be done.
SHUTDOWN
5
4
Clear this bit to enable VCARD[1:0] selection.
The reset value is 0.
Card Presence Detection Polarity
Set this bit to indicate the card presence detector is closed when no card is
inserted (CPRES is low).
CARDDET
Clear this bit to indicate the card presence detector is open when no card is
inserted (CPRES is high).Changing CARDDET will set INSERT bit (see
CONFIG0) even if no card is inserted or extracted.
The reset value is 0.
Pull-up Enable
Set this bit to enable the internal pull-up on the CPRES pin. This allows to
minimize the number of external components.
3
PULLUP
Clear this bit to disable the internal pull-up and minimize the power consumption
when the card detection contact is on. Then an external pull-up must be
connected to VCC (typically a 1 MΩ resistor).
The reset value is 1.
Card Detection filtering
CPRES is sampled by the master clock provided on CLK input. A change on
CPRES is detected after:
CDS[2-0] = 0: 0 sample(1)
CDS[2-0] = 1: 4 identical samples
CDS [2-0] = 2: 8 identical samples (reset value)
CDS[2-0] = 3: 16 identical samples
CDS[2-0] = 4: 32 identical samples
CDS[2-0] = 5: 64 identical samples
CDS[2-0] = 6: 128 identical samples
CDS[2-0] = 7: 256 identical samples
The reset value is 2.
2-0
CDS[2:0]
Note:
When CDS[2-0] = 0 and IT_SEL = 0, PRES/INT = 1 when no
card is present and PRES/INT = 0 when a card is inserted
even if CLK is STOPPED. This can be used to wake up the
external microcontroller and restart CLK when a card is
inserted in the AT83C24.
If CDS[2-0] = 0, IT_SEL = 1 and CLK is stopped, a card insertion or
extraction has no effect on PRES/INT pin.
22
AT83C24
4234E–SCR–09/04
AT83C24
Table 8. CONFIG2 (Config Byte 2)
7
6
5
4
3
2
1
0
X
DCK2
DCK1
DCK0
X
CKS2
CKS1
CKS0
Bit
Bit
Number
Mnemonic Description
7
X
This bit should not be set.
DC/DC Clock prescaler factor
DCCLK is the DC/DC clock. It is the division of CLK input by DCK prescaler.
DCK = 0: prescaler factor equals 1 (CLK = 4 to 4.61MHz)
DCK [2:0] = 1: prescaler factor equals 2 (CLK = 7 to 9.25MHz)
DCK [2:0] = 2: prescaler factor equals 4 (CLK = 14 to 18.5 MHz)
DCK [2:0] = 3: prescaler factor equals 6 (CLK = 21 to 27.6 MHz)
DCK [2:0] = 4: prescaler factor equals 8 (CLK = 28 to 34.8 MHz)
6-4
DCK[2:0] DCK [2:0] = 5: prescaler factor equals 10 (CLK = 35 to 43 MHz)
DCK [2:0] = 6: prescaler factor equals 12 (CLK = 43.1 to 48 MHz)
DCK [2:0] = 7: reserved
The reset value is 1.
DCCLK must be as close as possible to 4 MHz with a duty cycle of 50%.
DCK must be programmed before starting the DC/DC.
The other values of CLK are not allowed.
DCK has to be properly configured before resetting the STEPREG bit.
3
X
This bit should not be set.
Card Clock prescaler factor
CKS [2:0] = 0: CCLK = CLK (then the maximum frequency on CLK is 24 MHz)
CKS [2:0] = 1: CCLK = DCCLK (DC/DC clock)
CKS [2:0] = 2: CCLK = DCCLK / 2
CKS [2:0] = 3: CCLK = DCCLK / 4
CKS [2:0] = 4: CCLK = A2
2-0
CKS[2:0]
CKS [2:0] = 5: CCLK = A2 / 2
CKS [2:0] = 6: CCLK = CLK / 2
CKS [2:0] = 7: CCLK = CLK / 4
The reset value is 0.
Notes: 1. When this register is changed, a special logic insures no glitch occurs on the CCLK
pin and actual configuration changes can be delayed by half a period to two periods
of CCLK.
2. CCLK must be stopped with CKSTOP bit before switching from CKS = (0, 1, 2, 3, 6,
7) to CKS = (4, 5) or vice versa.
3. When DCK = 0, only CKS=4 and CKS=5 are allowed.
4. The user can’t directly select A2 or A2/2 after a reset or when switching from CKS =
(0, 1, 2, 3, 6, 7) to CKS = (4, 5). To select A2, the user should select A2/2 first and
after A2. To select A2/2, the user should select A2 first and after A2/2.
23
4234E–SCR–09/04
Table 9. CONFIG3 (Config Byte 3)
7
6
5
4
3
2
1
0
EAUTO
VEXT1
VEXT0
ICCADJ
LP
X
X
X
Bit
Bit
Number
Mnemonic Description
EVCC voltage configuration:
EAUTO VEXT1 VEXT0
0
0
0
0
1
0
0
1
1
X
0 EVCC = 0 the regulator is switched off.
1EVCC = 2.3V
0 EVCC = 1.8V
EAUTO
VEXT1
VEXT0
1 EVCC = 2.7V
7-5
X EVCC voltage is the level detected on I/O input pin.
if EVCC is supplied from the external EVCC pin, the user can switch off the
internal EVCC regulator to decrease the consumption.
If EVCC is switched off, and no external EVCC is supplied, the AT83C24 is
inactive until a hardware reset is done.
The reset value is 100.
CICC overflow adjust
This bit controls the DC/DC sensitivity to any overflow current .
Set this bit to decrease the DC/DC sensitivity (CICC_ovf is increased by about
4
ICCADJ 20%, see Electrical Characteristics). The start of the DC/DC with a high current
load is easier.
Clear this bit to have a normal configuration.
The reset value is 0.
Low-power Mode
Set this bit to enable low-power mode during shutdown mode (pulsed mode
activated).
Clear this bit to disable low-power mode during shutdown mode.
3
LP
The activation reference is the following:
• First select the Low-power mode by setting LP bit.
• The activation of SHUTDOWN bit can then be done.
This bit as no effect when SHUTDOWN bit is cleared.
The reset value is 0.
2
1
0
X
X
X
This bit should not be set.
This bit should not be set.
This bit should not be set.
24
AT83C24
4234E–SCR–09/04
AT83C24
Table 10. CONFIG4 (Config Byte 4)
7
6
5
4
3
2
1
0
X
X
X
STEPREG
INT_PULLUP
POWERMON
IT_SEL
CRST_SEL
Bit Number
Bit Mnemonic Description
7-5
X-X-X
These bits should not be set.
Step Regulator mode
Clear this bit to enable the automatic step-up converter (CVCC is stable even if VCC is not higher than CVCC).
Set this bit to permanently disable the step-up converter (CVCC is stable only if VCC is sufficiently higher than
CVCC).
4
STEPREG
This bit must be set before activating the DC/DC converter if no external coil is present.
The reset value is 0.
This bit must always be set if no external coil is used
Internal pull-up
Set this bit to activate the internal pull-up (connected internally to EVCC) on PRES/INT pin.
3
2
INT_PULLUP Clear this bit to deactivate the internal pull-up.
PRES/INT is an open drain output with a programmable internal pull up.
The reset value is 0.
Power monitor
Set this bit to monitor any glitch on the Digital Supply Voltage (DVCC) of the AT83C24.
Clear this bit to monitor any glitch on VCC.
POWERMON
The reset value is 0.
Interrupt Select
Set this bit to disable INSERT and VCARD_INT interrupts. Then PRES/INT is pulled up when a card is present
and no error is detected.
1
0
IT_SEL
Clear this bit to have all the interrupt sources enabled and active Low.
IT_SEL must be set to enable a hardware activation with CMDVCC.
The reset value is 0.
Card Reset Selection
Set this bit to have the CRST pin driven by hardware through the A1 pin (only with hardware activation).
Clear this bit to have the CRST pin driven by software through the CARDRST bit.
CRST_SEL must be set when CMDVCC is used (hardware activation).
The reset value is 0.
CRST_SEL
25
4234E–SCR–09/04
Table 11. INTERFACE (Interface Byte)
7
0
6
5
4
3
2
1
0
IODIS
CKSTOP
CARDRST
CARDC8
CARDC4
CARDCK
CARDIO
Bit Number
Bit Mnemonic Description
7
0
This bit should not be set.
Card I/O isolation
Set this bit to drive the CIO, CC4, CC8 pins according to CARDIO, CARDC4, CARDC8 respectively and to put
I/O, C4, C8 in Hi-Z. This can be used to have the I/O, and C4 and C8 pins of the host communicating with
another AT83C24 interface, while CIO, CC4 and CC8 are driven by software (or if the card is in standby or
power-down modes).
6
IODIS
Clear this bit to drive the I/O/CIO, C4/CC4 and C8/CC8 pins according to each other. This can be used to activate
asynchronous cards.
The reset value is 1.
CARD Clock Stop
Set this bit to stop CCLK according to CARDCK. This can be used to set asynchronous cards in power-down
mode (GSM) or to drive CCLK by software.
Clear this bit to have CCLK running according to CKS. This can be used to activate asynchronous cards.
Note:
1. When this bit is changed a special logic ensures that no glitch occurs on the CCLK pin
and actual configuration changes can be delayed by half a period to two periods of
CCLK.
5
CKSTOP
2. CKSTOP must be set before switching on the DC/DC with VCARD[1:0].
The reset value is 1.
Card Reset
Set this bit to enter a reset sequence according to ART bit value.
Clear this bit to drive a low level on the CRST pin.
The reset value is 0.
4
3
CARDRST
CARDC8
Card C8
Set this bit to drive the CC8 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CC8 pin (according to IODIS bit value).
The reset value is 0.
Card C4
Set this bit to drive the CC4 pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
2
CARDC4
Clear this bit to drive a low level on the CC4 pin (according to IODIS bit value).
The reset value is 0.
Card Clock
Set this bit to set a high level on the CCLK pin (according to CKSTOP bit value).
Clear this bit to drive a low level on the CCLK pin.
The reset value is 0.
1
0
CARDCK
CARDIO
Card I/O
Set this bit to drive the CIO pin High with the on-chip pull-up (according to IODIS bit value). The pin can then be
an input (read in STATUS register).
Clear this bit to drive a low level on the CIO pin (according to IODIS bit value).
The reset value is 0.
26
AT83C24
4234E–SCR–09/04
AT83C24
Table 12. STATUS (Status Byte)
7
6
5
4
3
X
2
1
0
CC8
CC4
CARDIN
VCARDOK
VCARD_INT
CRST
CIO
Bit Number
Bit Mnemonic
Description
Card CC8
7
CC8
This bit provides the actual level on the CC8 pin when read.
The reset value is 0.
Card CC4
6
5
CC4
This bit provides the actual level on the CC4 pin when read.
The reset value is 0.
Card Presence Status
CARDIN
This bit is set when a card is detected.
It is cleared otherwise.
Card Voltage Status
This bit is set by the DCDC when the output voltage remains within the
voltage range specified by VCARD[1:0] bits.
It is cleared otherwise.
4
VCARD_OK
The reset value is 0.
3
2
X
This bit should not be set.
Card voltage interrupt
This bit is set when VCARD_OK bit is set.
This bit is cleared when read by the microcontroller.
The reset value is 0.
VCARD_INT
Card RST
1
0
CRST
CIO
This bit provides the actual level on the CRST pin when read.
The reset value is 0.
Card I/O
This bit provides the actual level on the CIO pin when read.
The reset value is 0.
Table 13. TIMER 1 (Timer MSB)
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit
Bit
Number
Mnemonic Description
7 - 0
Bits 15 - 8 Timer MSB (bits 15 to 8)
Reset value = 0x00000001
27
4234E–SCR–09/04
Table 14. TIMER 0 (Timer LSB)
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Number
Mnemonic Description
7 - 0
bits 7 - 0 Timer LSB (bits 7to 0)
Reset value = 0x10010000
Table 15. CAPTURE 1 (Capture MSB)
7
6
5
4
3
2
1
0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Bit
Bit
Number
Mnemonic Description
7 - 0
bits 15 - 8 See “software activation with ART = 1”, page 15.
Reset value = 0x00000000
Table 16. CAPTURE 0 (Capture LSB)
7
6
5
4
3
2
1
0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Bit
Bit
Number
Mnemonic Description
7 - 0
bits 7 - 0 See “software activation with ART = 1”, page 15.
Reset value = 0x00000000
28
AT83C24
4234E–SCR–09/04
AT83C24
Electrical Characteristics
Absolute Maximum Ratings *
*NOTICE:
Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Ambient Temperature Under Bias: .....................-40°C to 85°C
Storage Temperature: ................................... -65°C to +150°C
Voltage on VCC: ........................................ VSS -0.5V to +6.0V
Voltage on SCIB pins (***): .........CVSS -0.5V to CVCC + 0.5V
Voltage on host interface pins:.......VSS -0.5V to EVCC + 0.5V
Voltage on other pins:...................... VSS -0.5V to VCC + 0.5V
Power Dissipation value is based on the maxi-
mum allowable die temperature and the thermal
resistance of the package.
Power Dissipation: .......................................................... 1.5W
Thermal resistor of QFN pack-
age..(**)............................35°C/W
Thermal resistor of SO package.................................48°C/W
(**) Exposed die attached pad must be soldered to ground
Thermal resistor are measured on multilayer PCB with 0 m/s air flow.
(***) including shortages between any groups of smart card pins.
AC/DC Parameters
EVCC connected to host power supply: from 1.6V to 5.5V.
TA = -40°C to +85°C; VSS = 0V; VCC = 3V to 5.5V.
CLASS A card supplied with CVCC = 4.75 to 5.25V for AT83C24NDS
CLASS A card supplied with CVCC = 4.6 to 5.25V for AT83C24
CLASS B card supplied with CVCC = 2.8V to 3.2V
CLASS C card supplied with CVCC = 1.68V to 1.92V
Table 17. Core (VCC)
Symbol
Parameter
Min
2.4
Typ
2.5
Max
2.6
Unit
V
Test Conditions
VPFDP
VPFDM
trise, tfall
Power fail high level threshold
Power fail low level threshold
VDD rise and fall time
2.25
1 µs
2.35
2.45
600s
V
Not tested.
Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
0.3 x EVCC
EVCC from 2.7V to VCC
EVCC from 1.6 to 2.7V
VIL
Input Low-voltage
Input High Voltage
-0.5
V
V
0.25 x EVCC
EAUTO=0
VIH
0.7 x EVCC
EVCC + 0.5
EAUTO=1
EVCC from 1.6V to VCC
29
4234E–SCR–09/04
Table 18. Host Interface (I/O, C4, C8, CLK, A2, A1, A0, CMDVCC, PRES/INT) (Continued)
Symbol
Parameter
Min
0.8 x EVCC
300
Typ
Max
Unit
Test Conditions
IOL = -100 µA
0.05
0.4
V
V
VOL
Output Low-voltage (I/O, C4, C8, PRES/INT)
IOL = -1.2 mA
Output High Voltage (C4, C8, PRES/INT)
VOH on I/O depends on external pull up value
EVCC from 1.6V to VCC
VOH
EVCC
+3
V
IOH = 100 µA
EICC
Extra Supply Current
mA CL = 100 nF
Short to VSS
RPRES/INT PRES/INT weak pull-up output current
330
360
κΩ
INT_PULLUP = 0: Internal
pull-up active.
CL = 100 nF, EIcc = +3
mA
Vpeak on I/O from 1.6V to
VCC
EVCC
EVCC pin not connected to a power supply
Vpeak - 10 mV
Vpeak
Vpeak + 25 mV
V
EAUTO = 1:
min duration 1µs,
min frequency 0.1Hz,
spikes <50ns are filtered.
Vpeak -
200mV
EVCC
CLK
EVCC pin connected to a power supply
Clock signal for AT83C24
EAUTO = 1
If DCK[2:0] =0
(CLK=4MHz to 4.61MHz),
a duty cycle of 50% is
needed.
4
48
48
MHz
MHz
no constrainst on duty
cycle
CLK
Clock signal for AT83C24NDS
18
Table 19. Host Interface (SCL, SDA, RESET)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
1.9
VCC > 4.5V
VIL
Input Low-voltage
-0.5
V
0.3 x VCC
VCC <= 4.5V
3
VCC > 4.5V
VIH
Input High Voltage
Output Low-voltage
VCC + 0.5
0.4
V
V
0.7 x VCC
VCC <= 4.5V
VOL
IOL = -3 mA
VHIST
Input trigger hysteresis
0.1 x VCC
Table 20. Smart Card Class A
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VCC=3V to 5.5V,
STEPREG=0
Card Supply Current Capability
65
65
CICC
mA
mA
VCC > 5.35V, STEPREG = 1
Card Supply Current Overflow:
ICCADJ = 0 (reset value)
ICCADJ = 1
CICC_ovf
66
66
120
130
130
150
VCC from 3 to 5.5V
30
AT83C24
4234E–SCR–09/04
AT83C24
Table 20. Smart Card Class A
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
0 < Icard < 60mA CL =10µF
for AT83C24
60
200
350
Ripple on CVCC
Spikes on CVCC
mV
150
0 < Icard < 65mA CL = 3.3µF
for AT83C24NDS
Max. charge 40 nA.s
4.6
4.8
5.3
V
Max. duration 400 ns
Max. Icard variation 200 mA
Vcardok up
Vcardok high level threshold
Vcardok low level threshold
4.9
V
V
4.6
4.8
4.8
AT83C24
Vcardok down
4.75
AT83C24NDS
Icard = 0, VCC > VPFDP
CL = 3.3 µF Icard = 0
CL = 10 µF Icard = 0
(see note 1)
180
500
250
750
TVHL
CVCC valid to 0
µs
µs
VCC = 3V, CL = 3.3µF
Icard = 65mA
180
110
250
250
Icard = 0mA
TVLH
CVCC 0 to Valid
VCC = 3V, CL = 10µF
Icard = 65mA
240
170
300
250
Icard = 0mA
Notes: 1. Capacitor: X7R type or X5R type, max ESR value is 30mΩ (100kHz-100MHz),
Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction.
Table 21. Smart Card Class B
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
65
65
VCC=3V to 5.5V, STEPREG=0
VCC > 5.35V, STEPREG = 1
CICC
Card Supply Current Capability
mA
mA
mV
V
Card Supply Current Overflow:
CICC_ovf ICCADJ = 0 (reset value)
ICCADJ = 1
66
66
130
140
140
150
VCC from 3.0 to 5.5V
200
350
0 < Icard < 65mA CL =10µF
0 < Icard < 65mA CL = 3.3µF
Ripple on CVCC
60
Maxi. charge 40 nA.s
Max. duration 400 ns
Spikes on CVCC
2.76
3.24
Max. variation Icard 200mA
Vcardok up Vcardok high level threshold
2.8
3
V
V
Vcardok
Vcardok low level threshold
down
2.76
2.9
Icard = 0, VCC > VPFDP
CL = 3.3 µF Icard = 0
(see note 1)
130
400
250
500
TVHL
CVCC valid to 0
µs
CL = 10 µF Icard = 0
31
4234E–SCR–09/04
Table 21. Smart Card Class B
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VCC = 3V, CL = 3.3µF
Icard = 65mA
140
110
250
250
Icard = 0mA
TVLH
CVCC 0 to Valid
µs
VCC = 3V, CL = 10µF
Icard = 60mA
130
100
250
250
Icard = 0mA
Notes: 1. Capacitor: X7R type or X5R type, max ESR value is 30mΩ (100kHz-100MHz),
Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction.
Table 22. Smart Card Class C
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
CICC
Card Supply Current Capability
40
mA VCC = 3V
Card Supply Current Overflow:
CICC_ovf ICCADJ = 0 (reset value)
ICCADJ = 1
45
mA
Spikes on CVCC
1.68
1.75
1.92
300
V
V
Vcardok up Vcardok high level threshold
1.8
Vcardok
Vcardok low level threshold
down
1.7
1.75
V
Icard = 0, CL = 10 µF(1)
TVHL
CVCC valid to 0
180
µs
µs
CVCC = 1.8V to 0.4V
200
100
50
300
150
80
Icard = 40mA, CL = 10 µF(1)
Icard = 0, CL = 10 µF(1)
TVLH
CVCC 0 to valid
Icard = 40mA, CL = 3.3 µF(1)
Icard = 0, CL = 3.3 µF(1)
CVCC = 0.4 to VCARDOK
60
100
Notes: 1. Capacitor: X7R type or X5R type, max ESR value is 30mΩ (100kHz-100MHz),
Replacing 3.3µF by 2.2µF in parrallel with 1µF is better for ESR and noise reduction.
Table 23. Smart Card Clock (CCLK pin)
Symbol
Parameter
Min
0
Typ
Max
0.4
Unit
Test Conditions
IOL = -200 µA CLASS
A&B&C
VOL
Output Low-voltage
V
CVCC - 0.45
CVCC
IOH = +200 µA CLASS
A&B
VOH
Output High Voltage
Short Circuit Current
V
CLASS C
0.7CVCC
-30
CVCC
30
IOS
mA
Short to GND or CVCC
CL = 30 pF CLASS A
CL = 30 pF CLASS B
CL = 30 pF CLASS C
16
22.5
50
ns
tR tF
Rise and Fall time
measurement between
10% and 90% of CVCC
32
AT83C24
4234E–SCR–09/04
AT83C24
Table 23. Smart Card Clock (CCLK pin) (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
0.2
CLASS A
CCLK from 0.5 to 4.2V
CLASS B
Rise and Fall Slew rate
0.12
V/ns
CCLK from 0.5 to 0.85 x
CVCC
Low level voltage stability
-0.25
0.5
V
CLASS A&B&C
(taking into account PCB design)
High level voltage stability
4.2
2.35
CVCC+0.25
CVCC+0.25
CVCC+0.25
CVCC = CLASS A
CVCC = CLASS B
CLASS C
(taking into account PCB design)
V
CVCC-0.4
CCLK
Smart card clock frequency
24
MHz
CL = 30pF, CLK=48MHz
Table 24. Smart Card I/O (CIO, CC4, CC8 pins)
Symbol
VIL
Parameter
Min
Typ
Max
0.8
Unit
V
Test Conditions
IIL = 500 µA
Input Low-voltage
Input Low Current
-0.3V
IIL
700
µA
CVCC = CLASS A&B&C
0.6 x CVCC
0.7 x CVCC
CVCC
CVCC
CVCC = CLASS A
VIH
IIH
Input High Voltage
Input High Current
V
CVCC = CLASS B & C
-20
+20
µA
0.45
0.3
IOL = -1 mA CLASS A
IOL = -1 mA CLASS B
IOL = -1 mA CLASS C
VOL
Output Low-voltage
0
V
0.3
IOH = 40 µA CLASS
A&B&C
0.75 x CVCC
0.9 x CVCC
CVCC
CVCC
VOH
Output High Voltage
V
mA
V
IOH = 0µA, CLASS A&B
IOS
Output Short Circuit Current
-15
+15
Short to GND or CVCC
-0.25
-0.25
-0.25
0.6
0.4
0.4
CLASS A
CLASS B
CLASS C
Low level voltage stability
(taking into account PCB design)
High level voltage stability
CVCC-0.5
CVCC+0.25
V
CVCC = CLASS A&B&C
(taking into account PCB design)
CL = 65 pF
CLASS A:
measurement between
0.6V and 70% of CVCC
Output rise and fall time
Input rise and fall time
tR tF
0.1
1
µs
µs
CLASS B & C:
measurement between
0.4V and 70% of CVCC
tR tF
CL = 65 pF
33
4234E–SCR–09/04
Table 25. Smart Card RST (CRST pin)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
0.12 x CVCC
IOL = -20 µA CLASS
A&B&C
0
0
VOL
Output Low-voltage
0.4
0.2
V
IOL = -200 µA CLASS A
IOL = -200 µA CLASS
B&C
IOH = 200 µA
VOH
IOS
Output High Voltage
Output High Current
0.9*CVCC
-15
CVCC
+15
V
CLASS A&B&C
mA
Short to GND or CVCC
CL = 30pF
tR tF
Rise and Fall time
0.1
µs
V
measurement between
10% and 90% of CVCC
0.50V
0.30V
0.30V
CLASS A
CLASS B
CLASS C
Low level voltage stability
-0.25
(taking into account PCB design)
4.2
2.35
CLASS A
CLASS B
CLASS C
High level voltage stability
CVCC+0.25
V
(taking into account PCB design)
CVCC-0.4
Table 26. Card Presence
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Short to VSS
RCPRES
CPRES weak pull-up output current
300
330
360
κΩ
PULLUP = 1:
Internal pull-up active
Table 27. TWI (SDA, SCL pins)
Symbol
tSU;DAT
tHD;DAT
tfDA
Parameter
Min
20
Typ
10
0
Max
Unit
ns
Test Conditions
Not tested
Data set-up time
Data hold time
10
ns
Not tested
Fall time on SDA signal
50
ns
Not tested
34
AT83C24
4234E–SCR–09/04
Typical Application
Figure 1. Typical Standard Mode Application Diagram for 3 AT83C24 (up to 8 AT83C24 if needed)
VCC
EVCC
100nF
L1
4.7µH
C1
2.2µF
VSS
C13
VSS
VCC
VCC
VCC
A2/CK
See note
pull up
A1/RST
A0/3V
for
I/O
CRST
CIO, CC4, CC8
CPRES
SDA,
SCL
pullups
Reset
pullup
Card 1
CCLK
SCL
SDA
CVCC,
CVCCin
TWI
AT83C24
2.2uF 1uF
100nF
C2
RESET
RST
C3
C10
CVSS
CVSS
CVSS
DVCC
INT0
Px.y
PRES/INT
I/O, C4, C8
100nF
CLK
VSS
VCC
100nF
EVCC
L2
4.7µH
C4
2.2µF
VSS
C14
VSS
Host
MICROCONTROLLER
VCC
A2/CK
A1/RST
A0/3V
CRST
CIO, CC4, CC8
CPRES
XTAL1
XTAL2
Card 2
VSS
CCLK
SCL
SDA
CVCC,
CVCCin
AT83C24
2.2uF
1uF
100nF
4 to 48 MHz
RESET
C5
C6
C11
CVSS
CVSS
CVSS
VSS
DVCC
PRES/INT
I/O, C4, C8
VSS
100nF
CLK
VSS
VCC
100nF
EVCC
L3
4.7µH
C5
2.2µF
VSS
C15
VSS
VCC
A2/CK
A1/RST
A0/3V
CRST
CIO, CC4, CC8
CPRES
Card 3
VSS
CCLK
SCL
SDA
CVCC,
CVCCin
AT83C24
2.2uF
1uF
100nF
RESET
C8
C9
C12
CVSS CVSS
CVSS
PRES/INT
I/O, C4, C8
DVCC
100nF
CLK
VSS
Note: 1. The external resistor on I/O can be removed if the host pin has an internal resistor.
Typical NDS Application
Figure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS.
VCC
EVCC
100nF
L1
4.7µH
C1
2.2µF
VSS
C13
VSS
See note 2
VCC
VCC
See note1
for
I/O pull up
CVSS
SDA,
SCL
pullups
Reset
pullup
SCL
SDA
CRST
TWI
Smart
Card 1
CIO, CC4, CC8
CCLK
RESET
RST
INT0
Px.y
PRES/INT
I/O, C4, C8
CVCCin
CVCC
CLK
Px.y
Px.y
Px.y
A2/CLK
1uF
2.2uF
100nF
A1/RST
A0/3V
C2
C3
C10
CVSS
CVSS
CVSS
Host
MICROCONTROLLER
AT83C24NDS
XTAL1
XTAL2
CPRES
DVCC
18.432 or 27MHz
card
present
100nF
VSS
VSS
VSS
VSS
Note:
1. The external resistor on I/O can be removed if the host pin has an internal resistor.
2. The internal pull up on PRES/INT is disabled during reset (recommended external
20kOhms pull up).
3. Refer to application note for AT83C24NDS software configuration.
36
AT83C24
4234E–SCR–09/04
AT83C24
Ordering Information
Part Number
Supply Voltage
3V to 5.5V
Temperature Range
Industrial
Package
QFN28
QFN28
QFN28
QFN28
SO28
Packing
Tray
AT83C24-PRTIL(2)
AT83C24-PRRIL(2)
AT83C24-PRTIM(2)
AT83C24-PRRIM(2)
AT83C24-TISIL
3V to 5.5V
Industrial
Tape&Reel
Tray
4.00V to 5.5V
4.00V to 5.5V
3V to 5.5V
Industrial
Industrial
Tape&Reel
Stick
Industrial
AT83C24-TIRIL
3V to 5.5V
Industrial
SO28
Tape&Reel
Stick
AT83C24-TISIM
AT83C24-TIRIM
4.00V to 5.5V
4.00V to 5.5V
Industrial
SO28
Industrial
SO28
Tape&Reel
AT83C24NDS-PRTIL (1)(2)
AT83C24NDS-PRRIL (1)(2)
AT83C24NDS-PRTIM (1)(2)
AT83C24NDS-PRRIM (1)(2)
AT83C24NDS-TISIL (1)
AT83C24NDS-TIRIL (1)
AT83C24NDS-TISIM (1)
AT83C24NDS-TIRIM (1)
3V to 5.5V
3V to 5.5V
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
QFN28
QFN28
QFN28
QFN28
SO28
Tray
Tape&Reel
Tray
4.00V to 5.5V
4.00V to 5.5V
3V to 5.5V
Tape&Reel
Stick
3V to 5.5V
SO28
Tape&Reel
Stick
4.00V to 5.5V
4.00V to 5.5V
SO28
SO28
Tape&Reel
LEAD FREE/
HALOGEN FREE:
AT83C24-PRTUL(2)
AT83C24-PRRUL(2)
AT83C24-PRTUM(2)
AT83C24-PRRUM(2)
AT83C24-TISUL
3V to 5.5V
3V to 5.5V
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
QFN28
QFN28
QFN28
QFN28
SO28
Tray
Tape&Reel
Tray
4.00V to 5.5V
4.00V to 5.5V
3V to 5.5V
Tape&Reel
Stick
AT83C24-TIRUL
3V to 5.5V
SO28
Tape&Reel
Stick
AT83C24-TISUM
AT83C24-TIRUM
4.00V to 5.5V
4.00V to 5.5V
SO28
SO28
Tape&Reel
AT83C24NDS-PRTUL (1)(2)
AT83C24NDS-PRRUL (1)(2)
AT83C24NDS-PRTUM(1)(2)
3V to 5.5V
3V to 5.5V
Industrial
Industrial
Industrial
QFN28
QFN28
QFN28
Tray
Tape&Reel
Tray
4.00V to 5.5V
37
4234E–SCR–09/04
Part Number
Supply Voltage
4.00V to 5.5V
3V to 5.5V
Temperature Range
Industrial
Package
QFN28
SO28
Packing
Tape&Reel
Stick
AT83C24NDS-PRRUM (1)(2)
AT83C24NDS-TISUL (1)
AT83C24NDS-TIRUL (1)
AT83C24NDS-TISUM (1)
AT83C24NDS-TIRUM (1)
Industrial
3V to 5.5V
Industrial
SO28
Tape&Reel
Stick
4.00V to 5.5V
4.00V to 5.5V
Industrial
SO28
Industrial
SO28
Tape&Reel
Note:
1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS.
2. Refer to index mark for proper placement.
38
AT83C24
4234E–SCR–09/04
AT83C24
Package Drawings
QFN28
39
4234E–SCR–09/04
SO28
AT83C24
Datasheet Change
Log
Changes from 4234A-
05/03 to 4234B-02/04
1. Addition of CRST, CIO, CCLK controllers descriptions, page 10.
2. Update of Hardware\Software activation description, page 14.
3. Suppression of low voltage regulator mode for power down modes, page 19.
4. Modification of clock values in CONFIG2 regsiter, page 22.
5. Addition of a point on QFN pinout view, page2.
6. Update of electrical characteristics, page 29.
Changes from 4234B-
02/04 to 4234C - 04/04
1. Addition of references in ordering information
2. Update of EVCC description
3. Update of CARDDET bit and INSERT bit description
Changes from 4234C-
04/04 to 4234D - 07/04
1. Update for Rev 4 silicon version (index 4 on component).
2. Software workaround for A2 or A2/2 selection in CKS register.
3. Max speed on IO/CIO transfer
4. New conditions for hardware activation (see IT_SEL).
5. SO28 drawing package (error with SO32).
6. Adjusted electrical parameters for NDS compliance, pages 28, 29, 30.
Changes from 4234D-
04/04 to 4234E - 09/04
1. QFN28 new package drawing.
2. Clock input parameters for AT83C24 and AT83C24NDS.
41
4234E–SCR–09/04
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4234E–SCR–09/04
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