AT87F52-24PL [ATMEL]
Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40;
| 型号： | AT87F52-24PL |
| 厂家： | 
ATMEL |
| 描述： | Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40 微控制器 光电二极管 |
| 文件： | 总24页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS-51™ Products
• 8K Bytes of User Programmable QuickFlash™ Memory
• Fully Static Operation: 0 Hz to 24 MHz
• Three-Level Program Memory Lock
• 256 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-Bit Timer/Counters
• Eight Interrupt Sources
• Programmable Serial Channel
• Low Power Idle and Power Down Modes
8-Bit
Microcontroller
with 8K Bytes
QuickFlash™
Description
The AT87F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K
bytes of QuickFlash programmable read only memory. The device is manufactured
using Atmel’s high density nonvolatile memory technology and is compatible with the
industry standard 80C51 and 80C52 instruction set and pinout. The on-chip Quick-
Flash allows the program memory to be user programmed by a conventional nonvola-
tile memory programmer. By combining a versatile 8-bit CPU with QuickFlash on a
monolithic chip, the Atmel AT87F52 is a powerful microcomputer which provides a
highly flexible and cost effective solution to many embedded control applications.
AT87F52
(continued)
PDIP
Not Recommended
for New Designs.
Use AT89S52.
Pin Configurations
( T 2 ) P 1 . 0
( T 2 E X ) P 1 . 1
P 1 . 2
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
V C C
1
2
3
4
5
6
7
P 0 . 0 ( A D 0 )
P 0 . 1 ( A D 1 )
P 0 . 2 ( A D 2 )
P 0 . 3 ( A D 3 )
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
E A / V P P
P 1 . 3
P 1 . 4
P 1 . 5
P 1 . 6
P 1 . 7
R S T
8
9
TQFP
( R X D ) P 3 . 0
( T X D ) P 3 . 1
( I N T 0 ) P 3 . 2
( I N T 1 ) P 3 . 3
( T 0 ) P 3 . 4
( T 1 ) P 3 . 5
( W R ) P 3 . 6
( R D ) P 3 . 7
X TA L 2
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
P 2 . 4 ( A 1 2 )
P 2 . 3 ( A 1 1 )
P 2 . 2 ( A 1 0 )
P 2 . 1 ( A 9 )
P 2 . 0 ( A 8 )
I N D E X
C O R N E R
4 4 4 2 4 0 3 8 3 6 3 4
4 3 4 1 3 9 3 7 3 5
X TA L 1
G N D
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
1
2
3
4
5
6
7
8
9
3 3
3 2
3 1
3 0
2 9
P 1 . 5
P 1 . 6
P 1 . 7
R S T
( R X D ) P 3 . 0
N C
( T X D ) P 3 . 1
( I N T 0 ) P 3 . 2
( I N T 1 ) P 3 . 3
( T 0 ) P 3 . 4
( T 1 ) P 3 . 5
E A / V P P
N C
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
2 8
2 7
2 6
2 5
2 4
2 3
PLCC
1 0
1 1
I N D E X
C O R N E R
1 9
1 8 2 0 2 2
1 3 1 5 1 7
2 1
1 6
1 2 1 4
6
4
2
4 4 4 2 4 0
5
3
1
4 3 4 1
3 9
P 1 . 5
7
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
E A / V P P
P 1 . 6
P 1 . 7
8
9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
R S T
( R X D ) P 3 . 0
N C
( T X D ) P 3 . 1
( I N T 0 ) P 3 . 2
( I N T 1 ) P 3 . 3
( T 0 ) P 3 . 4
N C
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
( T 1 ) P 3 . 5
1 9 2 1 2 3 2 5 2 7
2 8
1 8 2 0 2 2 2 4 2 6
Rev. 1011A–02/98
Block Diagram
P0.0 - P0.7
P2.0 - P2.7
VCC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
RAM ADDR.
REGISTER
PORT 2
LATCH
QUICK
FLASH
PORT 0
LATCH
RAM
PROGRAM
ADDRESS
REGISTER
STACK
POINTER
B
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DPTR
PORT 1
LATCH
PORT 3
LATCH
OSC
PORT 1 DRIVERS
P1.0 - P1.7
PORT 3 DRIVERS
P3.0 - P3.7
Not
2
Not
The AT87F52 provides the following standard features: 8K
bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines, three
16-bit timer/counters, a six-vector two-level interrupt archi-
tecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT87F52 is designed with
static logic for operation down to zero frequency and sup-
ports two software selectable power saving modes. The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue
functioning. The Power Down Mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip func-
tions until the next hardware reset.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Pin Description
VCC
Supply voltage.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash programming and verifi-
cation.
GND
Ground.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal pul-
lups.
Port 3 also serves the functions of various special features
of the AT89C51, as shown in the following table.
Port 3 also receives some control signals for QuickFlash
programming and verification.
Port 0 also receives the code bytes during QuickFlash pro-
gramming and outputs the code bytes during program veri-
fication. External pullups are required during program verifi-
cation.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
Port 1
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
Port 1 also receives the low-order address bytes during
QuickFlash programming and verification.
ALE/PROG
Port Pin
Alternate Functions
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
ory. This pin is also the program pulse input (PROG) during
QuickFlash programming.
P1.0
T2 (external count input to Timer/Counter 2),
clock-out
P1.1
T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
3
pulse is skipped during each access to external data mem-
ory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
EA should be strapped to VCC for internal program execu-
tions.
PSEN
This pin also receives the 12-volt programming enable volt-
age (VPP) during QuickFlash programming.
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT87F52 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Table 1. AT87F52 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
B
0F0H
00000000
0E8H
ACC
0E0H
00000000
0D8H
PSW
0D0H
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
SBUF
XXXXXXXX
P1
11111111
90H
97H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
88H
8FH
P0
11111111
SP
00000111
DPL
00000000
DPH
00000000
PCON
0XXX0000
80H
87H
Not
4
Not
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Special Function Registers
A map of the on-chip memory area called the Special Func-
Timer 2 Registers: Control and status bits are contained
in registers T2CON (shown in Table 2) and T2MOD (shown
in Table 4) for Timer 2. The register pair (RCAP2H,
RCAP2L) are the Capture/Reload registers for Timer 2 in
16-bit capture mode or 16-bit auto-reload mode.
tion Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
Interrupt Registers: The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H
Reset Value = 0000 0000B
Bit Addressable
Bit
TF2
7
EXF2
6
RCLK
5
TCLK
4
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Symbol
Function
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 =
1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2
must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
TCLK
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial
port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial
port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX
if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1.
CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when
EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2
overflow.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
Data Memory
The AT87F52 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.
MOV @R0, #data
5
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transi-
tion, the maximum count rate is 1/24 of the oscillator fre-
quency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.
Timer 0 and 1
Timer 0 and Timer 1 in the AT87F52 operate the same way
as Timer 0 and Timer 1 in the AT87F51.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.
Capture Mode
In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a 1-
to-0 transition at external input T2EX also causes the cur-
rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, respectively. In addition, the transition at T2EX
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illus-
trated in Figure 1.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscil-
lator periods, the count rate is 1/12 of the oscillator fre-
quency.
Table 3. Timer 2 Operating Modes
RCLK +TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-Bit Auto-Reload
16-Bit Capture
Baud Rate Generator
(Off)
Auto-Reload (Up or Down Counter)
1
Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
X
X
1
0
is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value
of the T2EX pin.
Figure 1. Timer in Capture Mode
÷12
OSC
C/T2 = 0
C/T2 = 1
TH2
TL2
TF2
OVERFLOW
CONTROL
TR2
CAPTURE
T2 PIN
RCAP2H RCAP2L
EXF2
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
T2EX PIN
CONTROL
EXEN2
Not
6
Not
Figure 2 shows Timer 2 automatically counting up when
DCEN = 0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The over-
flow also causes the timer registers to be reloaded with the
16-bit value in RCAP2H and RCAP2L. The values in Timer
in Capture ModeRCAP2H and RCAP2L are preset by soft-
ware. If EXEN2 = 1, a 16-bit reload can be triggered either
by an overflow or by a 1-to-0 transition at external input
T2EX. This transition also sets the EXF2 bit. Both the TF2
and EXF2 bits can generate an interrupt if enabled.
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in
RCAP2H and RCAP2L to be reloaded into the timer regis-
ters, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.
Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 3. In this mode, the T2EX pin controls
Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)
÷12
OSC
C/T2 = 0
TH2
TL2
OVERFLOW
CONTROL
TR2
C/T2 = 1
RELOAD
TIMER 2
INTERRUPT
T2 PIN
RCAP2H RCAP2L
TF2
TRANSITION
DETECTOR
EXF2
T2EX PIN
CONTROL
EXEN2
Table 4. T2MOD—Timer 2 Mode Control Register
T2MOD Address = 0C9H
Not Bit Addressable
Reset Value = XXXX XX00B
—
7
—
6
—
5
—
4
—
3
—
2
T2OE
1
DCEN
0
Bit
Symbol
—
Function
Not implemented, reserved for future
Timer 2 Output Enable bit.
T2OE
DCEN
When set, this bit allows Timer 2 to be configured as an up/down counter.
7
Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)
(DOWN COUNTING RELOAD VALUE)
0FFH 0FFH
TOGGLE
EXF2
12
OVERFLOW
OSC
÷
C/T2 = 0
TH2
TL2
TF2
CONTROL
TR2
C/T2 = 1
TIMER 2
INTERRUPT
T2 PIN
RCAP2H RCAP2L
COUNT
DIRECTION
1=UP
(UP COUNTING RELOAD VALUE)
0=DOWN
T2EX PIN
Figure 4. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW
2
÷
"0"
"0"
"1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1
RCLK
2
OSC
÷
C/T2 = 0
"1"
"1"
TH2
TL2
Rx
CLOCK
CONTROL
TR2
÷16
C/T2 = 1
"0"
T2 PIN
TCLK
RCAP2H RCAP2L
Tx
CLOCK
TRANSITION
DETECTOR
16
÷
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
Not
8
Not
increments every state time (at 1/2 the oscillator fre-
quency). The baud rate formula is given below.
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the baud
rates for transmit and receive can be different if Timer 2 is
used for the receiver or transmitter and Timer 1 is used for
the other function. Setting RCLK and/or TCLK puts Timer 2
into its baud rate generator mode, as shown in Figure 4.
Modes 1 and 3
Baud Rate 32 × [65536 – (RCAP2H,RCAP2L)]
Oscillator Frequency
--------------------------------------- = ----------------------------------------------------------------------------------------------
where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 4. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not gener-
ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0
transition in T2EX will set EXF2 but will not cause a reload
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer
2 is in use as a baud rate generator, T2EX can be used as
an extra external interrupt.
The baud rate generator mode is similar to the auto-reload
mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2H
and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer
2’s overflow rate according to the following equation.
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates = -----------------------------------------------------------
16
Note that when Timer 2 is running (TR2 = 1) as a timer in
the baud rate generator mode, TH2 or TL2 should not be
read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or
write may not be accurate. The RCAP2 registers may be
read but should not be written to, because a write might
overlap a reload and cause write and/or reload errors. The
timer should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
The Timer can be configured for either timer or counter
operation. In most applications, it is configured for timer
operation (CP/T2 = 0). The timer operation is different for
Timer 2 when it is used as a baud rate generator. Normally,
as a timer, it increments every machine cycle (at 1/12 the
oscillator frequency). As a baud rate generator, however, it
Figure 5. Timer 2 in Clock-Out Mode
TL2
(8-BITS)
TH2
(8-BITS)
÷2
OSC
TR2
RCAP2L RCAP2H
C/T2 BIT
P1.0
(T2)
÷2
T2OE (T2MOD.1)
TRANSITION
DETECTOR
P1.1
(T2EX)
TIMER 2
INTERRUPT
EXF2
EXEN2
9
Table 5. Interrupt Enable (IE) Register
Programmable Clock Out
(MSB)
(LSB)
EX0
A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 5. This pin, besides being a regu-
lar I/O pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 4
MHz at a 16 MHz operating frequency.
EA
—
ET2
ES
ET1
EX1
ET0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
To configure the Timer/Counter 2 as a clock generator, bit
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer.
Symbol
Position
Function
EA
IE.7
Disables all interrupts. If EA = 0,
no interrupt is acknowledged. If
EA = 1, each interrupt source is
individually enabled or disabled
by setting or clearing its enable
bit.
The clock-out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
Oscillator Fequency
Clock-Out Frequency= ------------------------------------------------------------------------------------------
4 × [65536 – (RCAP2H,RCAP2L)]
—
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Reserved.
In the clock-out mode, Timer 2 roll-overs will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock generator simulta-
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.
ET2
ES
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
ET1
EX1
ET0
EX0
Interrupts
User software should never write 1s to unimplemented bits,
because they may be used in future AT89 products.
The AT87F52 has a total of six interrupt vectors: two exter-
nal interrupts (INT0 and INT1), three timer interrupts (Tim-
ers 0, 1, and 2), and the serial port interrupt. These inter-
rupts are all shown in Figure 6.
Figure 6. Interrupt Sources
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
0
INT0
IE0
1
Note that Table 5 shows that bit position IE.6 is unimple-
mented. In the AT89C51, bit position IE.5 is also unimple-
mented. User software should not write 1s to these bit posi-
tions, since they may be used in future AT89 products.
TF0
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
0
1
INT1
IE1
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
TF1
TI
RI
TF2
EXF2
Not
10
Not
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 7. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 8.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Figure 7. Oscillator Connections
C2
XTAL2
C1
XTAL1
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
GND
Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution
from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to exter-
nal memory.
Note:
C1, C2 = 30 pF ±10 pF for Crystals
= 40 pF ±10 pF for Ceramic Resonators
Figure 8. External Clock Drive Configuration
NC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
Power Down Mode
In the power down mode, the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
Status of External Pins During Idle and Power Down Modes
Mode
Program Memory
Internal
ALE
PSEN
PORT0
Data
PORT1
Data
PORT2
Data
PORT3
Data
Idle
1
1
0
0
1
1
0
0
Idle
External
Float
Data
Data
Address
Data
Data
Power Down
Power Down
Internal
Data
Data
External
Float
Data
Data
Data
11
Programming Algorithm: Before programming the
AT87F52, the address, data, and control signals should be
set up according to the QuickFlash programming mode
table and Figures 9 and 10. To program the AT87F52, take
the following steps:
Program Memory Lock Bits
The AT87F52 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table.
1. Input the desired memory location on the address
lines.
Lock Bit Protection Modes
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
Program Lock Bits
LB1
U
LB2
U
LB3
U
Protection Type
1
2
No program lock features.
5. Pulse ALE/PROG once to program a byte in the Quick-
Flash array or the lock bits. The byte-write cycle is self-
timed and typically takes no more than 1.5 ms. Repeat
steps 1 through 5, changing the address and data for
the entire array or until the end of the object file is
reached.
P
U
U
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
internal memory, EA is
sampled and latched on reset,
and further programming of
the QuickFlash memory is
disabled.
Data Polling: The AT87F52 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on PO.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
3
4
P
P
P
P
U
P
Same as mode 2, but verify is
also disabled.
Same as mode 3, but external
execution is also disabled.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.4 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Programming the QuickFlash
The AT87F52 is shipped with the on-chip QuickFlash mem-
ory array ready to be programmed. The programming inter-
face needs a high-voltage (12-volt) program enable signal
and is compatible with conventional third-party Flash or
EPROM programmers.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H, 031H, and 032H, except that P3.6 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
The AT87F52 code memory array is programmed byte-by-
byte.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 87H indicates 87F family
(032H) = 02H indicates 87F52
Not
12
Not
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
Programming Interface
Every code byte in the QuickFlash array can be pro-
grammed by using the appropriate combination of control
signals. The write operation cycle is self-timed and once
initiated, will automatically time itself to completion.
QuickFlash Programming Modes
Mode
RST
PSEN
ALE/PROG
EA/VPP
P2.6
P2.7
P3.6
P3.7
Write Code Data
H
L
12V
L
H
H
H
Read Code Data
Write Lock
H
H
L
L
H
H
L
L
H
H
H
H
Bit - 1
Bit - 2
Bit - 3
12V
H
H
H
H
H
L
L
L
12V
12V
H
H
H
L
H
L
L
L
H
L
L
L
L
Read Signature Byte
H
13
Figure 9. Programming the QuickFlash Memory
Figure 10. Verifying the QuickFlash Memory
+5V
+5V
AT87F52
AT87F52
A0 - A7
OOOOH/1FFFH
A8 - A12
A0 - A7
VCC
P0
VCC
ADDR.
P1
ADDR.
P1
PGM DATA
(USE 10K
PULLUPS)
OOOOH/1FFFH
PGM
DATA
P2.0 - P2.4
P2.6
P0
P2.0 - P2.4
P2.6
A8 - A12
SEE FLASH
PROGRAMMING
MODES TABLE
P2.7
ALE
EA
PROG
P2.7
ALE
SEE FLASH
PROGRAMMING
MODES TABLE
P3.6
P3.6
VIH
P3.7
P3.7
XTAL2
VIH/VPP
XTAL2
EA
3-24 MHz
3-24 MHz
XTAL1
GND
RST
VIH
VIH
XTAL1
GND
RST
PSEN
PSEN
QuickFlash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ±10%
Symbol
VPP
Parameter
Min
Max
Units
V
Programming Enable Voltage
Programming Enable Current
Oscillator Frequency
11.5
12.5
1.0
24
IPP
mA
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
3
MHz
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold After PROG
PROG Width
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
µs
µs
µs
10
1
110
48tCLCL
48tCLCL
48tCLCL
1.0
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
0
µs
2.0
ms
Not
14
Not
QuickFlash Programming and Verification Waveforms
PROGRAMMING
VERIFICATION
ADDRESS
P1.0 - P1.7
P2.0 - P2.4
ADDRESS
tAVQV
PORT 0
DATA IN
DATA OUT
tDVGL tGHDX
tAVGL
tGHAX
ALE/PROG
tSHGL
tGHSL
tGLGH
VPP
LOGIC 1
LOGIC 0
EA/VPP
(2)
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY)
BUSY
tWC
READY
15
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ±20%, unless otherwise noted.
Symbol
Parameter
Condition
Min
-0.5
-0.5
Max
0.2 V -0.1
Units
V
V
V
V
V
V
Input Low Voltage
Input Low Voltage (EA)
Input High Voltage
Input High Voltage
(Except EA)
V
V
V
V
V
V
IL
CC
0.2 V -0.3
IL1
IH
CC
(Except XTAL1, RST)
(XTAL1, RST)
0.2 V +0.9
V
V
+0.5
+0.5
CC
CC
CC
0.7 V
IH1
OL
OL1
CC
(1)
Output Low Voltage (Ports 1,2,3)
I
= 1.6 mA
= 3.2 mA
0.45
0.45
OL
OL
(1)
Output Low Voltage
I
(Port 0, ALE, PSEN)
V
Output High Voltage
(Ports 1,2,3, ALE, PSEN)
I
I
I
I
I
I
= -60 µA, V = 5V ±10%
2.4
V
V
OH
OH
OH
OH
OH
OH
OH
CC
= -25 µA
= -10 µA
0.75 V
CC
CC
0.9 V
V
V
Output High Voltage
(Port 0 in External Bus Mode)
= -800 µA, V = 5V ±10%
2.4
V
OH1
CC
= -300 µA
= -80 µA
= 0.45V
0.75 V
V
CC
CC
0.9 V
V
I
I
Logical 0 Input Current (Ports 1,2,3)
V
V
-50
µA
µA
IL
IN
Logical 1 to 0 Transition Current
(Ports 1,2,3)
= 2V, V = 5V ±10%
-650
TL
IN
CC
I
Input Leakage Current (Port 0, EA)
Reset Pulldown Resistor
Pin Capacitance
0.45 < V < V
±10
300
10
µA
KΩ
pF
LI
IN
CC
RRST
50
C
Test Freq. = 1 MHz, T = 25°C
IO
A
I
Power Supply Current
Active Mode, 12 MHz
Idle Mode, 12 MHz
25
mA
CC
6.5
mA
(1)
100
40
µA
µA
Power Down Mode
V
V
= 6V
= 3V
CC
CC
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total I for all output pins: 71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater
OL
OL
than the listed test conditions.
2. Minimum VCC for Power Down is 2V.
Not
16
Not
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
Symbol
Parameter
12 MHz Oscillator
Variable Oscillator
Units
Min
Max
Min
0
Max
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
Oscillator Frequency
24
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE Pulse Width
127
43
2tCLCL-40
tCLCL-13
tCLCL-20
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
48
233
4tCLCL-65
tLLPL
43
tCLCL-13
tPLPH
tPLIV
205
3tCLCL-20
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
145
59
3tCLCL-45
tCLCL-10
tPXIX
0
0
tPXIZ
tPXAV
tAVIV
75
tCLCL-8
312
10
5tCLCL-55
10
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
400
400
6tCLCL-100
6tCLCL-100
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
252
5tCLCL-90
0
0
Data Float After RD
97
2tCLCL-28
8tCLCL-150
9tCLCL-165
3tCLCL+50
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold After WR
517
585
300
200
203
23
3tCLCL-50
4tCLCL-75
tCLCL-20
433
33
7tCLCL-120
tCLCL-20
RD Low to Address Float
RD or WR High to ALE High
0
0
43
123
tCLCL-20
tCLCL+25
17
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tPLIV
tLLPL
PSEN
tPXAV
tPLAZ
tPXIZ
tPXIX
tLLAX
A0 - A7
INSTR IN
A0 - A7
PORT 0
PORT 2
tAVIV
A8 - A15
A8 - A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
tLLDV
tRLRH
tLLWL
RD
tLLAX
tRHDZ
tRHDX
tRLDV
tAVLL
tRLAZ
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
PORT 0
tAVWL
tAVDV
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
PORT 2
Not
18
Not
External Data Memory Write Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
tQVWX
tWHQX
tAVLL
tQVWH
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
tCHCX
tCLCH
tCHCL
VCC - 0.5V
0.7 VCC
0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL
External Clock Drive
Symbol
1/tCLCL
tCLCL
Parameter
Oscillator Frequency
Clock Period
High Time
Min
0
Max
Units
MHz
ns
24
41.6
15
tCHCX
tCLCX
ns
Low Time
15
ns
tCLCH
Rise Time
20
20
ns
tCHCL
Fall Time
ns
19
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 5.0V ±20% and Load Capacitance = 80 pF.
Symbol
Parameter
12 MHz Osc
Variable Oscillator
Units
Min
Max
Min
12tCLCL
10tCLCL-133
2tCLCL-117
0
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
1.0
700
50
0
µs
ns
ns
ns
ns
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
700
10tCLCL-133
Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF
0
1
2
3
4
5
6
7
tXHDX
SET TI
tXHDV
OUTPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
(1)
(1)
AC Testing Input/Output Waveforms
Float Waveforms
VCC - 0.5V
+ 0.1V
- 0.1V
VOL
VLOAD
0.2 VCC + 0.9V
Timing Reference
Points
VLOAD
TEST POINTS
- 0.1V
0.2 VCC - 0.1V
0.45V
VLOAD
+ 0.1V
VOL
Note:
1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded V /V level occurs.
OH OL
Not
20
Not
Ordering Information
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
12
16
20
24
5V ±20%
5V ±20%
5V ±20%
5V ±20%
AT87F52-12AC
AT87F52-12JC
AT87F52-12PC
44A
44J
Commercial
(0°C to 70°C)
40P6
AT87F52-12AI
AT87F52-12JI
AT87F52-12PI
44A
44J
Industrial
(-40°C to 85°C)
40P6
AT87F52-16AC
AT87F52-16JC
AT87F52-16PC
44A
44J
Commercial
(0°C to 70°C)
40P6
AT87F52-16AI
AT87F52-16JI
AT87F52-16PI
44A
44J
Industrial
(-40°C to 85°C)
40P6
AT87F52-20AC
AT87F52-20JC
AT87F52-20PC
44A
44J
Commercial
(0°C to 70°C)
40P6
AT87F52-20AI
AT87F52-20JI
AT87F52-20QI
44A
44J
44Q
Industrial
(-40°C to 85°C)
AT87F52-24AC
AT87F52-24JC
AT87F52-24PC
44A
44J
Commercial
(0°C to 70°C)
40P6
AT87F52-24AI
AT87F52-24JI
AT87F52-24PI
44A
44J
Industrial
(-40°C to 85°C)
40P6
Package Type
44A
44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
44J
40P6
40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
21
Packaging Information
44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing
Quad Flat Package (TQFP)
44J, 44-Lead, Plastic J-Leaded Chip Carrier
(PLCC)
Dimensions in Millimeters and (Inches)*
Dimensions in Inches and (Millimeters)
12.21(0.478)
11.75(0.458)
.045(1.14) X 30° - 45°
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
SQ
.012(.305)
.008(.203)
PIN 1 ID
.630(16.0)
.590(15.0)
.656(16.7)
.650(16.5)
SQ
0.45(0.018)
0.30(0.012)
0.80(0.031) BSC
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
10.10(0.394)
9.90(0.386)
.165(4.19)
SQ
1.20(0.047) MAX
0
7
0.20(.008)
0.09(.003)
.022(.559) X 45° MAX (3X)
0.75(0.030) 0.15(0.006)
0.45(0.018) 0.05(0.002)
*Controlling dimension: millimeters
40P6, 40-Lead, 0.600" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.161(4.09)
.125(3.18)
.022(.559)
.014(.356)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0
15
REF
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
Not
22
Not
23
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Japan
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Fax-on-Demand
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International:
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e-mail
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http://www.atmel.com
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© Copyright Atmel Corporation 1998.
Atmel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Atmel Corporation product.
No other circuit patent licenses are implied. Atmel Corporation’s products are not authorized for use as critical components in life support
devices or systems.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1011A–02/98/15M
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