AT87LV51-16PI [ATMEL]
8-bit Microcontroller with 4K Bytes QuickFlash?; 8位微控制器与4K字节QuickFlash ？
| 型号： | AT87LV51-16PI |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 4K Bytes QuickFlash? |
| 文件： | 总16页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS-51™ Products
• 4K Bytes of User Programmable QuickFlash Memory
• 2.7V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 16 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
8-bit
• Six Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes
Microcontroller
with 4K Bytes
QuickFlash®
Description
The AT87LV51 is a low-voltage, high-performance CMOS 8-bit microcontroller with
4K bytes of QuickFlash One-Time Programmable (OTP) Read Only memory. The
device is manufactured using Atmel’s high-density nonvolatile memory technology
and is compatible with the industry standard MCS-51 instruction set and pinout. The
on-chip QuickFlash allows the program memory to be user programmed by a conven-
tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with
QuickFlash on a monolithic chip, the Atmel AT87LV51 is a powerful microcontroller
that provides a highly flexible and cost-effective solution to many embedded control
AT87LV51
Preliminary
applications.
(continued)
TQFP
Pin Configurations
P1.5
P1.6
1
2
3
4
5
6
7
8
9
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 EAVPP
P1.7
PDIP
RST
(RXD) P3.0
NC
28 NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
27 ALE/PROG
26 PSEN
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
1
2
3
4
5
6
7
8
9
40 VCC
25 P2.7 (A15)
24 P2.6 (A14)
23 P2.5 (A13)
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
(T0) P3.4 10
(T1) P3.5 11
(RXD) P3.0 10
(TXD) P3.1 11
(INT0) P3.2 12
(INT1) P3.3 13
(T0) P3.4 14
(T1) P3.5 15
(WR) P3.6 16
(RD) P3.7 17
XTAL2 18
PLCC
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
P1.5
P1.6
P1.7
7
8
9
39 P0.4 (AD4)
38 P0.5 (AD5)
37 P0.6 (AD6)
36 P0.7 (AD7)
35 EA/VPP
XTAL1 19
RST 10
(RXD) P3.0 11
NC 12
GND 20
34 NC
(TXD) P3.1 13
(INT0) P3.2 14
(INT1) P3.3 15
(T0) P3.4 16
(T1) P3.5 17
33 ALE/PROG
32 PSEN
31 P2.7 (A15)
30 P2.6 (A14)
29 P2.5 (A13)
Rev. 1602A–04/00
Block Diagram
AT87LV51
2
AT87LV51
The AT87LV51 provides the following standard features:
4K bytes of QuickFlash OTP program memory, 128 bytes
of RAM, 32 I/O lines, two 16-bit timer/counters, a five-vec-
tor, 2-level interrupt architecture, a full duplex serial port,
on-chip oscillator, and clock circuitry. In addition, the
AT87LV51 is designed with static logic for operation down
to zero frequency and supports two software-selectable
power-saving modes. The Idle mode stops the CPU while
allowing the RAM, timer/counters, serial port and interrupt
system to continue functioning. The Power-down mode
saves the RAM contents but freezes the oscillator disabling
all other chip functions until the next hardware reset.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, it uses strong internal pull-ups
when emitting 1s. During accesses to external data mem-
ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash programming and
verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pull-ups.
Pin Description
VCC
Supply voltage.
Port 3 also serves the functions of various special features
of the AT87LV51 as listed below:
GND
Ground.
Port 0
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to Port 0 pins, the pins can be used as high-
impedance inputs.
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
Port 0 may also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal
pull-ups.
Port 0 also receives the code bytes during QuickFlash pro-
gramming and outputs the code bytes during program
verification. External pull-ups are required during program
verification.
Port 3 also receives some control signals for QuickFlash
programming and verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pull-ups.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Port 1 also receives the low-order address bytes during
QuickFlash programming and verification.
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Quick-
Flash programming.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pull-ups.
In normal operation ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data
memory.
3
PSEN
EA should be strapped to VCC for internal program
executions.
Program Store Enable is the read strobe to external pro-
gram memory.
This pin also receives the 12-volt programming enable volt-
age (VPP) during QuickFlash programming.
When the AT87LV51 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
EA/VPP
XTAL2
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H, up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
Output from the inverting oscillator amplifier.
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
Table 1. AT87LV51 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
B
00000000
ACC
00000000
PSW
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
SBUF
00000000
XXXXXXXX
90H
P1
97H
11111111
88H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
8FH
87H
80H
P0
SP
DPL
DPH
PCON
11111111
00000111
00000000
00000000
0XXX0000
AT87LV51
4
AT87LV51
Note that not all of the addresses are occupied, and
unoccupied addresses may not be implemented on the
chip. Read accesses to these addresses will, in general,
return random data and write accesses will have an inde-
terminate effect.
Figure 2. External Clock Drive Configuration
NC
XTAL2
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
Timer 0 and 1
Timer 0 and Timer 1 in the AT87LV51 operate the same
way as Timer 0 and Timer 1 in the AT89C51.
Idle Mode
Oscillator Characteristics
In Idle Mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the Spe-
cial Function registers remains unchanged during this
mode. The Idle mode can be terminated by any enabled
interrupt or by a hardware reset.
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier, which can be configured for use as
an on-chip oscillator as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
It should be noted that when Idle is terminated by a hard-
ware reset, the device normally resumes program
execution from where it left off, up to two machine cycles
before the internal reset algorithm takes control. On-chip
hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when Idle is
terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port pin or to
external memory.
Figure 1. Oscillator Connections
C2
XTAL2
C1
Power-down Mode
XTAL1
In Power-down Mode, the oscillator is stopped and the
instruction that invokes power-down is the last instruction
executed. The on-chip RAM and Special Function registers
retain their values until the Power-down mode is termi-
nated. The only exit from Power-down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
GND
Note:
C1, C2 = 30 pF 10 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators
5
Status of External Pins during Idle and Power-down Modes
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
Data
PORT3
Data
Idle
Internal
1
1
0
0
1
1
0
0
Data
Data
Idle
External
Float
Data
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
External
Float
Data
Data
Data
Programming Algorithm: Before programming the
AT87LV51, the address, data and control signals should be
set up according to the QuickFlash Programming Modes
table and Figure 3 and Figure 4. To program the
AT87LV51, the following sequence should be followed:
Program Memory Lock Bits
The AT87LV51 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the
additional features listed in the table below:
1. Input the desired memory location on the address
lines.
Lock Bit Protection Modes
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
Program Lock Bits
LB1
U
LB2
U
LB3
U
Protection Type
1
2
No program lock features.
5. Pulse ALE/PROG once to program a byte in the
QuickFlash array or the lock bits. The byte-write
cycle is self-timed and typically takes no more than
1.5 ms. Repeat steps 1 through 5, changing the
address and data for the entire array or until the end
of the object file is reached.
P
U
U
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
internal memory, EA is
sampled and latched on
reset, and further
Data Polling: The AT87LV51 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P0.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
programming of the
QuickFlash is disabled.
3
4
P
P
P
P
U
P
Same as mode 2, also verify
is disabled.
Same as mode 3, also
external execution is
disabled.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.4 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is nec-
essary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to
function properly.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H and 031H, except that P3.6 and P3.7 need
to be pulled to a logic low. The values returned are:
Programming the QuickFlash
The AT87LV51 is shipped with the on-chip QuickFlash
memory array ready to be programmed. The programming
interface needs a high-voltage (12-volt) program enable
signal and is compatible with conventional third-party
QuickFlash or EPROM programmers.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 87H indicates 87F family
(032H) = 03H indicates 87LV51
The AT87LV52 code memory array is programmed byte-
by-byte.
AT87LV51
6
AT87LV51
Programming Interface
Every code byte in the QuickFlash array can be pro-
grammed by using the appropriate combination of control
signals. The write operation cycle is self-timed and once
initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
QuickFlash Programming Modes
Mode
RST
PSEN
ALE/PROG
EA/VPP
P2.6
P2.7
P3.6
P3.7
Write Code Data
H
L
12V
L
H
H
H
Read Code Data
Write Lock
H
H
L
L
H
H
L
L
H
H
H
H
Bit - 1
Bit - 2
Bit - 3
12V
H
H
H
H
H
L
L
L
12V
12V
H
H
H
L
H
L
L
L
H
L
L
L
L
Read Signature Byte
H
Figure 3. Programming the QuickFlash Memory
Figure 4. Verifying the QuickFlash Memory
+5V
+5V
AT87LV51
A0 - A7
AT87LV51
A0 - A7
0000H/0FFFH
A8 - A11
P1
VCC
P0
P1
VCC
P0
ADDR.
ADDR.
PGM DATA
(USE 10K
PULL-UPS)
0000H/0FFFH
PGM
DATA
P2.0 - P2.3
P2.6
P2.0 - P2.3
P2.6
A8 - A11
SEE QUICKFLASH
PROGRAMMING
MODES TABLE
SEE QUICKFLASH
PROGRAMMING
MODES TABLE
P2.7
ALE
EA
P2.7
PROG
ALE
P3.6
P3.6
V
IH
P3.7
P3.7
XTAL2
XTAL2
VIH /VPP
EA
3 -16 MHz
3 -16 MHz
P3.4
RDY/BSY
V
XTAL1
GND
RST
V
XTAL1
GND
RST
IH
IH
PSEN
PSEN
7
QuickFlash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0V 10%
Symbol
VPP
Parameter
Min
Max
12.5
1.0
Units
V
Programming Enable Voltage
Programming Enable Current
Oscillator Frequency
11.5
IPP
mA
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
3
16
MHz
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold After PROG
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
µs
µs
µs
10
PROG Width
1
110
48tCLCL
48tCLCL
48tCLCL
1.0
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
0
µs
2.0
ms
QuickFlash Programming and Verification Waveforms
PROGRAMMING
ADDRESS
VERIFICATION
ADDRESS
P1.0 - P1.7
P2.0 - P2.3
tAVQV
PORT 0
DATA IN
DATA IN
tDVGL tGHDX
tAVGL
tSHGL
tGHAX
tGHSL
ALE/PROG
tGLGH
VPP
LOGIC 1
LOGIC 0
EA/VPP
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY)
BUSY
tWC
READY
AT87LV51
8
AT87LV51
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.0V
DC Output Current...................................................... 15.0 mA
DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 2.7V to 5.5V, unless otherwise noted.
Symbol
Parameter
Condition
Min
Max
0.2 VCC - 0.1
0.2 VCC - 0.3
VCC + 0.5
VCC + 0.5
0.45
Units
VIL
Input Low Voltage
(Except EA)
-0.5
V
V
V
V
V
V
VIL1
Input Low Voltage (EA)
Input High Voltage
-0.5
VIH
(Except XTAL1, RST)
(XTAL1, RST)
IOL = 1.6 mA
0.2 VCC + 0.9
0.7 VCC
VIH1
VOL
Input High Voltage
Output Low Voltage(1) (Ports 1,2,3)
VOL1
Output Low Voltage(1)
(Port 0, ALE, PSEN)
IOL = 3.2 mA
0.45
VOH
Output High Voltage
(Ports 1,2,3, ALE, PSEN)
I
OH = -60 µA, VCC = 5V 10%
IOH = -20 µA
OH = -10 µA
2.4
V
V
0.75 VCC
0.9 VCC
2.4
I
V
VOH1
Output High Voltage
(Port 0 in External Bus Mode)
IOH = -800 µA, VCC = 5V 10%
IOH = -300 µA
V
0.75 VCC
0.9 VCC
V
IOH = -80 µA
V
IIL
ITL
ILI
Logical 0 Input Current
(Ports 1,2,3)
VIN = 0.45V
-50
-650
10
µA
Logical 1 to 0 Transition Current (Ports
1,2,3)
VIN = 2V, VCC= 5V 10%
0.45 < VIN < VCC
µA
µA
Input Leakage Current
(Port 0, EA)
RRST
CIO
Reset Pulldown Resistor
Pin Capacitance
50
300
10
KΩ
pF
Test Freq. = 1 MHz, TA = 25°C
Active Mode, 12 MHz, VCC = 6V/3V
Idle Mode, 12 MHz, VCC = 6V/3V
VCC = 6V
ICC
Power Supply Current
20/5.5
5/1
mA
mA
µA
µA
Power-down Mode(2)
100
20
VCC = 3V
Notes: 1. Under steady state (non-transient) conditions, IOL
must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Maximum total IOL for all output pins: 71mA
If IOL exceeds the test condition, VOL may exceed the
related specification. Pins are not guaranteed to sink
current greater than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
9
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
16 MHz Oscillator
Variable Oscillator
Symbol
1/tCLCL
tLHLL
Parameter
Min Max
Min
0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator Frequency
16
ALE Pulse Width
85
22
32
2tCLCL - 40
tCLCL - 40
tCLCL - 30
tAVLL
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
tLLAX
tLLIV
150
4tCLCL - 100
tLLPL
32
tCLCL - 30
tPLPH
tPLIV
142
3tCLCL - 45
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
82
37
3tCLCL - 105
tCLCL - 25
tPXIX
0
0
tPXIZ
tPXAV
tAVIV
75
tCLCL - 8
207
10
5tCLCL - 105
10
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
275
275
6tCLCL - 100
6tCLCL - 100
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
147
5tCLCL - 165
0
0
Data Float After RD
65
2tCLCL - 60
8tCLCL - 150
9tCLCL - 165
3tCLCL + 50
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold After WR
350
397
239
137
122
13
3tCLCL - 50
4tCLCL - 130
tCLCL - 50
287
13
7tCLCL - 150
tCLCL - 50
RD Low to Address Float
RD or WR High to ALE High
0
0
23
103
tCLCL - 40
tCLCL + 40
AT87LV51
10
AT87LV51
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tPLIV
tLLPL
PSEN
tPXAV
tPLAZ
tPXIZ
tPXIX
INSTR IN
tLLAX
PORT 0
PORT 2
A0 - A7
tAVIV
A0 - A7
A8 - A15
A8 - A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
RD
tLLDV
tLLWL
tRLRH
tLLAX
tRLAZ
tRHDZ
tRHDX
tRLDV
tAVLL
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
tAVDV
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
11
External Data Memory Write Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
tQVWX
tWHQX
tAVLL
tQVWH
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
tCHCX
tCLCH
tCHCL
VCC - 0.5V
0.7 VCC
0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL
External Clock Drive
Symbol
1/tCLCL
tCLCL
Parameter
Oscillator Frequency
Clock Period
High Time
Min
Max
Units
MHz
ns
0
62.5
20
16
tCHCX
tCLCX
ns
Low Time
20
ns
tCLCH
Rise Time
20
20
ns
tCHCL
Fall Time
ns
AT87LV51
12
AT87LV51
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 2.7V to 5.5V and Load Capacitance = 80 pF
12 MHz Oscillator
Variable Oscillator
Symbol
tXLXL
Parameter
Min
1.0
700
50
Max
Min
12tCLCL
Max
Units
µs
Serial Port Clock Cycle Time
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
10tCLCL - 133
2tCLCL - 117
0
ns
ns
0
ns
700
10tCLCL - 133
ns
Shift Register Mode Timing Waveforms
0
1
2
3
4
5
6
7
8
INSTRUCTION
ALE
tXLXL
CLOCK
tQVXH
tXHQX
1
WRITE TO SBUF
0
2
3
4
5
6
7
tXHDX
SET TI
OUTPUT DATA
CLEAR RI
tXHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
AC Testing Input/Output Waveforms(1)
Float Waveforms(1)
VCC - 0.5V
V
OL - 0.1V
VLOAD + 0.1V
0.2 V + 0.9V
CC
Timing Reference
Points
VLOAD
Test Points
VOL + 0.1V
VLOAD - 0.1V
0.2 VCC - 0.1V
0.45V
Note:
1. AC inputs during testing are driven at VCC - 0.5V for a
logic “1” and 0.45V for a logic “0”. Timing measure-
ments are made at VIH min. for a logic “1” and VIL
max. for a logic “0”.
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
13
Ordering Information
Speed
(MHz)
Power Supply
Ordering Code
Package
Operation Range
12
2.7V to 5.5V
AT87LV51-12AC
AT87LV51-12JC
AT87LV51-12PC
44A
44J
40P6
Commercial
(0°C to 70°C)
AT87LV51-12AI
AT87LV51-12JI
AT87LV51-12PI
44A
44J
40P6
Industrial
(-40°C to 85°C)
16
2.7V to 5.5V
AT87LV51-16AC
AT87LV51-16JC
AT87LV51-16PC
44A
44J
40P6
Commercial
(0°C to 70°C)
AT87LV51-16AI
AT87LV51-16JI
AT87LV51-16PI
44A
44J
40P6
Industrial
(-40°C to 85°C)
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
40P6
40-pin, 0.600" Wide, Plastic Dull Inline Package (PDIP)
AT87LV51
14
AT87LV51
Packaging Information
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing
Quad Flat Package (TQFP)
44J, 44-lead, Plastic J-leaded Chip Carrier
(PLCC)
Dimensions in Millimeters and (Inches)*
Dimensions in Inches and (Millimeters)
.045(1.14) X 30° - 45°
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
12.21(0.478)
11.75(0.458)
.012(.305)
.008(.203)
SQ
PIN 1 ID
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
0.45(0.018)
0.30(0.012)
0.80(0.031) BSC
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
.165(4.19)
10.10(0.394)
9.90(0.386)
SQ
1.20(0.047) MAX
0
7
0.20(.008)
0.09(.003)
.022(.559) X 45° MAX (3X)
0.75(0.030) 0.15(0.006)
0.45(0.018) 0.05(0.002)
*Controlling dimension: millimeters
40P6, 40-pin, 0.600" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.161(4.09)
.125(3.18)
.022(.559)
.014(.356)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0
15
REF
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
15
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex
France
Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL (33) 4-4253-6000
FAX (33) 4-4253-6001
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1602A–04/00/xM
相关型号：
©2020 ICPDF网 联系我们和版权申明