AT89C1051-12SC [ATMEL]
8-Bit Microcontroller with 1K Byte Flash; 8 -bit微控制器1K字节的FLASH
| 型号： | AT89C1051-12SC |
| 厂家： | 
ATMEL |
| 描述： | 8-Bit Microcontroller with 1K Byte Flash |
| 文件： | 总12页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS-51™ Products
• 1K Byte of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-Level Program Memory Lock
• 64 bytes SRAM
• 15 Programmable I/O Lines
• One 16-Bit Timer/Counter
• Three Interrupt Sources
• Direct LED Drive Outputs
• On-Chip Analog Comparator
• Low Power Idle and Power Down Modes
8-Bit
Microcontroller
with 1K Byte
Flash
Description
The AT89C1051 is a low-voltage, high-performance CMOS 8-bit microcomputer with
1K byte of Flash programmable and erasable read only memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51™ instruction set. By combining
a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C1051 is a pow-
erful microcomputer which provides a highly flexible and cost effective solution to
many embedded control applications.
AT89C1051
The AT89C1051 provides the following standard features: 1K Byte of Flash, 64 bytes
of RAM, 15 I/O lines, one 16-bit timer/counter, a three vector two-level interrupt archi-
tecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addi-
tion, the AT89C1051 is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port and interrupt system to con-
tinue functioning. The Power Down Mode saves the RAM contents but freezes the
oscillator disabling all other chip functions until the next hardware reset.
Pin Configuration
PDIP/SOIC
0366D-A–12/97
4-3
Block Diagram
VCC
RAM ADDR.
REGISTER
RAM
FLASH
GND
PROGRAM
ADDRESS
REGISTER
B
STACK
POINTER
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCREMENTER
ALU
INTERRUPT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
RST
DPTR
PORT 1
LATCH
PORT 3
LATCH
ANALOG
COMPARATOR
+
-
OSC
PORT 1 DRIVERS
P1.0 - P1.7
PORT 3 DRIVERS
P3.0 - P3.5
P3.7
AT89C1051
4-4
AT89C1051
Pin Description
VCC
Supply voltage.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
GND
Ground.
Port 1
Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to
P1.7 provide internal pullups. P1.0 and P1.1 require exter-
nal pullups. P1.0 and P1.1 also serve as the positive input
(AIN0) and the negative input (AIN1), respectively, of the
on-chip precision analog comparator. The Port 1 output
buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as
inputs. When pins P1.2 to P1.7 are used as inputs and are
externally pulled low, they will source current (IIL) because
of the internal pullups.
Figure 1. Oscillator Connections
Port 1 also receives code data during Flash programming
and verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O
pins with internal pullups. P3.6 is hard-wired as an input to
the output of the on-chip comparator and is not accessible
as a general purpose I/O pin. The Port 3 output buffers can
sink 20 mA. When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as
inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C1051 as listed below:
Note:
C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Port Pin
Alternate Functions
P3.2
P3.3
P3.4
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
Figure 2. External Clock Drive Configuration
Port 3 also receives some control signals for Flash pro-
gramming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST
goes high. Holding the RST pin high for two machine cycles
while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
4-5
Restrictions on Certain Instructions
Special Function Registers
The AT89C1051 is an economical and cost-effective mem-
ber of Atmel’s growing family of microcontrollers. It con-
tains 1K byte of flash program memory. It is fully compati-
ble with the MCS-51 architecture, and can be programmed
using the MCS-51 instruction set. However, there are a
few considerations one must keep in mind when utilizing
certain instructions to program this device.
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in the table below.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
All the instructions related to jumping or branching should
be restricted such that the destination address falls within
the physical program memory space of the device, which is
1K for the AT89C1051. This should be the responsibility of
the software programmer. For example, LJMP 3FEH
would be a valid instruction for the AT89C1051 (with 1K of
memory), whereas LJMP 410H would not.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.
Table 1. AT89C1051 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0F0H
0E8H
0E0H
0D8H
0D0H
B
00000000
ACC
00000000
PSW
00000000
0C8H
0C0H
0CFH
0C7H
0B8H
0B0H
0A8H
0A0H
98H
IP
0BFH
0B7H
0AFH
0A7H
9FH
XXX00000
P3
11111111
IE
0XX00000
90H
P1
97H
11111111
88H
TCON
00000000
TMOD
00000000
TL0
00000000
TH0
00000000
8FH
87H
80H
SP
DPL
DPH
PCON
00000111
00000000
00000000
0XXX0000
AT89C1051
4-6
AT89C1051
1. Branching instructions:
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
These unconditional branching instructions will execute
correctly as long as the programmer keeps in mind that the
destination branching address must fall within the physical
boundaries of the program memory size (locations 00H to
3FFH for the 89C1051). Violating the physical space limits
may cause unknown program behavior.
P1.0 and P1.1 should be set to ‘0’ if no external pullups are
used, or set to ‘1’ if external pullups are used.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With
these conditional branching instructions the same rule
above applies. Again, violating the memory boundaries
may cause erratic execution.
It should be noted that when idle is terminated by a hard-
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
For applications involving interrupts the normal interrupt
service routine address locations of the 80C51 family archi-
tecture have been preserved.
2. MOVX-related instructions, Data Memory:
The AT89C1051 contains 64 bytes of internal data mem-
ory. Thus, in the AT89C1051 the stack depth is limited to
64 bytes, the amount of available RAM. External DATA
memory access is not supported in this device, nor is exter-
nal PROGRAM memory execution. Therefore, no MOVX
[...] instructions should be included in the program.
Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
A typical 80C51 assembler will still assemble instructions,
even if they are written in violation of the restrictions men-
tioned above. It is the responsibility of the controller user to
know the physical features and limitations of the device
being used and adjust the instructions used correspond-
ingly.
Program Memory Lock Bits
On the chip are two lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the table below:
P1.0 and P1.1 should be set to ’0’ if no external pullups are
used, or set to ’1’ if external pullups are used.
(1)
Programming The Flash
Lock Bit Protection Modes
The AT89C1051 is shipped with the 1K byte of on-chip
PEROM code memory array in the erased state (i.e., con-
tents = FFH) and ready to be programmed. The code mem-
ory array is programmed one byte at a time. Once the array
is programmed, to re-program any non-blank byte, the
entire memory array needs to be erased electrically.
Program Lock Bits
LB1
LB2
Protection Type
1
2
U
U
No program lock features.
P
U
Further programming of the Flash
is disabled.
Internal Address Counter: The AT89C1051 contains an
internal PEROM address counter which is always reset to
000H on the rising edge of RST and is advanced by apply-
ing a positive going pulse to pin XTAL1.
3
P
P
Same as mode 2, also verify is
disabled.
Note:
1. The Lock Bits can only be erased with the Chip Erase
operation.
4-7
Programming Algorithm: To program the AT89C1051,
the following sequence is recommended.
Data Polling: The AT89C1051 features Data Polling to
indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P1.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
1. Power-up sequence:
Apply power between VCC and GND pins
Set RST and XTAL1 to GND
2. Set pin RST to ‘H’
Set pin P3.2 to ‘H’
Ready/Busy: The Progress of byte programming can also
be monitored by the RDY/BSY output signal. Pin P3.1 is
pulled low after P3.2 goes High during programming to indi-
cate BUSY. P3.1 is pulled High again when programming is
done to indicate READY.
3. Apply the appropriate combination of ‘H’ or ‘L’ logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the
programming operations shown in the PEROM Pro-
gramming Modes table.
To Program and Verify the Array:
Program Verify: If lock bits LB1 and LB2 have not been
programmed code data can be read back via the data lines
for verification:
4. Apply data for Code byte at location 000H to P1.0 to
P1.7.
5. Raise RST to 12V to enable programming.
1. Reset the internal address counter to 000H by bringing
RST from ’L’ to ’H’.
2. Apply the appropriate control signals for Read Code data
and read the output data at the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address
counter.
6. Pulse P3.2 once to program a byte in the PEROM array
or the lock bits. The byte-write cycle is self-timed and
typically takes 1.2 ms.
7. To verify the programmed data, lower RST from 12V to
logic ‘H’ level and set pins P3.3 to P3.7 to the appropiate
levels. Output data can be read at the port P1 pins.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read.
The lock bits cannot be verified directly. Verification of the
lock bits is achieved by observing that their features are
enabled.
8. To program a byte at the next address location, pulse
XTAL1 pin once to advance the internal address counter.
Apply new data to the port P1 pins.
9. Repeat steps 5 through 8, changing data and advancing
the address counter for the entire 1K byte array or until
the end of the object file is reached.
10.Power-off sequence:
set XTAL1 to ‘L’
set RST to ‘L’
Turn VCC power off
Flash Programming Modes
Mode
RST/VPP
P3.2/PROG
P3.3
P3.4
P3.5
P3.7
Write Code Data(1)(3)
12V
L
H
H
H
Read Code Data(1)
Write Lock
H
H
L
L
H
H
H
H
Bit-1
Bit-2
12V
H
H
12V
12V
H
H
H
L
H
L
L
L
L
L
L
L
L
Chip Erase
(2)
Read Signature Byte
H
Note:
1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
XTAL1 pin.
2. Chip Erase requires a 10-ms PROG pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY.
AT89C1051
4-8
AT89C1051
Chip Erase: The entire PEROM array (1K byte) and the
two Lock Bits are erased electrically by using the proper
combination of control signals and by holding P3.2 low for
10 ms. The code array is written with all “1”s in the Chip
Erase operation and must be executed before any non-
blank memory byte can be re-programmed.
Programming Interface
Every code byte in the Flash array can be written and the
entire array can be erased by using the appropriate combi-
nation of control signals. The write operation cycle is self-
timed and once initiated, will automatically time itself to
completion.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 001H, and 002H, except that P3.5 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 11H indicates 89C1051
Figure 3. Programming the Flash Memory
Figure 4. Verifying the Flash Memory
5V
5V
AT89C1051
AT89C1051
VCC
VCC
RDY/BSY
PROG
P3.1
P3.2
P3.3
P3.4
P3.5
P3.7
PGM
DATA
PGM
DATA
P1
P1
VI H
P3.2
P3.3
P3.4
P3.5
P3.7
SEE FLASH
PROGRAMMING
MODES TABLE
SEE FLASH
PROGRAMMING
MODES TABLE
VI H/ VPP
XTAL1
GND
RST
VI H
XTAL1
GND
RST
TO INCREMENT
ADDRESS COUNTER
4-9
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol
VPP
Parameter
Min
Max
12.5
250
Units
V
Programming Enable Voltage
Programming Enable Current
Data Setup to PROG Low
Data Hold After PROG
P3.4 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold After PROG
11.5
IPP
µA
µs
µs
µs
µs
µs
µs
µs
µs
ns
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tELQV
tEHQZ
tGHBL
tWC
1.0
1.0
1.0
10
10
1
PROG Width
110
1.0
1.0
50
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
RDY/BSY to Increment Clock Delay
Increment Clock High
0
2.0
ms
µs
ns
tBHIH
tIHIL
Note:
1.0
200
Only used in 12-volt programming mode.
Flash Programming and Verification Waveforms
AT89C1051
4-10
AT89C1051
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature........................-55°C to +125°C
Storage Temperature ...........................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................... -1.0V to +7.0V
Maximum Operating Voltage...................................6.6V
DC Output Current ............................................25.0 mA
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol
VIL
Parameter
Condition
Min
-0.5
Max
0.2 VCC - 0.1
VCC + 0.5
VCC + 0.5
0.50
Units
Input Low Voltage
Input High Voltage
Input High Voltage
V
V
V
V
VIH
(Except XTAL1, RST)
(XTAL1, RST)
0.2 VCC + 0.9
0.7 VCC
VIH1
VOL
Output Low Voltage(1)
(Ports 1, 3)
IOL = 20 mA, VCC = 5V
I
OL = 10 mA, VCC = 2.7V
IOH = -80 µA, VCC = 5V ± 10%
OH = -30 µA
VOH
Output High Voltage
(Ports 1, 3)
2.4
V
V
I
0.75 VCC
0.9 VCC
IOH = -12 µA
V
IIL
Logical 0 Input Current
(Ports 1, 3)
VIN = 0.45V
-50
-750
±10
20
µA
ITL
Logical 1 to 0 Transition
Current (Ports 1, 3)
VIN = 2V, VCC = 5V ± 10%
0 < VIN < VCC
µA
µA
mV
V
ILI
Input Leakage Current
(Port P1.0, P1.1)
VOS
VCM
Comparator Input Offset
Voltage
VCC = 5V
Comparator Input Common
Mode Voltage
0
VCC
RRST
CIO
Reset Pulldown Resistor
Pin Capacitance
50
300
10
KΩ
pF
Test Freq. = 1 MHz, TA = 25°C
ICC
Power Supply Current
Active Mode, 12 MHz, VCC = 6V/3V
15/5.5
5/1
mA
mA
Idle Mode, 12 MHz, VCC = 6V/3V P1.0 &
P1.1 = 0V or VCC
Power Down Mode(2)
VCC = 6V P1.0 & P1.1 = 0V or VCC
100
20
µA
µA
V
CC = 3V P1.0 & P1.1 = 0V or VCC
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 20 mA
Maximum total IOL for all output pins: 80 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power Down is 2V.
4-11
External Clock Drive Waveforms
External Clock Drive
Symbol
Parameter
VCC = 2.7V to 6.0V
Min Max
12
VCC = 4.0V to 6.0V
Units
Min
0
Max
1/tCLCL
tCLCL
Oscillator Frequency
Clock Period
High Time
0
24
MHz
ns
83.3
30
41.6
15
tCHCX
tCLCX
tCLCH
tCHCL
ns
Low Time
30
15
ns
Rise Time
20
20
20
20
ns
Fall Time
ns
(1)
(1)
AC Testing Input/Output Waveforms
Float Waveforms
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for a
logic 1 and 0.45V for a logic 0. Timing measurements
are made at VIH min. for a logic 1 and VIL max. for a
logic 0.
Note:
1. For timing purposes, a port pin is no longer float-
ing when a 100 mV change load voltage occurs. A
port pin begins to float when a 100 mV change
from the loaded V /V level occurs.
OH OL
AT89C1051
4-12
AT89C1051
AT89C1051
TYPICAL ICC - ACTIVE (85°C)
20
15
10
5
Vcc=6.0V
I
C
C
Vcc=5.0V
Vcc=3.0V
m
A
0
0
6
12
18
24
FREQUENCY (MHz)
AT89C1051
TYPICAL ICC - IDLE (85°C)
3
2
1
0
Vcc=6.0V
I
C
C
Vcc=5.0V
m
A
Vcc=3.0V
0
3
6
9
12
FREQUENCY (MHz)
AT89C1051
TYPICAL ICC vs.VOLTAGE- POWER DOWN (85°C)
20
15
10
5
I
C
C
µ
A
0
3.0V
4.0V
5.0V
6.0V
Vcc VOLTAGE
Notes: 1. XTAL1 tied to GND for I
(power down)
CC
2. P.1.0 and P1.1 = V
or GND
CC
3. Lock bits programmed
4-13
Ordering Information
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
12
2.7V to 6.0V
AT89C1051-12PC
AT89C1051-12SC
20P3
20S
Commercial
(0°C to 70°C)
AT89C1051-12PI
AT89C1051-12SI
20P3
20S
Industrial
(-40°C to 85°C)
AT89C1051-12PA
AT89C1051-12SA
20P3
20S
Automotive
(-40°C to 105°C)
24
4.0V to 6.0V
AT89C1051-24PC
AT89C1051-24SC
20P3
20S
Commercial
(0°C to 70°C)
AT89C1051-24PI
AT89C1051-24SI
20P3
20S
Industrial
(-40°C to 85°C)
Package Type
20P3
20 Lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)
20 Lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)
20S
AT89C1051
4-14
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